1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "amdgpu_pm.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_common.h" 32 33 #include "vcn/vcn_1_0_offset.h" 34 #include "vcn/vcn_1_0_sh_mask.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 #include "jpeg_v1_0.h" 40 #include "vcn_v1_0.h" 41 42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 44 #define mmUVD_REG_XX_MASK_1_0 0x05ac 45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 46 47 static int vcn_v1_0_stop(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 53 int inst_idx, struct dpg_pause_state *new_state); 54 55 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 56 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); 57 58 /** 59 * vcn_v1_0_early_init - set function pointers 60 * 61 * @handle: amdgpu_device pointer 62 * 63 * Set ring and irq function pointers 64 */ 65 static int vcn_v1_0_early_init(void *handle) 66 { 67 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 68 69 adev->vcn.num_enc_rings = 2; 70 71 vcn_v1_0_set_dec_ring_funcs(adev); 72 vcn_v1_0_set_enc_ring_funcs(adev); 73 vcn_v1_0_set_irq_funcs(adev); 74 75 jpeg_v1_0_early_init(handle); 76 77 return 0; 78 } 79 80 /** 81 * vcn_v1_0_sw_init - sw init for VCN block 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Load firmware and sw initialization 86 */ 87 static int vcn_v1_0_sw_init(void *handle) 88 { 89 struct amdgpu_ring *ring; 90 int i, r; 91 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 92 93 /* VCN DEC TRAP */ 94 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 95 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 96 if (r) 97 return r; 98 99 /* VCN ENC TRAP */ 100 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 102 &adev->vcn.inst->irq); 103 if (r) 104 return r; 105 } 106 107 r = amdgpu_vcn_sw_init(adev); 108 if (r) 109 return r; 110 111 /* Override the work func */ 112 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 113 114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 115 const struct common_firmware_header *hdr; 116 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 117 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 118 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 119 adev->firmware.fw_size += 120 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 121 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 122 } 123 124 r = amdgpu_vcn_resume(adev); 125 if (r) 126 return r; 127 128 ring = &adev->vcn.inst->ring_dec; 129 sprintf(ring->name, "vcn_dec"); 130 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 131 AMDGPU_RING_PRIO_DEFAULT, NULL); 132 if (r) 133 return r; 134 135 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 136 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 137 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 138 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 139 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 140 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 141 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 142 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 143 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 144 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 145 146 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 147 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 148 149 ring = &adev->vcn.inst->ring_enc[i]; 150 sprintf(ring->name, "vcn_enc%d", i); 151 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 152 hw_prio, NULL); 153 if (r) 154 return r; 155 } 156 157 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 158 159 r = jpeg_v1_0_sw_init(handle); 160 161 return r; 162 } 163 164 /** 165 * vcn_v1_0_sw_fini - sw fini for VCN block 166 * 167 * @handle: amdgpu_device pointer 168 * 169 * VCN suspend and free up sw allocation 170 */ 171 static int vcn_v1_0_sw_fini(void *handle) 172 { 173 int r; 174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 175 176 r = amdgpu_vcn_suspend(adev); 177 if (r) 178 return r; 179 180 jpeg_v1_0_sw_fini(handle); 181 182 r = amdgpu_vcn_sw_fini(adev); 183 184 return r; 185 } 186 187 /** 188 * vcn_v1_0_hw_init - start and test VCN block 189 * 190 * @handle: amdgpu_device pointer 191 * 192 * Initialize the hardware, boot up the VCPU and do some testing 193 */ 194 static int vcn_v1_0_hw_init(void *handle) 195 { 196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 197 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 198 int i, r; 199 200 r = amdgpu_ring_test_helper(ring); 201 if (r) 202 goto done; 203 204 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 205 ring = &adev->vcn.inst->ring_enc[i]; 206 r = amdgpu_ring_test_helper(ring); 207 if (r) 208 goto done; 209 } 210 211 ring = &adev->jpeg.inst->ring_dec; 212 r = amdgpu_ring_test_helper(ring); 213 if (r) 214 goto done; 215 216 done: 217 if (!r) 218 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 219 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 220 221 return r; 222 } 223 224 /** 225 * vcn_v1_0_hw_fini - stop the hardware block 226 * 227 * @handle: amdgpu_device pointer 228 * 229 * Stop the VCN block, mark ring as not ready any more 230 */ 231 static int vcn_v1_0_hw_fini(void *handle) 232 { 233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 234 235 cancel_delayed_work_sync(&adev->vcn.idle_work); 236 237 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 238 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 239 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { 240 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 241 } 242 243 return 0; 244 } 245 246 /** 247 * vcn_v1_0_suspend - suspend VCN block 248 * 249 * @handle: amdgpu_device pointer 250 * 251 * HW fini and suspend VCN block 252 */ 253 static int vcn_v1_0_suspend(void *handle) 254 { 255 int r; 256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 257 258 r = vcn_v1_0_hw_fini(adev); 259 if (r) 260 return r; 261 262 r = amdgpu_vcn_suspend(adev); 263 264 return r; 265 } 266 267 /** 268 * vcn_v1_0_resume - resume VCN block 269 * 270 * @handle: amdgpu_device pointer 271 * 272 * Resume firmware and hw init VCN block 273 */ 274 static int vcn_v1_0_resume(void *handle) 275 { 276 int r; 277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 278 279 r = amdgpu_vcn_resume(adev); 280 if (r) 281 return r; 282 283 r = vcn_v1_0_hw_init(adev); 284 285 return r; 286 } 287 288 /** 289 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 290 * 291 * @adev: amdgpu_device pointer 292 * 293 * Let the VCN memory controller know it's offsets 294 */ 295 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 296 { 297 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 298 uint32_t offset; 299 300 /* cache window 0: fw */ 301 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 302 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 303 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 304 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 305 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 306 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 307 offset = 0; 308 } else { 309 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 310 lower_32_bits(adev->vcn.inst->gpu_addr)); 311 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 312 upper_32_bits(adev->vcn.inst->gpu_addr)); 313 offset = size; 314 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 315 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 316 } 317 318 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 319 320 /* cache window 1: stack */ 321 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 322 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 324 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 325 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 326 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 327 328 /* cache window 2: context */ 329 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 330 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 331 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 332 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 333 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 334 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 335 336 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 337 adev->gfx.config.gb_addr_config); 338 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 343 adev->gfx.config.gb_addr_config); 344 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 345 adev->gfx.config.gb_addr_config); 346 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 347 adev->gfx.config.gb_addr_config); 348 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 349 adev->gfx.config.gb_addr_config); 350 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 351 adev->gfx.config.gb_addr_config); 352 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 353 adev->gfx.config.gb_addr_config); 354 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 355 adev->gfx.config.gb_addr_config); 356 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 357 adev->gfx.config.gb_addr_config); 358 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 359 adev->gfx.config.gb_addr_config); 360 } 361 362 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 363 { 364 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 365 uint32_t offset; 366 367 /* cache window 0: fw */ 368 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 369 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 370 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 371 0xFFFFFFFF, 0); 372 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 373 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 374 0xFFFFFFFF, 0); 375 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 376 0xFFFFFFFF, 0); 377 offset = 0; 378 } else { 379 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 380 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 381 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 382 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 383 offset = size; 384 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 385 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 386 } 387 388 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 389 390 /* cache window 1: stack */ 391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 392 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 393 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 394 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 395 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 396 0xFFFFFFFF, 0); 397 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 398 0xFFFFFFFF, 0); 399 400 /* cache window 2: context */ 401 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 402 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 403 0xFFFFFFFF, 0); 404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 405 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 406 0xFFFFFFFF, 0); 407 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 408 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 409 0xFFFFFFFF, 0); 410 411 /* VCN global tiling registers */ 412 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 413 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 414 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 416 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 417 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 418 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 419 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 421 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 422 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 423 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 424 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 425 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 426 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 427 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 428 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 429 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 430 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 431 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 432 } 433 434 /** 435 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 436 * 437 * @adev: amdgpu_device pointer 438 * 439 * Disable clock gating for VCN block 440 */ 441 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 442 { 443 uint32_t data; 444 445 /* JPEG disable CGC */ 446 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 447 448 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 449 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 450 else 451 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 452 453 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 454 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 455 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 456 457 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 458 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 459 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 460 461 /* UVD disable CGC */ 462 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 463 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 464 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 465 else 466 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 467 468 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 469 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 470 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 471 472 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 473 data &= ~(UVD_CGC_GATE__SYS_MASK 474 | UVD_CGC_GATE__UDEC_MASK 475 | UVD_CGC_GATE__MPEG2_MASK 476 | UVD_CGC_GATE__REGS_MASK 477 | UVD_CGC_GATE__RBC_MASK 478 | UVD_CGC_GATE__LMI_MC_MASK 479 | UVD_CGC_GATE__LMI_UMC_MASK 480 | UVD_CGC_GATE__IDCT_MASK 481 | UVD_CGC_GATE__MPRD_MASK 482 | UVD_CGC_GATE__MPC_MASK 483 | UVD_CGC_GATE__LBSI_MASK 484 | UVD_CGC_GATE__LRBBM_MASK 485 | UVD_CGC_GATE__UDEC_RE_MASK 486 | UVD_CGC_GATE__UDEC_CM_MASK 487 | UVD_CGC_GATE__UDEC_IT_MASK 488 | UVD_CGC_GATE__UDEC_DB_MASK 489 | UVD_CGC_GATE__UDEC_MP_MASK 490 | UVD_CGC_GATE__WCB_MASK 491 | UVD_CGC_GATE__VCPU_MASK 492 | UVD_CGC_GATE__SCPU_MASK); 493 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 494 495 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 496 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 497 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 498 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 499 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 500 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 501 | UVD_CGC_CTRL__SYS_MODE_MASK 502 | UVD_CGC_CTRL__UDEC_MODE_MASK 503 | UVD_CGC_CTRL__MPEG2_MODE_MASK 504 | UVD_CGC_CTRL__REGS_MODE_MASK 505 | UVD_CGC_CTRL__RBC_MODE_MASK 506 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 507 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 508 | UVD_CGC_CTRL__IDCT_MODE_MASK 509 | UVD_CGC_CTRL__MPRD_MODE_MASK 510 | UVD_CGC_CTRL__MPC_MODE_MASK 511 | UVD_CGC_CTRL__LBSI_MODE_MASK 512 | UVD_CGC_CTRL__LRBBM_MODE_MASK 513 | UVD_CGC_CTRL__WCB_MODE_MASK 514 | UVD_CGC_CTRL__VCPU_MODE_MASK 515 | UVD_CGC_CTRL__SCPU_MODE_MASK); 516 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 517 518 /* turn on */ 519 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 520 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 521 | UVD_SUVD_CGC_GATE__SIT_MASK 522 | UVD_SUVD_CGC_GATE__SMP_MASK 523 | UVD_SUVD_CGC_GATE__SCM_MASK 524 | UVD_SUVD_CGC_GATE__SDB_MASK 525 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 526 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 527 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 528 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 529 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 530 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 531 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 532 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 533 | UVD_SUVD_CGC_GATE__SCLR_MASK 534 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 535 | UVD_SUVD_CGC_GATE__ENT_MASK 536 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 537 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 538 | UVD_SUVD_CGC_GATE__SITE_MASK 539 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 540 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 541 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 542 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 543 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 544 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 545 546 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 547 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 548 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 549 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 550 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 551 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 552 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 553 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 554 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 555 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 556 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 557 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 558 } 559 560 /** 561 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 562 * 563 * @adev: amdgpu_device pointer 564 * 565 * Enable clock gating for VCN block 566 */ 567 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 568 { 569 uint32_t data = 0; 570 571 /* enable JPEG CGC */ 572 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 573 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 574 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 575 else 576 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 577 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 578 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 579 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 580 581 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 582 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 583 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 584 585 /* enable UVD CGC */ 586 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 587 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 588 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 589 else 590 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 591 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 592 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 593 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 594 595 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 596 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 597 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 598 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 599 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 600 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 601 | UVD_CGC_CTRL__SYS_MODE_MASK 602 | UVD_CGC_CTRL__UDEC_MODE_MASK 603 | UVD_CGC_CTRL__MPEG2_MODE_MASK 604 | UVD_CGC_CTRL__REGS_MODE_MASK 605 | UVD_CGC_CTRL__RBC_MODE_MASK 606 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 607 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 608 | UVD_CGC_CTRL__IDCT_MODE_MASK 609 | UVD_CGC_CTRL__MPRD_MODE_MASK 610 | UVD_CGC_CTRL__MPC_MODE_MASK 611 | UVD_CGC_CTRL__LBSI_MODE_MASK 612 | UVD_CGC_CTRL__LRBBM_MODE_MASK 613 | UVD_CGC_CTRL__WCB_MODE_MASK 614 | UVD_CGC_CTRL__VCPU_MODE_MASK 615 | UVD_CGC_CTRL__SCPU_MODE_MASK); 616 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 617 618 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 619 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 620 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 621 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 622 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 623 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 624 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 625 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 626 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 627 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 628 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 629 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 630 } 631 632 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 633 { 634 uint32_t reg_data = 0; 635 636 /* disable JPEG CGC */ 637 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 638 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 639 else 640 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 641 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 642 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 643 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 644 645 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 646 647 /* enable sw clock gating control */ 648 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 649 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 650 else 651 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 652 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 653 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 654 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 655 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 656 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 657 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 658 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 659 UVD_CGC_CTRL__SYS_MODE_MASK | 660 UVD_CGC_CTRL__UDEC_MODE_MASK | 661 UVD_CGC_CTRL__MPEG2_MODE_MASK | 662 UVD_CGC_CTRL__REGS_MODE_MASK | 663 UVD_CGC_CTRL__RBC_MODE_MASK | 664 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 665 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 666 UVD_CGC_CTRL__IDCT_MODE_MASK | 667 UVD_CGC_CTRL__MPRD_MODE_MASK | 668 UVD_CGC_CTRL__MPC_MODE_MASK | 669 UVD_CGC_CTRL__LBSI_MODE_MASK | 670 UVD_CGC_CTRL__LRBBM_MODE_MASK | 671 UVD_CGC_CTRL__WCB_MODE_MASK | 672 UVD_CGC_CTRL__VCPU_MODE_MASK | 673 UVD_CGC_CTRL__SCPU_MODE_MASK); 674 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 675 676 /* turn off clock gating */ 677 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 678 679 /* turn on SUVD clock gating */ 680 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 681 682 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 683 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 684 } 685 686 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 687 { 688 uint32_t data = 0; 689 690 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 691 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 692 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 693 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 694 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 695 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 696 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 697 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 698 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 699 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 700 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 701 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 702 703 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 704 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); 705 } else { 706 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 709 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 710 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 711 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 712 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 713 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 714 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 715 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 716 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 717 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 718 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); 719 } 720 721 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 722 723 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 724 data &= ~0x103; 725 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 726 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 727 728 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 729 } 730 731 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 732 { 733 uint32_t data = 0; 734 735 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 736 /* Before power off, this indicator has to be turned on */ 737 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 738 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 739 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 740 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 741 742 743 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 746 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 747 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 748 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 749 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 750 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 751 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 752 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 753 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 754 755 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 756 757 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 760 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 761 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 762 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 763 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 764 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 765 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 766 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 767 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 768 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); 769 } 770 } 771 772 /** 773 * vcn_v1_0_start_spg_mode - start VCN block 774 * 775 * @adev: amdgpu_device pointer 776 * 777 * Setup and start the VCN block 778 */ 779 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 780 { 781 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 782 uint32_t rb_bufsz, tmp; 783 uint32_t lmi_swap_cntl; 784 int i, j, r; 785 786 /* disable byte swapping */ 787 lmi_swap_cntl = 0; 788 789 vcn_1_0_disable_static_power_gating(adev); 790 791 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 792 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 793 794 /* disable clock gating */ 795 vcn_v1_0_disable_clock_gating(adev); 796 797 /* disable interupt */ 798 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 799 ~UVD_MASTINT_EN__VCPU_EN_MASK); 800 801 /* initialize VCN memory controller */ 802 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 803 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 804 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 805 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 806 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 807 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 808 809 #ifdef __BIG_ENDIAN 810 /* swap (8 in 32) RB and IB */ 811 lmi_swap_cntl = 0xa; 812 #endif 813 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 814 815 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 816 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 817 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 818 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 819 820 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 821 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 822 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 823 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 824 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 825 826 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 827 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 828 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 829 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 830 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 831 832 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 833 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 834 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 835 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 836 837 vcn_v1_0_mc_resume_spg_mode(adev); 838 839 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 840 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 841 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 842 843 /* enable VCPU clock */ 844 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 845 846 /* boot up the VCPU */ 847 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 848 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 849 850 /* enable UMC */ 851 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 852 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 853 854 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 855 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 856 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 857 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 858 859 for (i = 0; i < 10; ++i) { 860 uint32_t status; 861 862 for (j = 0; j < 100; ++j) { 863 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 864 if (status & UVD_STATUS__IDLE) 865 break; 866 mdelay(10); 867 } 868 r = 0; 869 if (status & UVD_STATUS__IDLE) 870 break; 871 872 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 873 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 874 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 875 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 876 mdelay(10); 877 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 878 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 879 mdelay(10); 880 r = -1; 881 } 882 883 if (r) { 884 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 885 return r; 886 } 887 /* enable master interrupt */ 888 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 889 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 890 891 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 892 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 893 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 894 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 895 896 /* clear the busy bit of UVD_STATUS */ 897 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 898 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 899 900 /* force RBC into idle state */ 901 rb_bufsz = order_base_2(ring->ring_size); 902 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 903 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 904 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 905 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 906 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 907 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 908 909 /* set the write pointer delay */ 910 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 911 912 /* set the wb address */ 913 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 914 (upper_32_bits(ring->gpu_addr) >> 2)); 915 916 /* program the RB_BASE for ring buffer */ 917 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 918 lower_32_bits(ring->gpu_addr)); 919 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 920 upper_32_bits(ring->gpu_addr)); 921 922 /* Initialize the ring buffer's read and write pointers */ 923 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 924 925 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 926 927 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 928 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 929 lower_32_bits(ring->wptr)); 930 931 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 932 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 933 934 ring = &adev->vcn.inst->ring_enc[0]; 935 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 936 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 937 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 938 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 939 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 940 941 ring = &adev->vcn.inst->ring_enc[1]; 942 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 943 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 944 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 945 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 946 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 947 948 jpeg_v1_0_start(adev, 0); 949 950 return 0; 951 } 952 953 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 954 { 955 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 956 uint32_t rb_bufsz, tmp; 957 uint32_t lmi_swap_cntl; 958 959 /* disable byte swapping */ 960 lmi_swap_cntl = 0; 961 962 vcn_1_0_enable_static_power_gating(adev); 963 964 /* enable dynamic power gating mode */ 965 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 966 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 967 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 968 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 969 970 /* enable clock gating */ 971 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 972 973 /* enable VCPU clock */ 974 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 975 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 976 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 977 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 978 979 /* disable interupt */ 980 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 981 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 982 983 /* initialize VCN memory controller */ 984 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 985 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 986 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 987 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 988 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 989 UVD_LMI_CTRL__REQ_MODE_MASK | 990 UVD_LMI_CTRL__CRC_RESET_MASK | 991 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 992 0x00100000L, 0xFFFFFFFF, 0); 993 994 #ifdef __BIG_ENDIAN 995 /* swap (8 in 32) RB and IB */ 996 lmi_swap_cntl = 0xa; 997 #endif 998 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 999 1000 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, 1001 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1002 1003 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, 1004 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1005 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1006 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1007 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1008 1009 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, 1010 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1011 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1012 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1013 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1014 1015 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, 1016 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1017 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1018 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1019 1020 vcn_v1_0_mc_resume_dpg_mode(adev); 1021 1022 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1023 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1024 1025 /* boot up the VCPU */ 1026 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1027 1028 /* enable UMC */ 1029 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, 1030 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1031 0xFFFFFFFF, 0); 1032 1033 /* enable master interrupt */ 1034 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 1035 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1036 1037 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1038 /* setup mmUVD_LMI_CTRL */ 1039 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1040 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1041 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1042 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1043 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1044 UVD_LMI_CTRL__REQ_MODE_MASK | 1045 UVD_LMI_CTRL__CRC_RESET_MASK | 1046 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1047 0x00100000L, 0xFFFFFFFF, 1); 1048 1049 tmp = adev->gfx.config.gb_addr_config; 1050 /* setup VCN global tiling registers */ 1051 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1052 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1053 1054 /* enable System Interrupt for JRBC */ 1055 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, 1056 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1057 1058 /* force RBC into idle state */ 1059 rb_bufsz = order_base_2(ring->ring_size); 1060 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1065 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1066 1067 /* set the write pointer delay */ 1068 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1069 1070 /* set the wb address */ 1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1072 (upper_32_bits(ring->gpu_addr) >> 2)); 1073 1074 /* program the RB_BASE for ring buffer */ 1075 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1076 lower_32_bits(ring->gpu_addr)); 1077 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1078 upper_32_bits(ring->gpu_addr)); 1079 1080 /* Initialize the ring buffer's read and write pointers */ 1081 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1082 1083 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1084 1085 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1086 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1087 lower_32_bits(ring->wptr)); 1088 1089 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1090 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1091 1092 jpeg_v1_0_start(adev, 1); 1093 1094 return 0; 1095 } 1096 1097 static int vcn_v1_0_start(struct amdgpu_device *adev) 1098 { 1099 int r; 1100 1101 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1102 r = vcn_v1_0_start_dpg_mode(adev); 1103 else 1104 r = vcn_v1_0_start_spg_mode(adev); 1105 return r; 1106 } 1107 1108 /** 1109 * vcn_v1_0_stop_spg_mode - stop VCN block 1110 * 1111 * @adev: amdgpu_device pointer 1112 * 1113 * stop the VCN block 1114 */ 1115 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1116 { 1117 int tmp; 1118 1119 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1120 1121 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1122 UVD_LMI_STATUS__READ_CLEAN_MASK | 1123 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1124 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1125 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1126 1127 /* stall UMC channel */ 1128 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1129 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1130 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1131 1132 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1133 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1134 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1135 1136 /* disable VCPU clock */ 1137 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1138 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1139 1140 /* reset LMI UMC/LMI */ 1141 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1142 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1143 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1144 1145 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1146 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1147 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1148 1149 /* put VCPU into reset */ 1150 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1151 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1152 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1153 1154 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1155 1156 vcn_v1_0_enable_clock_gating(adev); 1157 vcn_1_0_enable_static_power_gating(adev); 1158 return 0; 1159 } 1160 1161 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1162 { 1163 uint32_t tmp; 1164 1165 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1166 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1167 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1168 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1169 1170 /* wait for read ptr to be equal to write ptr */ 1171 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1172 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1173 1174 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1175 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1176 1177 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1178 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); 1179 1180 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1181 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1182 1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1184 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1185 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1186 1187 /* disable dynamic power gating mode */ 1188 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1189 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1190 1191 return 0; 1192 } 1193 1194 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1195 { 1196 int r; 1197 1198 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1199 r = vcn_v1_0_stop_dpg_mode(adev); 1200 else 1201 r = vcn_v1_0_stop_spg_mode(adev); 1202 1203 return r; 1204 } 1205 1206 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1207 int inst_idx, struct dpg_pause_state *new_state) 1208 { 1209 int ret_code; 1210 uint32_t reg_data = 0; 1211 uint32_t reg_data2 = 0; 1212 struct amdgpu_ring *ring; 1213 1214 /* pause/unpause if state is changed */ 1215 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1216 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1217 adev->vcn.inst[inst_idx].pause_state.fw_based, 1218 adev->vcn.inst[inst_idx].pause_state.jpeg, 1219 new_state->fw_based, new_state->jpeg); 1220 1221 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1222 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1223 1224 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1225 ret_code = 0; 1226 1227 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1228 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1229 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1230 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1231 1232 if (!ret_code) { 1233 /* pause DPG non-jpeg */ 1234 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1235 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1236 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1237 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1238 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1239 1240 /* Restore */ 1241 ring = &adev->vcn.inst->ring_enc[0]; 1242 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1247 1248 ring = &adev->vcn.inst->ring_enc[1]; 1249 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1250 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1251 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1252 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1253 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1254 1255 ring = &adev->vcn.inst->ring_dec; 1256 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1257 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1258 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1259 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1260 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1261 } 1262 } else { 1263 /* unpause dpg non-jpeg, no need to wait */ 1264 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1265 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1266 } 1267 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1268 } 1269 1270 /* pause/unpause if state is changed */ 1271 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1272 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1273 adev->vcn.inst[inst_idx].pause_state.fw_based, 1274 adev->vcn.inst[inst_idx].pause_state.jpeg, 1275 new_state->fw_based, new_state->jpeg); 1276 1277 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1278 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1279 1280 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1281 ret_code = 0; 1282 1283 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1284 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1285 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1286 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1287 1288 if (!ret_code) { 1289 /* Make sure JPRG Snoop is disabled before sending the pause */ 1290 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1291 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1292 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1293 1294 /* pause DPG jpeg */ 1295 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1296 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1297 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1298 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1299 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1300 1301 /* Restore */ 1302 ring = &adev->jpeg.inst->ring_dec; 1303 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1304 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1305 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1306 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1307 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1308 lower_32_bits(ring->gpu_addr)); 1309 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1310 upper_32_bits(ring->gpu_addr)); 1311 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1312 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1313 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1314 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1315 1316 ring = &adev->vcn.inst->ring_dec; 1317 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1318 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1319 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1320 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1321 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1322 } 1323 } else { 1324 /* unpause dpg jpeg, no need to wait */ 1325 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1326 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1327 } 1328 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1329 } 1330 1331 return 0; 1332 } 1333 1334 static bool vcn_v1_0_is_idle(void *handle) 1335 { 1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1337 1338 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1339 } 1340 1341 static int vcn_v1_0_wait_for_idle(void *handle) 1342 { 1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1344 int ret; 1345 1346 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1347 UVD_STATUS__IDLE); 1348 1349 return ret; 1350 } 1351 1352 static int vcn_v1_0_set_clockgating_state(void *handle, 1353 enum amd_clockgating_state state) 1354 { 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 bool enable = (state == AMD_CG_STATE_GATE); 1357 1358 if (enable) { 1359 /* wait for STATUS to clear */ 1360 if (!vcn_v1_0_is_idle(handle)) 1361 return -EBUSY; 1362 vcn_v1_0_enable_clock_gating(adev); 1363 } else { 1364 /* disable HW gating and enable Sw gating */ 1365 vcn_v1_0_disable_clock_gating(adev); 1366 } 1367 return 0; 1368 } 1369 1370 /** 1371 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1372 * 1373 * @ring: amdgpu_ring pointer 1374 * 1375 * Returns the current hardware read pointer 1376 */ 1377 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1378 { 1379 struct amdgpu_device *adev = ring->adev; 1380 1381 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1382 } 1383 1384 /** 1385 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1386 * 1387 * @ring: amdgpu_ring pointer 1388 * 1389 * Returns the current hardware write pointer 1390 */ 1391 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1392 { 1393 struct amdgpu_device *adev = ring->adev; 1394 1395 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1396 } 1397 1398 /** 1399 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1400 * 1401 * @ring: amdgpu_ring pointer 1402 * 1403 * Commits the write pointer to the hardware 1404 */ 1405 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1406 { 1407 struct amdgpu_device *adev = ring->adev; 1408 1409 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1410 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1411 lower_32_bits(ring->wptr) | 0x80000000); 1412 1413 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1414 } 1415 1416 /** 1417 * vcn_v1_0_dec_ring_insert_start - insert a start command 1418 * 1419 * @ring: amdgpu_ring pointer 1420 * 1421 * Write a start command to the ring. 1422 */ 1423 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1424 { 1425 struct amdgpu_device *adev = ring->adev; 1426 1427 amdgpu_ring_write(ring, 1428 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1429 amdgpu_ring_write(ring, 0); 1430 amdgpu_ring_write(ring, 1431 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1432 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1433 } 1434 1435 /** 1436 * vcn_v1_0_dec_ring_insert_end - insert a end command 1437 * 1438 * @ring: amdgpu_ring pointer 1439 * 1440 * Write a end command to the ring. 1441 */ 1442 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1443 { 1444 struct amdgpu_device *adev = ring->adev; 1445 1446 amdgpu_ring_write(ring, 1447 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1448 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1449 } 1450 1451 /** 1452 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1453 * 1454 * @ring: amdgpu_ring pointer 1455 * @addr: address 1456 * @seq: sequence number 1457 * @flags: fence related flags 1458 * 1459 * Write a fence and a trap command to the ring. 1460 */ 1461 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1462 unsigned flags) 1463 { 1464 struct amdgpu_device *adev = ring->adev; 1465 1466 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1467 1468 amdgpu_ring_write(ring, 1469 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1470 amdgpu_ring_write(ring, seq); 1471 amdgpu_ring_write(ring, 1472 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1473 amdgpu_ring_write(ring, addr & 0xffffffff); 1474 amdgpu_ring_write(ring, 1475 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1476 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1477 amdgpu_ring_write(ring, 1478 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1479 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1480 1481 amdgpu_ring_write(ring, 1482 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1483 amdgpu_ring_write(ring, 0); 1484 amdgpu_ring_write(ring, 1485 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1486 amdgpu_ring_write(ring, 0); 1487 amdgpu_ring_write(ring, 1488 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1489 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1490 } 1491 1492 /** 1493 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1494 * 1495 * @ring: amdgpu_ring pointer 1496 * @job: job to retrieve vmid from 1497 * @ib: indirect buffer to execute 1498 * @flags: unused 1499 * 1500 * Write ring commands to execute the indirect buffer 1501 */ 1502 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1503 struct amdgpu_job *job, 1504 struct amdgpu_ib *ib, 1505 uint32_t flags) 1506 { 1507 struct amdgpu_device *adev = ring->adev; 1508 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1509 1510 amdgpu_ring_write(ring, 1511 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1512 amdgpu_ring_write(ring, vmid); 1513 1514 amdgpu_ring_write(ring, 1515 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1516 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1517 amdgpu_ring_write(ring, 1518 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1519 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1520 amdgpu_ring_write(ring, 1521 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1522 amdgpu_ring_write(ring, ib->length_dw); 1523 } 1524 1525 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1526 uint32_t reg, uint32_t val, 1527 uint32_t mask) 1528 { 1529 struct amdgpu_device *adev = ring->adev; 1530 1531 amdgpu_ring_write(ring, 1532 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1533 amdgpu_ring_write(ring, reg << 2); 1534 amdgpu_ring_write(ring, 1535 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1536 amdgpu_ring_write(ring, val); 1537 amdgpu_ring_write(ring, 1538 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1539 amdgpu_ring_write(ring, mask); 1540 amdgpu_ring_write(ring, 1541 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1542 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1543 } 1544 1545 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1546 unsigned vmid, uint64_t pd_addr) 1547 { 1548 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1549 uint32_t data0, data1, mask; 1550 1551 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1552 1553 /* wait for register write */ 1554 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1555 data1 = lower_32_bits(pd_addr); 1556 mask = 0xffffffff; 1557 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1558 } 1559 1560 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1561 uint32_t reg, uint32_t val) 1562 { 1563 struct amdgpu_device *adev = ring->adev; 1564 1565 amdgpu_ring_write(ring, 1566 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1567 amdgpu_ring_write(ring, reg << 2); 1568 amdgpu_ring_write(ring, 1569 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1570 amdgpu_ring_write(ring, val); 1571 amdgpu_ring_write(ring, 1572 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1573 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1574 } 1575 1576 /** 1577 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1578 * 1579 * @ring: amdgpu_ring pointer 1580 * 1581 * Returns the current hardware enc read pointer 1582 */ 1583 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1584 { 1585 struct amdgpu_device *adev = ring->adev; 1586 1587 if (ring == &adev->vcn.inst->ring_enc[0]) 1588 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1589 else 1590 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1591 } 1592 1593 /** 1594 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1595 * 1596 * @ring: amdgpu_ring pointer 1597 * 1598 * Returns the current hardware enc write pointer 1599 */ 1600 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1601 { 1602 struct amdgpu_device *adev = ring->adev; 1603 1604 if (ring == &adev->vcn.inst->ring_enc[0]) 1605 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1606 else 1607 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1608 } 1609 1610 /** 1611 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1612 * 1613 * @ring: amdgpu_ring pointer 1614 * 1615 * Commits the enc write pointer to the hardware 1616 */ 1617 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1618 { 1619 struct amdgpu_device *adev = ring->adev; 1620 1621 if (ring == &adev->vcn.inst->ring_enc[0]) 1622 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1623 lower_32_bits(ring->wptr)); 1624 else 1625 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1626 lower_32_bits(ring->wptr)); 1627 } 1628 1629 /** 1630 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1631 * 1632 * @ring: amdgpu_ring pointer 1633 * @addr: address 1634 * @seq: sequence number 1635 * @flags: fence related flags 1636 * 1637 * Write enc a fence and a trap command to the ring. 1638 */ 1639 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1640 u64 seq, unsigned flags) 1641 { 1642 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1643 1644 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1645 amdgpu_ring_write(ring, addr); 1646 amdgpu_ring_write(ring, upper_32_bits(addr)); 1647 amdgpu_ring_write(ring, seq); 1648 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1649 } 1650 1651 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1652 { 1653 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1654 } 1655 1656 /** 1657 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1658 * 1659 * @ring: amdgpu_ring pointer 1660 * @job: job to retrive vmid from 1661 * @ib: indirect buffer to execute 1662 * @flags: unused 1663 * 1664 * Write enc ring commands to execute the indirect buffer 1665 */ 1666 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1667 struct amdgpu_job *job, 1668 struct amdgpu_ib *ib, 1669 uint32_t flags) 1670 { 1671 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1672 1673 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1674 amdgpu_ring_write(ring, vmid); 1675 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1676 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1677 amdgpu_ring_write(ring, ib->length_dw); 1678 } 1679 1680 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1681 uint32_t reg, uint32_t val, 1682 uint32_t mask) 1683 { 1684 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1685 amdgpu_ring_write(ring, reg << 2); 1686 amdgpu_ring_write(ring, mask); 1687 amdgpu_ring_write(ring, val); 1688 } 1689 1690 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1691 unsigned int vmid, uint64_t pd_addr) 1692 { 1693 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1694 1695 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1696 1697 /* wait for reg writes */ 1698 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1699 vmid * hub->ctx_addr_distance, 1700 lower_32_bits(pd_addr), 0xffffffff); 1701 } 1702 1703 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1704 uint32_t reg, uint32_t val) 1705 { 1706 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1707 amdgpu_ring_write(ring, reg << 2); 1708 amdgpu_ring_write(ring, val); 1709 } 1710 1711 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1712 struct amdgpu_irq_src *source, 1713 unsigned type, 1714 enum amdgpu_interrupt_state state) 1715 { 1716 return 0; 1717 } 1718 1719 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1720 struct amdgpu_irq_src *source, 1721 struct amdgpu_iv_entry *entry) 1722 { 1723 DRM_DEBUG("IH: VCN TRAP\n"); 1724 1725 switch (entry->src_id) { 1726 case 124: 1727 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1728 break; 1729 case 119: 1730 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1731 break; 1732 case 120: 1733 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1734 break; 1735 default: 1736 DRM_ERROR("Unhandled interrupt: %d %d\n", 1737 entry->src_id, entry->src_data[0]); 1738 break; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1745 { 1746 struct amdgpu_device *adev = ring->adev; 1747 int i; 1748 1749 WARN_ON(ring->wptr % 2 || count % 2); 1750 1751 for (i = 0; i < count / 2; i++) { 1752 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1753 amdgpu_ring_write(ring, 0); 1754 } 1755 } 1756 1757 static int vcn_v1_0_set_powergating_state(void *handle, 1758 enum amd_powergating_state state) 1759 { 1760 /* This doesn't actually powergate the VCN block. 1761 * That's done in the dpm code via the SMC. This 1762 * just re-inits the block as necessary. The actual 1763 * gating still happens in the dpm code. We should 1764 * revisit this when there is a cleaner line between 1765 * the smc and the hw blocks 1766 */ 1767 int ret; 1768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1769 1770 if(state == adev->vcn.cur_state) 1771 return 0; 1772 1773 if (state == AMD_PG_STATE_GATE) 1774 ret = vcn_v1_0_stop(adev); 1775 else 1776 ret = vcn_v1_0_start(adev); 1777 1778 if(!ret) 1779 adev->vcn.cur_state = state; 1780 return ret; 1781 } 1782 1783 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1784 { 1785 struct amdgpu_device *adev = 1786 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1787 unsigned int fences = 0, i; 1788 1789 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1790 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1791 1792 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1793 struct dpg_pause_state new_state; 1794 1795 if (fences) 1796 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1797 else 1798 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1799 1800 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1801 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1802 else 1803 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1804 1805 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1806 } 1807 1808 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1809 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1810 1811 if (fences == 0) { 1812 amdgpu_gfx_off_ctrl(adev, true); 1813 if (adev->pm.dpm_enabled) 1814 amdgpu_dpm_enable_uvd(adev, false); 1815 else 1816 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1817 AMD_PG_STATE_GATE); 1818 } else { 1819 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1820 } 1821 } 1822 1823 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1824 { 1825 struct amdgpu_device *adev = ring->adev; 1826 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1827 1828 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround); 1829 1830 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec)) 1831 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n"); 1832 1833 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks); 1834 1835 } 1836 1837 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) 1838 { 1839 struct amdgpu_device *adev = ring->adev; 1840 1841 if (set_clocks) { 1842 amdgpu_gfx_off_ctrl(adev, false); 1843 if (adev->pm.dpm_enabled) 1844 amdgpu_dpm_enable_uvd(adev, true); 1845 else 1846 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1847 AMD_PG_STATE_UNGATE); 1848 } 1849 1850 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1851 struct dpg_pause_state new_state; 1852 unsigned int fences = 0, i; 1853 1854 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1855 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1856 1857 if (fences) 1858 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1859 else 1860 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1861 1862 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1863 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1864 else 1865 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1866 1867 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1868 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1869 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1870 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1871 1872 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1873 } 1874 } 1875 1876 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) 1877 { 1878 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1879 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); 1880 } 1881 1882 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1883 .name = "vcn_v1_0", 1884 .early_init = vcn_v1_0_early_init, 1885 .late_init = NULL, 1886 .sw_init = vcn_v1_0_sw_init, 1887 .sw_fini = vcn_v1_0_sw_fini, 1888 .hw_init = vcn_v1_0_hw_init, 1889 .hw_fini = vcn_v1_0_hw_fini, 1890 .suspend = vcn_v1_0_suspend, 1891 .resume = vcn_v1_0_resume, 1892 .is_idle = vcn_v1_0_is_idle, 1893 .wait_for_idle = vcn_v1_0_wait_for_idle, 1894 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1895 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1896 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1897 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1898 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1899 .set_powergating_state = vcn_v1_0_set_powergating_state, 1900 }; 1901 1902 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1903 .type = AMDGPU_RING_TYPE_VCN_DEC, 1904 .align_mask = 0xf, 1905 .support_64bit_ptrs = false, 1906 .no_user_fence = true, 1907 .vmhub = AMDGPU_MMHUB_0, 1908 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1909 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1910 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1911 .emit_frame_size = 1912 6 + 6 + /* hdp invalidate / flush */ 1913 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1914 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1915 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1916 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1917 6, 1918 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1919 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1920 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1921 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1922 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1923 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1924 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1925 .insert_start = vcn_v1_0_dec_ring_insert_start, 1926 .insert_end = vcn_v1_0_dec_ring_insert_end, 1927 .pad_ib = amdgpu_ring_generic_pad_ib, 1928 .begin_use = vcn_v1_0_ring_begin_use, 1929 .end_use = vcn_v1_0_ring_end_use, 1930 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1931 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1932 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1933 }; 1934 1935 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1936 .type = AMDGPU_RING_TYPE_VCN_ENC, 1937 .align_mask = 0x3f, 1938 .nop = VCN_ENC_CMD_NO_OP, 1939 .support_64bit_ptrs = false, 1940 .no_user_fence = true, 1941 .vmhub = AMDGPU_MMHUB_0, 1942 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1943 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1944 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1945 .emit_frame_size = 1946 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1947 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1948 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1949 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1950 1, /* vcn_v1_0_enc_ring_insert_end */ 1951 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1952 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1953 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1954 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1955 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1956 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1957 .insert_nop = amdgpu_ring_insert_nop, 1958 .insert_end = vcn_v1_0_enc_ring_insert_end, 1959 .pad_ib = amdgpu_ring_generic_pad_ib, 1960 .begin_use = vcn_v1_0_ring_begin_use, 1961 .end_use = vcn_v1_0_ring_end_use, 1962 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1963 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1964 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1965 }; 1966 1967 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1968 { 1969 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1970 DRM_INFO("VCN decode is enabled in VM mode\n"); 1971 } 1972 1973 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1974 { 1975 int i; 1976 1977 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1978 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1979 1980 DRM_INFO("VCN encode is enabled in VM mode\n"); 1981 } 1982 1983 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1984 .set = vcn_v1_0_set_interrupt_state, 1985 .process = vcn_v1_0_process_interrupt, 1986 }; 1987 1988 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1989 { 1990 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 1991 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 1992 } 1993 1994 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1995 { 1996 .type = AMD_IP_BLOCK_TYPE_VCN, 1997 .major = 1, 1998 .minor = 0, 1999 .rev = 0, 2000 .funcs = &vcn_v1_0_ip_funcs, 2001 }; 2002