1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 32 #include "vcn/vcn_1_0_offset.h" 33 #include "vcn/vcn_1_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 40 #define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab 41 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 42 #define mmUVD_REG_XX_MASK 0x05ac 43 #define mmUVD_REG_XX_MASK_BASE_IDX 1 44 45 static int vcn_v1_0_stop(struct amdgpu_device *adev); 46 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 47 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 53 struct dpg_pause_state *new_state); 54 55 /** 56 * vcn_v1_0_early_init - set function pointers 57 * 58 * @handle: amdgpu_device pointer 59 * 60 * Set ring and irq function pointers 61 */ 62 static int vcn_v1_0_early_init(void *handle) 63 { 64 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 65 66 adev->vcn.num_enc_rings = 2; 67 68 vcn_v1_0_set_dec_ring_funcs(adev); 69 vcn_v1_0_set_enc_ring_funcs(adev); 70 vcn_v1_0_set_jpeg_ring_funcs(adev); 71 vcn_v1_0_set_irq_funcs(adev); 72 73 return 0; 74 } 75 76 /** 77 * vcn_v1_0_sw_init - sw init for VCN block 78 * 79 * @handle: amdgpu_device pointer 80 * 81 * Load firmware and sw initialization 82 */ 83 static int vcn_v1_0_sw_init(void *handle) 84 { 85 struct amdgpu_ring *ring; 86 int i, r; 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 89 /* VCN DEC TRAP */ 90 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq); 91 if (r) 92 return r; 93 94 /* VCN ENC TRAP */ 95 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 97 &adev->vcn.irq); 98 if (r) 99 return r; 100 } 101 102 /* VCN JPEG TRAP */ 103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq); 104 if (r) 105 return r; 106 107 r = amdgpu_vcn_sw_init(adev); 108 if (r) 109 return r; 110 111 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 112 const struct common_firmware_header *hdr; 113 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 114 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 115 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 116 adev->firmware.fw_size += 117 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 118 DRM_INFO("PSP loading VCN firmware\n"); 119 } 120 121 r = amdgpu_vcn_resume(adev); 122 if (r) 123 return r; 124 125 ring = &adev->vcn.ring_dec; 126 sprintf(ring->name, "vcn_dec"); 127 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 128 if (r) 129 return r; 130 131 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 132 ring = &adev->vcn.ring_enc[i]; 133 sprintf(ring->name, "vcn_enc%d", i); 134 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 135 if (r) 136 return r; 137 } 138 139 ring = &adev->vcn.ring_jpeg; 140 sprintf(ring->name, "vcn_jpeg"); 141 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 142 if (r) 143 return r; 144 145 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 146 147 return 0; 148 } 149 150 /** 151 * vcn_v1_0_sw_fini - sw fini for VCN block 152 * 153 * @handle: amdgpu_device pointer 154 * 155 * VCN suspend and free up sw allocation 156 */ 157 static int vcn_v1_0_sw_fini(void *handle) 158 { 159 int r; 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 162 r = amdgpu_vcn_suspend(adev); 163 if (r) 164 return r; 165 166 r = amdgpu_vcn_sw_fini(adev); 167 168 return r; 169 } 170 171 /** 172 * vcn_v1_0_hw_init - start and test VCN block 173 * 174 * @handle: amdgpu_device pointer 175 * 176 * Initialize the hardware, boot up the VCPU and do some testing 177 */ 178 static int vcn_v1_0_hw_init(void *handle) 179 { 180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 181 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 182 int i, r; 183 184 r = amdgpu_ring_test_helper(ring); 185 if (r) 186 goto done; 187 188 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 189 ring = &adev->vcn.ring_enc[i]; 190 ring->sched.ready = true; 191 r = amdgpu_ring_test_helper(ring); 192 if (r) 193 goto done; 194 } 195 196 ring = &adev->vcn.ring_jpeg; 197 r = amdgpu_ring_test_helper(ring); 198 if (r) 199 goto done; 200 201 done: 202 if (!r) 203 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 204 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 205 206 return r; 207 } 208 209 /** 210 * vcn_v1_0_hw_fini - stop the hardware block 211 * 212 * @handle: amdgpu_device pointer 213 * 214 * Stop the VCN block, mark ring as not ready any more 215 */ 216 static int vcn_v1_0_hw_fini(void *handle) 217 { 218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 219 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 220 221 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 222 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 223 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 224 225 ring->sched.ready = false; 226 227 return 0; 228 } 229 230 /** 231 * vcn_v1_0_suspend - suspend VCN block 232 * 233 * @handle: amdgpu_device pointer 234 * 235 * HW fini and suspend VCN block 236 */ 237 static int vcn_v1_0_suspend(void *handle) 238 { 239 int r; 240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 241 242 r = vcn_v1_0_hw_fini(adev); 243 if (r) 244 return r; 245 246 r = amdgpu_vcn_suspend(adev); 247 248 return r; 249 } 250 251 /** 252 * vcn_v1_0_resume - resume VCN block 253 * 254 * @handle: amdgpu_device pointer 255 * 256 * Resume firmware and hw init VCN block 257 */ 258 static int vcn_v1_0_resume(void *handle) 259 { 260 int r; 261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 262 263 r = amdgpu_vcn_resume(adev); 264 if (r) 265 return r; 266 267 r = vcn_v1_0_hw_init(adev); 268 269 return r; 270 } 271 272 /** 273 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 274 * 275 * @adev: amdgpu_device pointer 276 * 277 * Let the VCN memory controller know it's offsets 278 */ 279 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 280 { 281 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 282 uint32_t offset; 283 284 /* cache window 0: fw */ 285 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 286 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 287 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 288 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 289 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 290 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 291 offset = 0; 292 } else { 293 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 294 lower_32_bits(adev->vcn.gpu_addr)); 295 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 296 upper_32_bits(adev->vcn.gpu_addr)); 297 offset = size; 298 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 299 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 300 } 301 302 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 303 304 /* cache window 1: stack */ 305 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 306 lower_32_bits(adev->vcn.gpu_addr + offset)); 307 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 308 upper_32_bits(adev->vcn.gpu_addr + offset)); 309 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 310 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 311 312 /* cache window 2: context */ 313 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 314 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 315 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 316 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 317 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 318 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 319 320 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 321 adev->gfx.config.gb_addr_config); 322 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 323 adev->gfx.config.gb_addr_config); 324 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 325 adev->gfx.config.gb_addr_config); 326 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 327 adev->gfx.config.gb_addr_config); 328 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 329 adev->gfx.config.gb_addr_config); 330 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 331 adev->gfx.config.gb_addr_config); 332 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 333 adev->gfx.config.gb_addr_config); 334 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 335 adev->gfx.config.gb_addr_config); 336 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 337 adev->gfx.config.gb_addr_config); 338 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 343 adev->gfx.config.gb_addr_config); 344 } 345 346 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 347 { 348 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 349 uint32_t offset; 350 351 /* cache window 0: fw */ 352 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 353 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 354 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 355 0xFFFFFFFF, 0); 356 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 357 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 358 0xFFFFFFFF, 0); 359 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 360 0xFFFFFFFF, 0); 361 offset = 0; 362 } else { 363 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 364 lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); 365 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 366 upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); 367 offset = size; 368 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 369 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 370 } 371 372 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 373 374 /* cache window 1: stack */ 375 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 376 lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); 377 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 378 upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); 379 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 380 0xFFFFFFFF, 0); 381 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 382 0xFFFFFFFF, 0); 383 384 /* cache window 2: context */ 385 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 386 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 387 0xFFFFFFFF, 0); 388 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 389 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 390 0xFFFFFFFF, 0); 391 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 392 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 393 0xFFFFFFFF, 0); 394 395 /* VCN global tiling registers */ 396 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 397 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 398 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 399 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 400 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 401 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 402 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 403 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 404 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 405 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 406 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 407 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 408 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 409 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 410 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 411 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 412 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 413 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 414 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 416 } 417 418 /** 419 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 420 * 421 * @adev: amdgpu_device pointer 422 * @sw: enable SW clock gating 423 * 424 * Disable clock gating for VCN block 425 */ 426 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 427 { 428 uint32_t data; 429 430 /* JPEG disable CGC */ 431 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 432 433 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 434 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 435 else 436 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 437 438 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 439 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 440 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 441 442 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 443 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 444 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 445 446 /* UVD disable CGC */ 447 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 448 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 449 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 450 else 451 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 452 453 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 454 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 455 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 456 457 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 458 data &= ~(UVD_CGC_GATE__SYS_MASK 459 | UVD_CGC_GATE__UDEC_MASK 460 | UVD_CGC_GATE__MPEG2_MASK 461 | UVD_CGC_GATE__REGS_MASK 462 | UVD_CGC_GATE__RBC_MASK 463 | UVD_CGC_GATE__LMI_MC_MASK 464 | UVD_CGC_GATE__LMI_UMC_MASK 465 | UVD_CGC_GATE__IDCT_MASK 466 | UVD_CGC_GATE__MPRD_MASK 467 | UVD_CGC_GATE__MPC_MASK 468 | UVD_CGC_GATE__LBSI_MASK 469 | UVD_CGC_GATE__LRBBM_MASK 470 | UVD_CGC_GATE__UDEC_RE_MASK 471 | UVD_CGC_GATE__UDEC_CM_MASK 472 | UVD_CGC_GATE__UDEC_IT_MASK 473 | UVD_CGC_GATE__UDEC_DB_MASK 474 | UVD_CGC_GATE__UDEC_MP_MASK 475 | UVD_CGC_GATE__WCB_MASK 476 | UVD_CGC_GATE__VCPU_MASK 477 | UVD_CGC_GATE__SCPU_MASK); 478 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 479 480 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 481 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 482 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 483 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 484 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 485 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 486 | UVD_CGC_CTRL__SYS_MODE_MASK 487 | UVD_CGC_CTRL__UDEC_MODE_MASK 488 | UVD_CGC_CTRL__MPEG2_MODE_MASK 489 | UVD_CGC_CTRL__REGS_MODE_MASK 490 | UVD_CGC_CTRL__RBC_MODE_MASK 491 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 492 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 493 | UVD_CGC_CTRL__IDCT_MODE_MASK 494 | UVD_CGC_CTRL__MPRD_MODE_MASK 495 | UVD_CGC_CTRL__MPC_MODE_MASK 496 | UVD_CGC_CTRL__LBSI_MODE_MASK 497 | UVD_CGC_CTRL__LRBBM_MODE_MASK 498 | UVD_CGC_CTRL__WCB_MODE_MASK 499 | UVD_CGC_CTRL__VCPU_MODE_MASK 500 | UVD_CGC_CTRL__SCPU_MODE_MASK); 501 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 502 503 /* turn on */ 504 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 505 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 506 | UVD_SUVD_CGC_GATE__SIT_MASK 507 | UVD_SUVD_CGC_GATE__SMP_MASK 508 | UVD_SUVD_CGC_GATE__SCM_MASK 509 | UVD_SUVD_CGC_GATE__SDB_MASK 510 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 511 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 512 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 513 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 514 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 515 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 516 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 517 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 518 | UVD_SUVD_CGC_GATE__SCLR_MASK 519 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 520 | UVD_SUVD_CGC_GATE__ENT_MASK 521 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 522 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 523 | UVD_SUVD_CGC_GATE__SITE_MASK 524 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 525 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 526 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 527 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 528 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 529 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 530 531 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 532 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 533 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 534 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 535 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 536 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 537 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 538 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 539 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 540 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 541 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 542 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 543 } 544 545 /** 546 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 547 * 548 * @adev: amdgpu_device pointer 549 * @sw: enable SW clock gating 550 * 551 * Enable clock gating for VCN block 552 */ 553 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 554 { 555 uint32_t data = 0; 556 557 /* enable JPEG CGC */ 558 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 559 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 560 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 561 else 562 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 563 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 564 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 565 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 566 567 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 568 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 569 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 570 571 /* enable UVD CGC */ 572 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 573 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 574 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 575 else 576 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 577 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 578 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 579 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 580 581 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 582 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 583 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 584 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 585 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 586 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 587 | UVD_CGC_CTRL__SYS_MODE_MASK 588 | UVD_CGC_CTRL__UDEC_MODE_MASK 589 | UVD_CGC_CTRL__MPEG2_MODE_MASK 590 | UVD_CGC_CTRL__REGS_MODE_MASK 591 | UVD_CGC_CTRL__RBC_MODE_MASK 592 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 593 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 594 | UVD_CGC_CTRL__IDCT_MODE_MASK 595 | UVD_CGC_CTRL__MPRD_MODE_MASK 596 | UVD_CGC_CTRL__MPC_MODE_MASK 597 | UVD_CGC_CTRL__LBSI_MODE_MASK 598 | UVD_CGC_CTRL__LRBBM_MODE_MASK 599 | UVD_CGC_CTRL__WCB_MODE_MASK 600 | UVD_CGC_CTRL__VCPU_MODE_MASK 601 | UVD_CGC_CTRL__SCPU_MODE_MASK); 602 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 603 604 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 605 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 606 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 607 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 608 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 609 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 610 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 611 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 612 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 613 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 614 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 615 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 616 } 617 618 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 619 { 620 uint32_t reg_data = 0; 621 622 /* disable JPEG CGC */ 623 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 624 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 625 else 626 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 627 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 628 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 629 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 630 631 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 632 633 /* enable sw clock gating control */ 634 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 635 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 636 else 637 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 638 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 639 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 640 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 641 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 642 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 643 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 644 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 645 UVD_CGC_CTRL__SYS_MODE_MASK | 646 UVD_CGC_CTRL__UDEC_MODE_MASK | 647 UVD_CGC_CTRL__MPEG2_MODE_MASK | 648 UVD_CGC_CTRL__REGS_MODE_MASK | 649 UVD_CGC_CTRL__RBC_MODE_MASK | 650 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 651 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 652 UVD_CGC_CTRL__IDCT_MODE_MASK | 653 UVD_CGC_CTRL__MPRD_MODE_MASK | 654 UVD_CGC_CTRL__MPC_MODE_MASK | 655 UVD_CGC_CTRL__LBSI_MODE_MASK | 656 UVD_CGC_CTRL__LRBBM_MODE_MASK | 657 UVD_CGC_CTRL__WCB_MODE_MASK | 658 UVD_CGC_CTRL__VCPU_MODE_MASK | 659 UVD_CGC_CTRL__SCPU_MODE_MASK); 660 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 661 662 /* turn off clock gating */ 663 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 664 665 /* turn on SUVD clock gating */ 666 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 667 668 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 669 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 670 } 671 672 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 673 { 674 uint32_t data = 0; 675 int ret; 676 677 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 678 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 679 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 680 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 681 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 682 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 686 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 687 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 688 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 689 690 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 691 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 692 } else { 693 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 694 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 695 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 696 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 697 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 698 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 699 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 700 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 704 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 705 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 706 } 707 708 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 709 710 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 711 data &= ~0x103; 712 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 713 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 714 715 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 716 } 717 718 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 719 { 720 uint32_t data = 0; 721 int ret; 722 723 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 724 /* Before power off, this indicator has to be turned on */ 725 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 726 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 727 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 728 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 729 730 731 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 732 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 733 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 734 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 735 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 736 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 737 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 738 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 739 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 740 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 742 743 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 744 745 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 746 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 747 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 748 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 749 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 750 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 751 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 752 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 753 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 754 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 755 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 756 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 757 } 758 } 759 760 /** 761 * vcn_v1_0_start - start VCN block 762 * 763 * @adev: amdgpu_device pointer 764 * 765 * Setup and start the VCN block 766 */ 767 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 768 { 769 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 770 uint32_t rb_bufsz, tmp; 771 uint32_t lmi_swap_cntl; 772 int i, j, r; 773 774 /* disable byte swapping */ 775 lmi_swap_cntl = 0; 776 777 vcn_1_0_disable_static_power_gating(adev); 778 779 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 780 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 781 782 /* disable clock gating */ 783 vcn_v1_0_disable_clock_gating(adev); 784 785 /* disable interupt */ 786 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 787 ~UVD_MASTINT_EN__VCPU_EN_MASK); 788 789 /* initialize VCN memory controller */ 790 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 791 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 792 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 793 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 794 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 795 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 796 797 #ifdef __BIG_ENDIAN 798 /* swap (8 in 32) RB and IB */ 799 lmi_swap_cntl = 0xa; 800 #endif 801 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 802 803 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 804 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 805 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 806 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 807 808 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 809 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 810 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 811 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 812 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 813 814 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 815 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 816 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 817 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 818 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 819 820 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 821 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 822 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 823 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 824 825 vcn_v1_0_mc_resume_spg_mode(adev); 826 827 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10); 828 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 829 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); 830 831 /* enable VCPU clock */ 832 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 833 834 /* boot up the VCPU */ 835 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 836 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 837 838 /* enable UMC */ 839 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 840 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 841 842 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 843 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 844 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 845 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 846 847 for (i = 0; i < 10; ++i) { 848 uint32_t status; 849 850 for (j = 0; j < 100; ++j) { 851 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 852 if (status & UVD_STATUS__IDLE) 853 break; 854 mdelay(10); 855 } 856 r = 0; 857 if (status & UVD_STATUS__IDLE) 858 break; 859 860 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 861 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 862 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 863 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 864 mdelay(10); 865 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 866 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 867 mdelay(10); 868 r = -1; 869 } 870 871 if (r) { 872 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 873 return r; 874 } 875 /* enable master interrupt */ 876 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 877 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 878 879 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 880 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 881 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 882 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 883 884 /* clear the busy bit of UVD_STATUS */ 885 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 886 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 887 888 /* force RBC into idle state */ 889 rb_bufsz = order_base_2(ring->ring_size); 890 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 891 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 892 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 893 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 894 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 895 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 896 897 /* set the write pointer delay */ 898 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 899 900 /* set the wb address */ 901 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 902 (upper_32_bits(ring->gpu_addr) >> 2)); 903 904 /* programm the RB_BASE for ring buffer */ 905 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 906 lower_32_bits(ring->gpu_addr)); 907 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 908 upper_32_bits(ring->gpu_addr)); 909 910 /* Initialize the ring buffer's read and write pointers */ 911 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 912 913 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 914 915 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 917 lower_32_bits(ring->wptr)); 918 919 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 920 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 921 922 ring = &adev->vcn.ring_enc[0]; 923 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 924 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 925 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 926 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 927 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 928 929 ring = &adev->vcn.ring_enc[1]; 930 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 931 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 932 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 933 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 934 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 935 936 ring = &adev->vcn.ring_jpeg; 937 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 938 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 939 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 940 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); 941 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); 942 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); 943 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); 944 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 945 946 /* initialize wptr */ 947 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 948 949 /* copy patch commands to the jpeg ring */ 950 vcn_v1_0_jpeg_ring_set_patch_ring(ring, 951 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); 952 953 return 0; 954 } 955 956 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 957 { 958 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 959 uint32_t rb_bufsz, tmp; 960 uint32_t lmi_swap_cntl; 961 962 /* disable byte swapping */ 963 lmi_swap_cntl = 0; 964 965 vcn_1_0_enable_static_power_gating(adev); 966 967 /* enable dynamic power gating mode */ 968 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 969 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 970 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 971 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 972 973 /* enable clock gating */ 974 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 975 976 /* enable VCPU clock */ 977 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 978 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 979 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 980 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 981 982 /* disable interupt */ 983 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 984 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 985 986 /* initialize VCN memory controller */ 987 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 988 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 989 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 990 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 991 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 992 UVD_LMI_CTRL__REQ_MODE_MASK | 993 UVD_LMI_CTRL__CRC_RESET_MASK | 994 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 995 0x00100000L, 0xFFFFFFFF, 0); 996 997 #ifdef __BIG_ENDIAN 998 /* swap (8 in 32) RB and IB */ 999 lmi_swap_cntl = 0xa; 1000 #endif 1001 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1002 1003 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, 1004 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1005 1006 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 1007 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1008 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1009 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1010 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1011 1012 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 1013 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1014 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1015 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1016 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1017 1018 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 1019 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1020 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1021 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1022 1023 vcn_v1_0_mc_resume_dpg_mode(adev); 1024 1025 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1026 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1027 1028 /* boot up the VCPU */ 1029 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1030 1031 /* enable UMC */ 1032 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1033 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1034 0xFFFFFFFF, 0); 1035 1036 /* enable master interrupt */ 1037 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1038 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1039 1040 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1041 /* setup mmUVD_LMI_CTRL */ 1042 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1043 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1044 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1045 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1046 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1047 UVD_LMI_CTRL__REQ_MODE_MASK | 1048 UVD_LMI_CTRL__CRC_RESET_MASK | 1049 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1050 0x00100000L, 0xFFFFFFFF, 1); 1051 1052 tmp = adev->gfx.config.gb_addr_config; 1053 /* setup VCN global tiling registers */ 1054 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1055 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1056 1057 /* enable System Interrupt for JRBC */ 1058 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, 1059 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1060 1061 /* force RBC into idle state */ 1062 rb_bufsz = order_base_2(ring->ring_size); 1063 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1065 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1066 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1068 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1069 1070 /* set the write pointer delay */ 1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1072 1073 /* set the wb address */ 1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1075 (upper_32_bits(ring->gpu_addr) >> 2)); 1076 1077 /* programm the RB_BASE for ring buffer */ 1078 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1079 lower_32_bits(ring->gpu_addr)); 1080 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1081 upper_32_bits(ring->gpu_addr)); 1082 1083 /* Initialize the ring buffer's read and write pointers */ 1084 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1085 1086 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1087 1088 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1089 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1090 lower_32_bits(ring->wptr)); 1091 1092 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1093 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1094 1095 /* initialize JPEG wptr */ 1096 ring = &adev->vcn.ring_jpeg; 1097 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1098 1099 /* copy patch commands to the jpeg ring */ 1100 vcn_v1_0_jpeg_ring_set_patch_ring(ring, 1101 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); 1102 1103 return 0; 1104 } 1105 1106 static int vcn_v1_0_start(struct amdgpu_device *adev) 1107 { 1108 int r; 1109 1110 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1111 r = vcn_v1_0_start_dpg_mode(adev); 1112 else 1113 r = vcn_v1_0_start_spg_mode(adev); 1114 return r; 1115 } 1116 1117 /** 1118 * vcn_v1_0_stop - stop VCN block 1119 * 1120 * @adev: amdgpu_device pointer 1121 * 1122 * stop the VCN block 1123 */ 1124 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1125 { 1126 int ret_code, tmp; 1127 1128 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1129 1130 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1131 UVD_LMI_STATUS__READ_CLEAN_MASK | 1132 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1133 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1134 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1135 1136 /* put VCPU into reset */ 1137 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1138 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1139 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1140 1141 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1142 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1143 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1144 1145 /* disable VCPU clock */ 1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1147 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1148 1149 /* reset LMI UMC/LMI */ 1150 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1151 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1152 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1153 1154 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1155 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1156 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1157 1158 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1159 1160 vcn_v1_0_enable_clock_gating(adev); 1161 vcn_1_0_enable_static_power_gating(adev); 1162 return 0; 1163 } 1164 1165 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1166 { 1167 int ret_code = 0; 1168 uint32_t tmp; 1169 1170 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1172 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1173 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1174 1175 /* wait for read ptr to be equal to write ptr */ 1176 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1178 1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1181 1182 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1184 1185 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1187 1188 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1189 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1190 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1191 1192 /* disable dynamic power gating mode */ 1193 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1194 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1195 1196 return 0; 1197 } 1198 1199 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1200 { 1201 int r; 1202 1203 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1204 r = vcn_v1_0_stop_dpg_mode(adev); 1205 else 1206 r = vcn_v1_0_stop_spg_mode(adev); 1207 1208 return r; 1209 } 1210 1211 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1212 struct dpg_pause_state *new_state) 1213 { 1214 int ret_code; 1215 uint32_t reg_data = 0; 1216 uint32_t reg_data2 = 0; 1217 struct amdgpu_ring *ring; 1218 1219 /* pause/unpause if state is changed */ 1220 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { 1221 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1222 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, 1223 new_state->fw_based, new_state->jpeg); 1224 1225 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1226 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1227 1228 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1229 ret_code = 0; 1230 1231 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1232 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1233 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1234 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1235 1236 if (!ret_code) { 1237 /* pause DPG non-jpeg */ 1238 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1239 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1240 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1241 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1242 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1243 1244 /* Restore */ 1245 ring = &adev->vcn.ring_enc[0]; 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1248 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1249 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1250 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1251 1252 ring = &adev->vcn.ring_enc[1]; 1253 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1254 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1255 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1256 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1257 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1258 1259 ring = &adev->vcn.ring_dec; 1260 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1261 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1262 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1263 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1264 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1265 } 1266 } else { 1267 /* unpause dpg non-jpeg, no need to wait */ 1268 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1270 } 1271 adev->vcn.pause_state.fw_based = new_state->fw_based; 1272 } 1273 1274 /* pause/unpause if state is changed */ 1275 if (adev->vcn.pause_state.jpeg != new_state->jpeg) { 1276 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1277 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, 1278 new_state->fw_based, new_state->jpeg); 1279 1280 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1281 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1282 1283 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1284 ret_code = 0; 1285 1286 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1287 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1288 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1289 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1290 1291 if (!ret_code) { 1292 /* Make sure JPRG Snoop is disabled before sending the pause */ 1293 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1294 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1295 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1296 1297 /* pause DPG jpeg */ 1298 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1299 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1300 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1301 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1302 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); 1303 1304 /* Restore */ 1305 ring = &adev->vcn.ring_jpeg; 1306 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1307 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1308 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1309 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1310 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1311 lower_32_bits(ring->gpu_addr)); 1312 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1313 upper_32_bits(ring->gpu_addr)); 1314 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1315 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1316 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1317 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1318 1319 ring = &adev->vcn.ring_dec; 1320 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1321 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1322 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1323 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1324 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1325 } 1326 } else { 1327 /* unpause dpg jpeg, no need to wait */ 1328 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1329 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1330 } 1331 adev->vcn.pause_state.jpeg = new_state->jpeg; 1332 } 1333 1334 return 0; 1335 } 1336 1337 static bool vcn_v1_0_is_idle(void *handle) 1338 { 1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1340 1341 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1342 } 1343 1344 static int vcn_v1_0_wait_for_idle(void *handle) 1345 { 1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347 int ret = 0; 1348 1349 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1350 UVD_STATUS__IDLE, ret); 1351 1352 return ret; 1353 } 1354 1355 static int vcn_v1_0_set_clockgating_state(void *handle, 1356 enum amd_clockgating_state state) 1357 { 1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1359 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1360 1361 if (enable) { 1362 /* wait for STATUS to clear */ 1363 if (vcn_v1_0_is_idle(handle)) 1364 return -EBUSY; 1365 vcn_v1_0_enable_clock_gating(adev); 1366 } else { 1367 /* disable HW gating and enable Sw gating */ 1368 vcn_v1_0_disable_clock_gating(adev); 1369 } 1370 return 0; 1371 } 1372 1373 /** 1374 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1375 * 1376 * @ring: amdgpu_ring pointer 1377 * 1378 * Returns the current hardware read pointer 1379 */ 1380 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1381 { 1382 struct amdgpu_device *adev = ring->adev; 1383 1384 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1385 } 1386 1387 /** 1388 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1389 * 1390 * @ring: amdgpu_ring pointer 1391 * 1392 * Returns the current hardware write pointer 1393 */ 1394 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1395 { 1396 struct amdgpu_device *adev = ring->adev; 1397 1398 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1399 } 1400 1401 /** 1402 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1403 * 1404 * @ring: amdgpu_ring pointer 1405 * 1406 * Commits the write pointer to the hardware 1407 */ 1408 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1409 { 1410 struct amdgpu_device *adev = ring->adev; 1411 1412 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1413 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1414 lower_32_bits(ring->wptr) | 0x80000000); 1415 1416 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1417 } 1418 1419 /** 1420 * vcn_v1_0_dec_ring_insert_start - insert a start command 1421 * 1422 * @ring: amdgpu_ring pointer 1423 * 1424 * Write a start command to the ring. 1425 */ 1426 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1427 { 1428 struct amdgpu_device *adev = ring->adev; 1429 1430 amdgpu_ring_write(ring, 1431 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1432 amdgpu_ring_write(ring, 0); 1433 amdgpu_ring_write(ring, 1434 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1435 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1436 } 1437 1438 /** 1439 * vcn_v1_0_dec_ring_insert_end - insert a end command 1440 * 1441 * @ring: amdgpu_ring pointer 1442 * 1443 * Write a end command to the ring. 1444 */ 1445 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1446 { 1447 struct amdgpu_device *adev = ring->adev; 1448 1449 amdgpu_ring_write(ring, 1450 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1451 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1452 } 1453 1454 /** 1455 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1456 * 1457 * @ring: amdgpu_ring pointer 1458 * @fence: fence to emit 1459 * 1460 * Write a fence and a trap command to the ring. 1461 */ 1462 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1463 unsigned flags) 1464 { 1465 struct amdgpu_device *adev = ring->adev; 1466 1467 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1468 1469 amdgpu_ring_write(ring, 1470 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1471 amdgpu_ring_write(ring, seq); 1472 amdgpu_ring_write(ring, 1473 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1474 amdgpu_ring_write(ring, addr & 0xffffffff); 1475 amdgpu_ring_write(ring, 1476 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1477 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1478 amdgpu_ring_write(ring, 1479 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1480 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1481 1482 amdgpu_ring_write(ring, 1483 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1484 amdgpu_ring_write(ring, 0); 1485 amdgpu_ring_write(ring, 1486 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1487 amdgpu_ring_write(ring, 0); 1488 amdgpu_ring_write(ring, 1489 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1490 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1491 } 1492 1493 /** 1494 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1495 * 1496 * @ring: amdgpu_ring pointer 1497 * @ib: indirect buffer to execute 1498 * 1499 * Write ring commands to execute the indirect buffer 1500 */ 1501 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1502 struct amdgpu_job *job, 1503 struct amdgpu_ib *ib, 1504 uint32_t flags) 1505 { 1506 struct amdgpu_device *adev = ring->adev; 1507 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1508 1509 amdgpu_ring_write(ring, 1510 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1511 amdgpu_ring_write(ring, vmid); 1512 1513 amdgpu_ring_write(ring, 1514 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1515 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1516 amdgpu_ring_write(ring, 1517 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1518 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1519 amdgpu_ring_write(ring, 1520 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1521 amdgpu_ring_write(ring, ib->length_dw); 1522 } 1523 1524 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1525 uint32_t reg, uint32_t val, 1526 uint32_t mask) 1527 { 1528 struct amdgpu_device *adev = ring->adev; 1529 1530 amdgpu_ring_write(ring, 1531 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1532 amdgpu_ring_write(ring, reg << 2); 1533 amdgpu_ring_write(ring, 1534 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1535 amdgpu_ring_write(ring, val); 1536 amdgpu_ring_write(ring, 1537 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1538 amdgpu_ring_write(ring, mask); 1539 amdgpu_ring_write(ring, 1540 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1541 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1542 } 1543 1544 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1545 unsigned vmid, uint64_t pd_addr) 1546 { 1547 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1548 uint32_t data0, data1, mask; 1549 1550 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1551 1552 /* wait for register write */ 1553 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1554 data1 = lower_32_bits(pd_addr); 1555 mask = 0xffffffff; 1556 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1557 } 1558 1559 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1560 uint32_t reg, uint32_t val) 1561 { 1562 struct amdgpu_device *adev = ring->adev; 1563 1564 amdgpu_ring_write(ring, 1565 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1566 amdgpu_ring_write(ring, reg << 2); 1567 amdgpu_ring_write(ring, 1568 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1569 amdgpu_ring_write(ring, val); 1570 amdgpu_ring_write(ring, 1571 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1572 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1573 } 1574 1575 /** 1576 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1577 * 1578 * @ring: amdgpu_ring pointer 1579 * 1580 * Returns the current hardware enc read pointer 1581 */ 1582 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1583 { 1584 struct amdgpu_device *adev = ring->adev; 1585 1586 if (ring == &adev->vcn.ring_enc[0]) 1587 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1588 else 1589 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1590 } 1591 1592 /** 1593 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1594 * 1595 * @ring: amdgpu_ring pointer 1596 * 1597 * Returns the current hardware enc write pointer 1598 */ 1599 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1600 { 1601 struct amdgpu_device *adev = ring->adev; 1602 1603 if (ring == &adev->vcn.ring_enc[0]) 1604 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1605 else 1606 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1607 } 1608 1609 /** 1610 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1611 * 1612 * @ring: amdgpu_ring pointer 1613 * 1614 * Commits the enc write pointer to the hardware 1615 */ 1616 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1617 { 1618 struct amdgpu_device *adev = ring->adev; 1619 1620 if (ring == &adev->vcn.ring_enc[0]) 1621 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1622 lower_32_bits(ring->wptr)); 1623 else 1624 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1625 lower_32_bits(ring->wptr)); 1626 } 1627 1628 /** 1629 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1630 * 1631 * @ring: amdgpu_ring pointer 1632 * @fence: fence to emit 1633 * 1634 * Write enc a fence and a trap command to the ring. 1635 */ 1636 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1637 u64 seq, unsigned flags) 1638 { 1639 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1640 1641 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1642 amdgpu_ring_write(ring, addr); 1643 amdgpu_ring_write(ring, upper_32_bits(addr)); 1644 amdgpu_ring_write(ring, seq); 1645 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1646 } 1647 1648 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1649 { 1650 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1651 } 1652 1653 /** 1654 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1655 * 1656 * @ring: amdgpu_ring pointer 1657 * @ib: indirect buffer to execute 1658 * 1659 * Write enc ring commands to execute the indirect buffer 1660 */ 1661 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1662 struct amdgpu_job *job, 1663 struct amdgpu_ib *ib, 1664 uint32_t flags) 1665 { 1666 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1667 1668 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1669 amdgpu_ring_write(ring, vmid); 1670 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1671 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1672 amdgpu_ring_write(ring, ib->length_dw); 1673 } 1674 1675 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1676 uint32_t reg, uint32_t val, 1677 uint32_t mask) 1678 { 1679 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1680 amdgpu_ring_write(ring, reg << 2); 1681 amdgpu_ring_write(ring, mask); 1682 amdgpu_ring_write(ring, val); 1683 } 1684 1685 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1686 unsigned int vmid, uint64_t pd_addr) 1687 { 1688 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1689 1690 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1691 1692 /* wait for reg writes */ 1693 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1694 lower_32_bits(pd_addr), 0xffffffff); 1695 } 1696 1697 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1698 uint32_t reg, uint32_t val) 1699 { 1700 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1701 amdgpu_ring_write(ring, reg << 2); 1702 amdgpu_ring_write(ring, val); 1703 } 1704 1705 1706 /** 1707 * vcn_v1_0_jpeg_ring_get_rptr - get read pointer 1708 * 1709 * @ring: amdgpu_ring pointer 1710 * 1711 * Returns the current hardware read pointer 1712 */ 1713 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) 1714 { 1715 struct amdgpu_device *adev = ring->adev; 1716 1717 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); 1718 } 1719 1720 /** 1721 * vcn_v1_0_jpeg_ring_get_wptr - get write pointer 1722 * 1723 * @ring: amdgpu_ring pointer 1724 * 1725 * Returns the current hardware write pointer 1726 */ 1727 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) 1728 { 1729 struct amdgpu_device *adev = ring->adev; 1730 1731 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1732 } 1733 1734 /** 1735 * vcn_v1_0_jpeg_ring_set_wptr - set write pointer 1736 * 1737 * @ring: amdgpu_ring pointer 1738 * 1739 * Commits the write pointer to the hardware 1740 */ 1741 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) 1742 { 1743 struct amdgpu_device *adev = ring->adev; 1744 1745 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 1746 } 1747 1748 /** 1749 * vcn_v1_0_jpeg_ring_insert_start - insert a start command 1750 * 1751 * @ring: amdgpu_ring pointer 1752 * 1753 * Write a start command to the ring. 1754 */ 1755 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) 1756 { 1757 struct amdgpu_device *adev = ring->adev; 1758 1759 amdgpu_ring_write(ring, 1760 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1761 amdgpu_ring_write(ring, 0x68e04); 1762 1763 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1764 amdgpu_ring_write(ring, 0x80010000); 1765 } 1766 1767 /** 1768 * vcn_v1_0_jpeg_ring_insert_end - insert a end command 1769 * 1770 * @ring: amdgpu_ring pointer 1771 * 1772 * Write a end command to the ring. 1773 */ 1774 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) 1775 { 1776 struct amdgpu_device *adev = ring->adev; 1777 1778 amdgpu_ring_write(ring, 1779 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1780 amdgpu_ring_write(ring, 0x68e04); 1781 1782 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1783 amdgpu_ring_write(ring, 0x00010000); 1784 } 1785 1786 /** 1787 * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command 1788 * 1789 * @ring: amdgpu_ring pointer 1790 * @fence: fence to emit 1791 * 1792 * Write a fence and a trap command to the ring. 1793 */ 1794 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1795 unsigned flags) 1796 { 1797 struct amdgpu_device *adev = ring->adev; 1798 1799 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1800 1801 amdgpu_ring_write(ring, 1802 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0)); 1803 amdgpu_ring_write(ring, seq); 1804 1805 amdgpu_ring_write(ring, 1806 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0)); 1807 amdgpu_ring_write(ring, seq); 1808 1809 amdgpu_ring_write(ring, 1810 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1811 amdgpu_ring_write(ring, lower_32_bits(addr)); 1812 1813 amdgpu_ring_write(ring, 1814 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1815 amdgpu_ring_write(ring, upper_32_bits(addr)); 1816 1817 amdgpu_ring_write(ring, 1818 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); 1819 amdgpu_ring_write(ring, 0x8); 1820 1821 amdgpu_ring_write(ring, 1822 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 1823 amdgpu_ring_write(ring, 0); 1824 1825 amdgpu_ring_write(ring, 1826 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1827 amdgpu_ring_write(ring, 0x01400200); 1828 1829 amdgpu_ring_write(ring, 1830 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1831 amdgpu_ring_write(ring, seq); 1832 1833 amdgpu_ring_write(ring, 1834 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1835 amdgpu_ring_write(ring, lower_32_bits(addr)); 1836 1837 amdgpu_ring_write(ring, 1838 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1839 amdgpu_ring_write(ring, upper_32_bits(addr)); 1840 1841 amdgpu_ring_write(ring, 1842 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2)); 1843 amdgpu_ring_write(ring, 0xffffffff); 1844 1845 amdgpu_ring_write(ring, 1846 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1847 amdgpu_ring_write(ring, 0x3fbc); 1848 1849 amdgpu_ring_write(ring, 1850 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1851 amdgpu_ring_write(ring, 0x1); 1852 1853 /* emit trap */ 1854 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 1855 amdgpu_ring_write(ring, 0); 1856 } 1857 1858 /** 1859 * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer 1860 * 1861 * @ring: amdgpu_ring pointer 1862 * @ib: indirect buffer to execute 1863 * 1864 * Write ring commands to execute the indirect buffer. 1865 */ 1866 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, 1867 struct amdgpu_job *job, 1868 struct amdgpu_ib *ib, 1869 uint32_t flags) 1870 { 1871 struct amdgpu_device *adev = ring->adev; 1872 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1873 1874 amdgpu_ring_write(ring, 1875 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); 1876 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1877 1878 amdgpu_ring_write(ring, 1879 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); 1880 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1881 1882 amdgpu_ring_write(ring, 1883 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1884 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1885 1886 amdgpu_ring_write(ring, 1887 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1888 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1889 1890 amdgpu_ring_write(ring, 1891 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); 1892 amdgpu_ring_write(ring, ib->length_dw); 1893 1894 amdgpu_ring_write(ring, 1895 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1896 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 1897 1898 amdgpu_ring_write(ring, 1899 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1900 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 1901 1902 amdgpu_ring_write(ring, 1903 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 1904 amdgpu_ring_write(ring, 0); 1905 1906 amdgpu_ring_write(ring, 1907 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1908 amdgpu_ring_write(ring, 0x01400200); 1909 1910 amdgpu_ring_write(ring, 1911 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1912 amdgpu_ring_write(ring, 0x2); 1913 1914 amdgpu_ring_write(ring, 1915 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 1916 amdgpu_ring_write(ring, 0x2); 1917 } 1918 1919 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, 1920 uint32_t reg, uint32_t val, 1921 uint32_t mask) 1922 { 1923 struct amdgpu_device *adev = ring->adev; 1924 uint32_t reg_offset = (reg << 2); 1925 1926 amdgpu_ring_write(ring, 1927 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1928 amdgpu_ring_write(ring, 0x01400200); 1929 1930 amdgpu_ring_write(ring, 1931 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1932 amdgpu_ring_write(ring, val); 1933 1934 amdgpu_ring_write(ring, 1935 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1936 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1937 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1938 amdgpu_ring_write(ring, 0); 1939 amdgpu_ring_write(ring, 1940 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 1941 } else { 1942 amdgpu_ring_write(ring, reg_offset); 1943 amdgpu_ring_write(ring, 1944 PACKETJ(0, 0, 0, PACKETJ_TYPE3)); 1945 } 1946 amdgpu_ring_write(ring, mask); 1947 } 1948 1949 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, 1950 unsigned vmid, uint64_t pd_addr) 1951 { 1952 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1953 uint32_t data0, data1, mask; 1954 1955 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1956 1957 /* wait for register write */ 1958 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1959 data1 = lower_32_bits(pd_addr); 1960 mask = 0xffffffff; 1961 vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); 1962 } 1963 1964 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, 1965 uint32_t reg, uint32_t val) 1966 { 1967 struct amdgpu_device *adev = ring->adev; 1968 uint32_t reg_offset = (reg << 2); 1969 1970 amdgpu_ring_write(ring, 1971 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1972 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1973 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1974 amdgpu_ring_write(ring, 0); 1975 amdgpu_ring_write(ring, 1976 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 1977 } else { 1978 amdgpu_ring_write(ring, reg_offset); 1979 amdgpu_ring_write(ring, 1980 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1981 } 1982 amdgpu_ring_write(ring, val); 1983 } 1984 1985 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) 1986 { 1987 int i; 1988 1989 WARN_ON(ring->wptr % 2 || count % 2); 1990 1991 for (i = 0; i < count / 2; i++) { 1992 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 1993 amdgpu_ring_write(ring, 0); 1994 } 1995 } 1996 1997 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) 1998 { 1999 struct amdgpu_device *adev = ring->adev; 2000 ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 2001 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 2002 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 2003 ring->ring[(*ptr)++] = 0; 2004 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); 2005 } else { 2006 ring->ring[(*ptr)++] = reg_offset; 2007 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); 2008 } 2009 ring->ring[(*ptr)++] = val; 2010 } 2011 2012 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) 2013 { 2014 struct amdgpu_device *adev = ring->adev; 2015 2016 uint32_t reg, reg_offset, val, mask, i; 2017 2018 // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 2019 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); 2020 reg_offset = (reg << 2); 2021 val = lower_32_bits(ring->gpu_addr); 2022 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 2023 2024 // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 2025 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); 2026 reg_offset = (reg << 2); 2027 val = upper_32_bits(ring->gpu_addr); 2028 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 2029 2030 // 3rd to 5th: issue MEM_READ commands 2031 for (i = 0; i <= 2; i++) { 2032 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); 2033 ring->ring[ptr++] = 0; 2034 } 2035 2036 // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability 2037 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 2038 reg_offset = (reg << 2); 2039 val = 0x13; 2040 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 2041 2042 // 7th: program mmUVD_JRBC_RB_REF_DATA 2043 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA); 2044 reg_offset = (reg << 2); 2045 val = 0x1; 2046 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 2047 2048 // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL 2049 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 2050 reg_offset = (reg << 2); 2051 val = 0x1; 2052 mask = 0x1; 2053 2054 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0); 2055 ring->ring[ptr++] = 0x01400200; 2056 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0); 2057 ring->ring[ptr++] = val; 2058 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 2059 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 2060 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 2061 ring->ring[ptr++] = 0; 2062 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); 2063 } else { 2064 ring->ring[ptr++] = reg_offset; 2065 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); 2066 } 2067 ring->ring[ptr++] = mask; 2068 2069 //9th to 21st: insert no-op 2070 for (i = 0; i <= 12; i++) { 2071 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 2072 ring->ring[ptr++] = 0; 2073 } 2074 2075 //22nd: reset mmUVD_JRBC_RB_RPTR 2076 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR); 2077 reg_offset = (reg << 2); 2078 val = 0; 2079 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 2080 2081 //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch 2082 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 2083 reg_offset = (reg << 2); 2084 val = 0x12; 2085 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 2086 } 2087 2088 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 2089 struct amdgpu_irq_src *source, 2090 unsigned type, 2091 enum amdgpu_interrupt_state state) 2092 { 2093 return 0; 2094 } 2095 2096 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 2097 struct amdgpu_irq_src *source, 2098 struct amdgpu_iv_entry *entry) 2099 { 2100 DRM_DEBUG("IH: VCN TRAP\n"); 2101 2102 switch (entry->src_id) { 2103 case 124: 2104 amdgpu_fence_process(&adev->vcn.ring_dec); 2105 break; 2106 case 119: 2107 amdgpu_fence_process(&adev->vcn.ring_enc[0]); 2108 break; 2109 case 120: 2110 amdgpu_fence_process(&adev->vcn.ring_enc[1]); 2111 break; 2112 case 126: 2113 amdgpu_fence_process(&adev->vcn.ring_jpeg); 2114 break; 2115 default: 2116 DRM_ERROR("Unhandled interrupt: %d %d\n", 2117 entry->src_id, entry->src_data[0]); 2118 break; 2119 } 2120 2121 return 0; 2122 } 2123 2124 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 2125 { 2126 struct amdgpu_device *adev = ring->adev; 2127 int i; 2128 2129 WARN_ON(ring->wptr % 2 || count % 2); 2130 2131 for (i = 0; i < count / 2; i++) { 2132 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 2133 amdgpu_ring_write(ring, 0); 2134 } 2135 } 2136 2137 static int vcn_v1_0_set_powergating_state(void *handle, 2138 enum amd_powergating_state state) 2139 { 2140 /* This doesn't actually powergate the VCN block. 2141 * That's done in the dpm code via the SMC. This 2142 * just re-inits the block as necessary. The actual 2143 * gating still happens in the dpm code. We should 2144 * revisit this when there is a cleaner line between 2145 * the smc and the hw blocks 2146 */ 2147 int ret; 2148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2149 2150 if(state == adev->vcn.cur_state) 2151 return 0; 2152 2153 if (state == AMD_PG_STATE_GATE) 2154 ret = vcn_v1_0_stop(adev); 2155 else 2156 ret = vcn_v1_0_start(adev); 2157 2158 if(!ret) 2159 adev->vcn.cur_state = state; 2160 return ret; 2161 } 2162 2163 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 2164 .name = "vcn_v1_0", 2165 .early_init = vcn_v1_0_early_init, 2166 .late_init = NULL, 2167 .sw_init = vcn_v1_0_sw_init, 2168 .sw_fini = vcn_v1_0_sw_fini, 2169 .hw_init = vcn_v1_0_hw_init, 2170 .hw_fini = vcn_v1_0_hw_fini, 2171 .suspend = vcn_v1_0_suspend, 2172 .resume = vcn_v1_0_resume, 2173 .is_idle = vcn_v1_0_is_idle, 2174 .wait_for_idle = vcn_v1_0_wait_for_idle, 2175 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 2176 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 2177 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 2178 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 2179 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 2180 .set_powergating_state = vcn_v1_0_set_powergating_state, 2181 }; 2182 2183 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 2184 .type = AMDGPU_RING_TYPE_VCN_DEC, 2185 .align_mask = 0xf, 2186 .support_64bit_ptrs = false, 2187 .no_user_fence = true, 2188 .vmhub = AMDGPU_MMHUB, 2189 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 2190 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 2191 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 2192 .emit_frame_size = 2193 6 + 6 + /* hdp invalidate / flush */ 2194 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2195 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2196 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 2197 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 2198 6, 2199 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 2200 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 2201 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 2202 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 2203 .test_ring = amdgpu_vcn_dec_ring_test_ring, 2204 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2205 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 2206 .insert_start = vcn_v1_0_dec_ring_insert_start, 2207 .insert_end = vcn_v1_0_dec_ring_insert_end, 2208 .pad_ib = amdgpu_ring_generic_pad_ib, 2209 .begin_use = amdgpu_vcn_ring_begin_use, 2210 .end_use = amdgpu_vcn_ring_end_use, 2211 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 2212 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 2213 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2214 }; 2215 2216 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 2217 .type = AMDGPU_RING_TYPE_VCN_ENC, 2218 .align_mask = 0x3f, 2219 .nop = VCN_ENC_CMD_NO_OP, 2220 .support_64bit_ptrs = false, 2221 .no_user_fence = true, 2222 .vmhub = AMDGPU_MMHUB, 2223 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 2224 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 2225 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 2226 .emit_frame_size = 2227 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2228 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2229 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 2230 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 2231 1, /* vcn_v1_0_enc_ring_insert_end */ 2232 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 2233 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 2234 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 2235 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 2236 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2237 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2238 .insert_nop = amdgpu_ring_insert_nop, 2239 .insert_end = vcn_v1_0_enc_ring_insert_end, 2240 .pad_ib = amdgpu_ring_generic_pad_ib, 2241 .begin_use = amdgpu_vcn_ring_begin_use, 2242 .end_use = amdgpu_vcn_ring_end_use, 2243 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 2244 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 2245 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2246 }; 2247 2248 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = { 2249 .type = AMDGPU_RING_TYPE_VCN_JPEG, 2250 .align_mask = 0xf, 2251 .nop = PACKET0(0x81ff, 0), 2252 .support_64bit_ptrs = false, 2253 .no_user_fence = true, 2254 .vmhub = AMDGPU_MMHUB, 2255 .extra_dw = 64, 2256 .get_rptr = vcn_v1_0_jpeg_ring_get_rptr, 2257 .get_wptr = vcn_v1_0_jpeg_ring_get_wptr, 2258 .set_wptr = vcn_v1_0_jpeg_ring_set_wptr, 2259 .emit_frame_size = 2260 6 + 6 + /* hdp invalidate / flush */ 2261 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2262 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2263 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */ 2264 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */ 2265 6, 2266 .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */ 2267 .emit_ib = vcn_v1_0_jpeg_ring_emit_ib, 2268 .emit_fence = vcn_v1_0_jpeg_ring_emit_fence, 2269 .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush, 2270 .test_ring = amdgpu_vcn_jpeg_ring_test_ring, 2271 .test_ib = amdgpu_vcn_jpeg_ring_test_ib, 2272 .insert_nop = vcn_v1_0_jpeg_ring_nop, 2273 .insert_start = vcn_v1_0_jpeg_ring_insert_start, 2274 .insert_end = vcn_v1_0_jpeg_ring_insert_end, 2275 .pad_ib = amdgpu_ring_generic_pad_ib, 2276 .begin_use = amdgpu_vcn_ring_begin_use, 2277 .end_use = amdgpu_vcn_ring_end_use, 2278 .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg, 2279 .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait, 2280 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2281 }; 2282 2283 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2284 { 2285 adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 2286 DRM_INFO("VCN decode is enabled in VM mode\n"); 2287 } 2288 2289 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2290 { 2291 int i; 2292 2293 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2294 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 2295 2296 DRM_INFO("VCN encode is enabled in VM mode\n"); 2297 } 2298 2299 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) 2300 { 2301 adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs; 2302 DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); 2303 } 2304 2305 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 2306 .set = vcn_v1_0_set_interrupt_state, 2307 .process = vcn_v1_0_process_interrupt, 2308 }; 2309 2310 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 2311 { 2312 adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2; 2313 adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; 2314 } 2315 2316 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 2317 { 2318 .type = AMD_IP_BLOCK_TYPE_VCN, 2319 .major = 1, 2320 .minor = 0, 2321 .rev = 0, 2322 .funcs = &vcn_v1_0_ip_funcs, 2323 }; 2324