1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 32 #include "vcn/vcn_1_0_offset.h" 33 #include "vcn/vcn_1_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 #include "jpeg_v1_0.h" 40 41 #define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab 42 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 43 #define mmUVD_REG_XX_MASK 0x05ac 44 #define mmUVD_REG_XX_MASK_BASE_IDX 1 45 46 static int vcn_v1_0_stop(struct amdgpu_device *adev); 47 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 50 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 51 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 52 struct dpg_pause_state *new_state); 53 54 /** 55 * vcn_v1_0_early_init - set function pointers 56 * 57 * @handle: amdgpu_device pointer 58 * 59 * Set ring and irq function pointers 60 */ 61 static int vcn_v1_0_early_init(void *handle) 62 { 63 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 64 65 adev->vcn.num_vcn_inst = 1; 66 adev->vcn.num_enc_rings = 2; 67 68 vcn_v1_0_set_dec_ring_funcs(adev); 69 vcn_v1_0_set_enc_ring_funcs(adev); 70 vcn_v1_0_set_irq_funcs(adev); 71 72 jpeg_v1_0_early_init(handle); 73 74 return 0; 75 } 76 77 /** 78 * vcn_v1_0_sw_init - sw init for VCN block 79 * 80 * @handle: amdgpu_device pointer 81 * 82 * Load firmware and sw initialization 83 */ 84 static int vcn_v1_0_sw_init(void *handle) 85 { 86 struct amdgpu_ring *ring; 87 int i, r; 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 90 /* VCN DEC TRAP */ 91 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 92 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 93 if (r) 94 return r; 95 96 /* VCN ENC TRAP */ 97 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 98 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 99 &adev->vcn.inst->irq); 100 if (r) 101 return r; 102 } 103 104 r = amdgpu_vcn_sw_init(adev); 105 if (r) 106 return r; 107 108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 109 const struct common_firmware_header *hdr; 110 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 111 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 112 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 113 adev->firmware.fw_size += 114 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 115 DRM_INFO("PSP loading VCN firmware\n"); 116 } 117 118 r = amdgpu_vcn_resume(adev); 119 if (r) 120 return r; 121 122 ring = &adev->vcn.inst->ring_dec; 123 sprintf(ring->name, "vcn_dec"); 124 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 125 if (r) 126 return r; 127 128 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 129 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 130 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 131 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 132 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 133 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 134 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 135 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 136 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 137 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 138 139 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 140 ring = &adev->vcn.inst->ring_enc[i]; 141 sprintf(ring->name, "vcn_enc%d", i); 142 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 143 if (r) 144 return r; 145 } 146 147 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 148 149 r = jpeg_v1_0_sw_init(handle); 150 151 return r; 152 } 153 154 /** 155 * vcn_v1_0_sw_fini - sw fini for VCN block 156 * 157 * @handle: amdgpu_device pointer 158 * 159 * VCN suspend and free up sw allocation 160 */ 161 static int vcn_v1_0_sw_fini(void *handle) 162 { 163 int r; 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 166 r = amdgpu_vcn_suspend(adev); 167 if (r) 168 return r; 169 170 jpeg_v1_0_sw_fini(handle); 171 172 r = amdgpu_vcn_sw_fini(adev); 173 174 return r; 175 } 176 177 /** 178 * vcn_v1_0_hw_init - start and test VCN block 179 * 180 * @handle: amdgpu_device pointer 181 * 182 * Initialize the hardware, boot up the VCPU and do some testing 183 */ 184 static int vcn_v1_0_hw_init(void *handle) 185 { 186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 187 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 188 int i, r; 189 190 r = amdgpu_ring_test_helper(ring); 191 if (r) 192 goto done; 193 194 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 195 ring = &adev->vcn.inst->ring_enc[i]; 196 r = amdgpu_ring_test_helper(ring); 197 if (r) 198 goto done; 199 } 200 201 ring = &adev->jpeg.inst->ring_dec; 202 r = amdgpu_ring_test_helper(ring); 203 if (r) 204 goto done; 205 206 done: 207 if (!r) 208 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 209 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 210 211 return r; 212 } 213 214 /** 215 * vcn_v1_0_hw_fini - stop the hardware block 216 * 217 * @handle: amdgpu_device pointer 218 * 219 * Stop the VCN block, mark ring as not ready any more 220 */ 221 static int vcn_v1_0_hw_fini(void *handle) 222 { 223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 224 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 225 226 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 227 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 228 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 229 230 ring->sched.ready = false; 231 232 return 0; 233 } 234 235 /** 236 * vcn_v1_0_suspend - suspend VCN block 237 * 238 * @handle: amdgpu_device pointer 239 * 240 * HW fini and suspend VCN block 241 */ 242 static int vcn_v1_0_suspend(void *handle) 243 { 244 int r; 245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 246 247 r = vcn_v1_0_hw_fini(adev); 248 if (r) 249 return r; 250 251 r = amdgpu_vcn_suspend(adev); 252 253 return r; 254 } 255 256 /** 257 * vcn_v1_0_resume - resume VCN block 258 * 259 * @handle: amdgpu_device pointer 260 * 261 * Resume firmware and hw init VCN block 262 */ 263 static int vcn_v1_0_resume(void *handle) 264 { 265 int r; 266 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 267 268 r = amdgpu_vcn_resume(adev); 269 if (r) 270 return r; 271 272 r = vcn_v1_0_hw_init(adev); 273 274 return r; 275 } 276 277 /** 278 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 279 * 280 * @adev: amdgpu_device pointer 281 * 282 * Let the VCN memory controller know it's offsets 283 */ 284 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 285 { 286 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 287 uint32_t offset; 288 289 /* cache window 0: fw */ 290 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 291 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 292 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 293 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 294 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 295 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 296 offset = 0; 297 } else { 298 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 299 lower_32_bits(adev->vcn.inst->gpu_addr)); 300 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 301 upper_32_bits(adev->vcn.inst->gpu_addr)); 302 offset = size; 303 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 304 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 305 } 306 307 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 308 309 /* cache window 1: stack */ 310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 311 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 312 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 313 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 314 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 315 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 316 317 /* cache window 2: context */ 318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 319 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 320 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 321 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 322 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 323 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 324 325 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 326 adev->gfx.config.gb_addr_config); 327 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 328 adev->gfx.config.gb_addr_config); 329 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 330 adev->gfx.config.gb_addr_config); 331 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 332 adev->gfx.config.gb_addr_config); 333 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 334 adev->gfx.config.gb_addr_config); 335 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 336 adev->gfx.config.gb_addr_config); 337 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 338 adev->gfx.config.gb_addr_config); 339 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 340 adev->gfx.config.gb_addr_config); 341 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 342 adev->gfx.config.gb_addr_config); 343 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 344 adev->gfx.config.gb_addr_config); 345 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 346 adev->gfx.config.gb_addr_config); 347 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 348 adev->gfx.config.gb_addr_config); 349 } 350 351 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 352 { 353 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 354 uint32_t offset; 355 356 /* cache window 0: fw */ 357 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 358 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 359 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 360 0xFFFFFFFF, 0); 361 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 362 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 363 0xFFFFFFFF, 0); 364 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 365 0xFFFFFFFF, 0); 366 offset = 0; 367 } else { 368 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 369 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 370 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 371 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 372 offset = size; 373 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 374 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 375 } 376 377 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 378 379 /* cache window 1: stack */ 380 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 381 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 382 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 383 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 384 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 385 0xFFFFFFFF, 0); 386 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 387 0xFFFFFFFF, 0); 388 389 /* cache window 2: context */ 390 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 391 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 392 0xFFFFFFFF, 0); 393 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 394 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 395 0xFFFFFFFF, 0); 396 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 397 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 398 0xFFFFFFFF, 0); 399 400 /* VCN global tiling registers */ 401 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 402 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 403 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 404 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 405 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 406 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 407 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 408 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 409 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 410 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 411 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 412 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 413 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 414 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 415 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 416 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 417 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 418 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 419 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 420 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 421 } 422 423 /** 424 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 425 * 426 * @adev: amdgpu_device pointer 427 * @sw: enable SW clock gating 428 * 429 * Disable clock gating for VCN block 430 */ 431 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 432 { 433 uint32_t data; 434 435 /* JPEG disable CGC */ 436 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 437 438 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 439 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 440 else 441 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 442 443 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 444 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 445 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 446 447 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 448 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 449 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 450 451 /* UVD disable CGC */ 452 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 453 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 454 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 455 else 456 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 457 458 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 459 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 460 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 461 462 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 463 data &= ~(UVD_CGC_GATE__SYS_MASK 464 | UVD_CGC_GATE__UDEC_MASK 465 | UVD_CGC_GATE__MPEG2_MASK 466 | UVD_CGC_GATE__REGS_MASK 467 | UVD_CGC_GATE__RBC_MASK 468 | UVD_CGC_GATE__LMI_MC_MASK 469 | UVD_CGC_GATE__LMI_UMC_MASK 470 | UVD_CGC_GATE__IDCT_MASK 471 | UVD_CGC_GATE__MPRD_MASK 472 | UVD_CGC_GATE__MPC_MASK 473 | UVD_CGC_GATE__LBSI_MASK 474 | UVD_CGC_GATE__LRBBM_MASK 475 | UVD_CGC_GATE__UDEC_RE_MASK 476 | UVD_CGC_GATE__UDEC_CM_MASK 477 | UVD_CGC_GATE__UDEC_IT_MASK 478 | UVD_CGC_GATE__UDEC_DB_MASK 479 | UVD_CGC_GATE__UDEC_MP_MASK 480 | UVD_CGC_GATE__WCB_MASK 481 | UVD_CGC_GATE__VCPU_MASK 482 | UVD_CGC_GATE__SCPU_MASK); 483 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 484 485 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 486 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 487 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 488 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 489 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 490 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 491 | UVD_CGC_CTRL__SYS_MODE_MASK 492 | UVD_CGC_CTRL__UDEC_MODE_MASK 493 | UVD_CGC_CTRL__MPEG2_MODE_MASK 494 | UVD_CGC_CTRL__REGS_MODE_MASK 495 | UVD_CGC_CTRL__RBC_MODE_MASK 496 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 497 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 498 | UVD_CGC_CTRL__IDCT_MODE_MASK 499 | UVD_CGC_CTRL__MPRD_MODE_MASK 500 | UVD_CGC_CTRL__MPC_MODE_MASK 501 | UVD_CGC_CTRL__LBSI_MODE_MASK 502 | UVD_CGC_CTRL__LRBBM_MODE_MASK 503 | UVD_CGC_CTRL__WCB_MODE_MASK 504 | UVD_CGC_CTRL__VCPU_MODE_MASK 505 | UVD_CGC_CTRL__SCPU_MODE_MASK); 506 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 507 508 /* turn on */ 509 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 510 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 511 | UVD_SUVD_CGC_GATE__SIT_MASK 512 | UVD_SUVD_CGC_GATE__SMP_MASK 513 | UVD_SUVD_CGC_GATE__SCM_MASK 514 | UVD_SUVD_CGC_GATE__SDB_MASK 515 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 516 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 517 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 518 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 519 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 520 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 521 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 522 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 523 | UVD_SUVD_CGC_GATE__SCLR_MASK 524 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 525 | UVD_SUVD_CGC_GATE__ENT_MASK 526 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 527 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 528 | UVD_SUVD_CGC_GATE__SITE_MASK 529 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 530 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 531 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 532 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 533 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 534 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 535 536 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 537 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 538 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 539 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 540 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 541 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 542 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 543 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 544 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 545 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 546 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 547 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 548 } 549 550 /** 551 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 552 * 553 * @adev: amdgpu_device pointer 554 * @sw: enable SW clock gating 555 * 556 * Enable clock gating for VCN block 557 */ 558 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 559 { 560 uint32_t data = 0; 561 562 /* enable JPEG CGC */ 563 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 564 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 565 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 566 else 567 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 568 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 569 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 570 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 571 572 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 573 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 574 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 575 576 /* enable UVD CGC */ 577 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 578 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 579 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 580 else 581 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 582 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 583 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 584 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 585 586 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 587 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 588 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 589 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 590 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 591 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 592 | UVD_CGC_CTRL__SYS_MODE_MASK 593 | UVD_CGC_CTRL__UDEC_MODE_MASK 594 | UVD_CGC_CTRL__MPEG2_MODE_MASK 595 | UVD_CGC_CTRL__REGS_MODE_MASK 596 | UVD_CGC_CTRL__RBC_MODE_MASK 597 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 598 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 599 | UVD_CGC_CTRL__IDCT_MODE_MASK 600 | UVD_CGC_CTRL__MPRD_MODE_MASK 601 | UVD_CGC_CTRL__MPC_MODE_MASK 602 | UVD_CGC_CTRL__LBSI_MODE_MASK 603 | UVD_CGC_CTRL__LRBBM_MODE_MASK 604 | UVD_CGC_CTRL__WCB_MODE_MASK 605 | UVD_CGC_CTRL__VCPU_MODE_MASK 606 | UVD_CGC_CTRL__SCPU_MODE_MASK); 607 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 608 609 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 610 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 611 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 612 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 613 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 614 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 615 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 616 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 617 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 618 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 619 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 620 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 621 } 622 623 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 624 { 625 uint32_t reg_data = 0; 626 627 /* disable JPEG CGC */ 628 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 629 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 630 else 631 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 632 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 633 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 634 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 635 636 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 637 638 /* enable sw clock gating control */ 639 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 640 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 641 else 642 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 643 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 644 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 645 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 646 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 647 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 648 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 649 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 650 UVD_CGC_CTRL__SYS_MODE_MASK | 651 UVD_CGC_CTRL__UDEC_MODE_MASK | 652 UVD_CGC_CTRL__MPEG2_MODE_MASK | 653 UVD_CGC_CTRL__REGS_MODE_MASK | 654 UVD_CGC_CTRL__RBC_MODE_MASK | 655 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 656 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 657 UVD_CGC_CTRL__IDCT_MODE_MASK | 658 UVD_CGC_CTRL__MPRD_MODE_MASK | 659 UVD_CGC_CTRL__MPC_MODE_MASK | 660 UVD_CGC_CTRL__LBSI_MODE_MASK | 661 UVD_CGC_CTRL__LRBBM_MODE_MASK | 662 UVD_CGC_CTRL__WCB_MODE_MASK | 663 UVD_CGC_CTRL__VCPU_MODE_MASK | 664 UVD_CGC_CTRL__SCPU_MODE_MASK); 665 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 666 667 /* turn off clock gating */ 668 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 669 670 /* turn on SUVD clock gating */ 671 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 672 673 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 674 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 675 } 676 677 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 678 { 679 uint32_t data = 0; 680 int ret; 681 682 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 683 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 684 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 686 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 687 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 688 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 689 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 690 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 691 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 692 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 693 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 694 695 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 696 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 697 } else { 698 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 699 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 700 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 709 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 710 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 711 } 712 713 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 714 715 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 716 data &= ~0x103; 717 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 718 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 719 720 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 721 } 722 723 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 724 { 725 uint32_t data = 0; 726 int ret; 727 728 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 729 /* Before power off, this indicator has to be turned on */ 730 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 731 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 732 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 733 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 734 735 736 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 737 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 738 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 739 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 740 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 746 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 747 748 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 749 750 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 751 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 752 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 753 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 754 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 755 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 756 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 760 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 761 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 762 } 763 } 764 765 /** 766 * vcn_v1_0_start - start VCN block 767 * 768 * @adev: amdgpu_device pointer 769 * 770 * Setup and start the VCN block 771 */ 772 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 773 { 774 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 775 uint32_t rb_bufsz, tmp; 776 uint32_t lmi_swap_cntl; 777 int i, j, r; 778 779 /* disable byte swapping */ 780 lmi_swap_cntl = 0; 781 782 vcn_1_0_disable_static_power_gating(adev); 783 784 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 785 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 786 787 /* disable clock gating */ 788 vcn_v1_0_disable_clock_gating(adev); 789 790 /* disable interupt */ 791 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 792 ~UVD_MASTINT_EN__VCPU_EN_MASK); 793 794 /* initialize VCN memory controller */ 795 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 796 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 797 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 798 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 799 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 800 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 801 802 #ifdef __BIG_ENDIAN 803 /* swap (8 in 32) RB and IB */ 804 lmi_swap_cntl = 0xa; 805 #endif 806 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 807 808 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 809 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 810 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 811 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 812 813 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 814 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 815 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 816 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 817 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 818 819 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 820 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 821 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 822 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 823 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 824 825 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 826 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 827 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 828 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 829 830 vcn_v1_0_mc_resume_spg_mode(adev); 831 832 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10); 833 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 834 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); 835 836 /* enable VCPU clock */ 837 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 838 839 /* boot up the VCPU */ 840 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 841 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 842 843 /* enable UMC */ 844 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 845 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 846 847 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 848 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 849 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 850 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 851 852 for (i = 0; i < 10; ++i) { 853 uint32_t status; 854 855 for (j = 0; j < 100; ++j) { 856 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 857 if (status & UVD_STATUS__IDLE) 858 break; 859 mdelay(10); 860 } 861 r = 0; 862 if (status & UVD_STATUS__IDLE) 863 break; 864 865 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 866 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 867 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 868 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 869 mdelay(10); 870 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 871 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 872 mdelay(10); 873 r = -1; 874 } 875 876 if (r) { 877 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 878 return r; 879 } 880 /* enable master interrupt */ 881 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 882 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 883 884 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 885 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 886 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 887 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 888 889 /* clear the busy bit of UVD_STATUS */ 890 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 891 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 892 893 /* force RBC into idle state */ 894 rb_bufsz = order_base_2(ring->ring_size); 895 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 896 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 897 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 898 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 899 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 900 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 901 902 /* set the write pointer delay */ 903 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 904 905 /* set the wb address */ 906 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 907 (upper_32_bits(ring->gpu_addr) >> 2)); 908 909 /* programm the RB_BASE for ring buffer */ 910 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 911 lower_32_bits(ring->gpu_addr)); 912 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 913 upper_32_bits(ring->gpu_addr)); 914 915 /* Initialize the ring buffer's read and write pointers */ 916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 917 918 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 919 920 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 921 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 922 lower_32_bits(ring->wptr)); 923 924 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 925 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 926 927 ring = &adev->vcn.inst->ring_enc[0]; 928 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 929 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 930 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 931 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 932 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 933 934 ring = &adev->vcn.inst->ring_enc[1]; 935 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 936 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 937 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 938 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 939 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 940 941 jpeg_v1_0_start(adev, 0); 942 943 return 0; 944 } 945 946 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 947 { 948 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 949 uint32_t rb_bufsz, tmp; 950 uint32_t lmi_swap_cntl; 951 952 /* disable byte swapping */ 953 lmi_swap_cntl = 0; 954 955 vcn_1_0_enable_static_power_gating(adev); 956 957 /* enable dynamic power gating mode */ 958 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 959 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 960 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 961 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 962 963 /* enable clock gating */ 964 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 965 966 /* enable VCPU clock */ 967 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 968 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 969 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 970 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 971 972 /* disable interupt */ 973 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 974 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 975 976 /* initialize VCN memory controller */ 977 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 978 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 979 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 980 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 981 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 982 UVD_LMI_CTRL__REQ_MODE_MASK | 983 UVD_LMI_CTRL__CRC_RESET_MASK | 984 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 985 0x00100000L, 0xFFFFFFFF, 0); 986 987 #ifdef __BIG_ENDIAN 988 /* swap (8 in 32) RB and IB */ 989 lmi_swap_cntl = 0xa; 990 #endif 991 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 992 993 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, 994 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 995 996 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 997 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 998 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 999 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1000 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1001 1002 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 1003 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1004 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1005 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1006 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1007 1008 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 1009 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1010 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1011 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1012 1013 vcn_v1_0_mc_resume_dpg_mode(adev); 1014 1015 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1016 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1017 1018 /* boot up the VCPU */ 1019 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1020 1021 /* enable UMC */ 1022 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1023 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1024 0xFFFFFFFF, 0); 1025 1026 /* enable master interrupt */ 1027 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1028 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1029 1030 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1031 /* setup mmUVD_LMI_CTRL */ 1032 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1033 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1034 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1035 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1036 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1037 UVD_LMI_CTRL__REQ_MODE_MASK | 1038 UVD_LMI_CTRL__CRC_RESET_MASK | 1039 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1040 0x00100000L, 0xFFFFFFFF, 1); 1041 1042 tmp = adev->gfx.config.gb_addr_config; 1043 /* setup VCN global tiling registers */ 1044 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1045 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1046 1047 /* enable System Interrupt for JRBC */ 1048 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, 1049 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1050 1051 /* force RBC into idle state */ 1052 rb_bufsz = order_base_2(ring->ring_size); 1053 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1054 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1055 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1056 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1058 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1059 1060 /* set the write pointer delay */ 1061 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1062 1063 /* set the wb address */ 1064 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1065 (upper_32_bits(ring->gpu_addr) >> 2)); 1066 1067 /* programm the RB_BASE for ring buffer */ 1068 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1069 lower_32_bits(ring->gpu_addr)); 1070 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1071 upper_32_bits(ring->gpu_addr)); 1072 1073 /* Initialize the ring buffer's read and write pointers */ 1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1075 1076 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1077 1078 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1079 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1080 lower_32_bits(ring->wptr)); 1081 1082 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1083 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1084 1085 jpeg_v1_0_start(adev, 1); 1086 1087 return 0; 1088 } 1089 1090 static int vcn_v1_0_start(struct amdgpu_device *adev) 1091 { 1092 int r; 1093 1094 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1095 r = vcn_v1_0_start_dpg_mode(adev); 1096 else 1097 r = vcn_v1_0_start_spg_mode(adev); 1098 return r; 1099 } 1100 1101 /** 1102 * vcn_v1_0_stop - stop VCN block 1103 * 1104 * @adev: amdgpu_device pointer 1105 * 1106 * stop the VCN block 1107 */ 1108 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1109 { 1110 int ret_code, tmp; 1111 1112 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1113 1114 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1115 UVD_LMI_STATUS__READ_CLEAN_MASK | 1116 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1117 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1119 1120 /* put VCPU into reset */ 1121 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1122 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1123 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1124 1125 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1126 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1127 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1128 1129 /* disable VCPU clock */ 1130 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1131 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1132 1133 /* reset LMI UMC/LMI */ 1134 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1135 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1136 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1137 1138 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1139 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1140 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1141 1142 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1143 1144 vcn_v1_0_enable_clock_gating(adev); 1145 vcn_1_0_enable_static_power_gating(adev); 1146 return 0; 1147 } 1148 1149 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1150 { 1151 int ret_code = 0; 1152 uint32_t tmp; 1153 1154 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1155 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1156 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1157 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1158 1159 /* wait for read ptr to be equal to write ptr */ 1160 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1161 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1162 1163 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1164 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1165 1166 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1167 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1168 1169 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1170 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1171 1172 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1173 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1174 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1175 1176 /* disable dynamic power gating mode */ 1177 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1178 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1179 1180 return 0; 1181 } 1182 1183 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1184 { 1185 int r; 1186 1187 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1188 r = vcn_v1_0_stop_dpg_mode(adev); 1189 else 1190 r = vcn_v1_0_stop_spg_mode(adev); 1191 1192 return r; 1193 } 1194 1195 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1196 struct dpg_pause_state *new_state) 1197 { 1198 int ret_code; 1199 uint32_t reg_data = 0; 1200 uint32_t reg_data2 = 0; 1201 struct amdgpu_ring *ring; 1202 1203 /* pause/unpause if state is changed */ 1204 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { 1205 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1206 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, 1207 new_state->fw_based, new_state->jpeg); 1208 1209 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1210 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1211 1212 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1213 ret_code = 0; 1214 1215 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1216 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1217 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1218 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1219 1220 if (!ret_code) { 1221 /* pause DPG non-jpeg */ 1222 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1223 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1224 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1225 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1226 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1227 1228 /* Restore */ 1229 ring = &adev->vcn.inst->ring_enc[0]; 1230 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1231 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1232 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1233 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1234 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1235 1236 ring = &adev->vcn.inst->ring_enc[1]; 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1238 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1239 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1240 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1241 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1242 1243 ring = &adev->vcn.inst->ring_dec; 1244 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1245 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1246 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1247 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1248 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1249 } 1250 } else { 1251 /* unpause dpg non-jpeg, no need to wait */ 1252 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1253 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1254 } 1255 adev->vcn.pause_state.fw_based = new_state->fw_based; 1256 } 1257 1258 /* pause/unpause if state is changed */ 1259 if (adev->vcn.pause_state.jpeg != new_state->jpeg) { 1260 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1261 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, 1262 new_state->fw_based, new_state->jpeg); 1263 1264 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1265 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1266 1267 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1268 ret_code = 0; 1269 1270 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1271 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1272 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1273 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1274 1275 if (!ret_code) { 1276 /* Make sure JPRG Snoop is disabled before sending the pause */ 1277 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1278 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1279 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1280 1281 /* pause DPG jpeg */ 1282 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1283 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1284 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1285 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1286 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); 1287 1288 /* Restore */ 1289 ring = &adev->jpeg.inst->ring_dec; 1290 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1291 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1292 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1293 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1294 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1295 lower_32_bits(ring->gpu_addr)); 1296 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1297 upper_32_bits(ring->gpu_addr)); 1298 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1299 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1300 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1301 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1302 1303 ring = &adev->vcn.inst->ring_dec; 1304 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1305 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1306 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1307 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1308 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1309 } 1310 } else { 1311 /* unpause dpg jpeg, no need to wait */ 1312 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1313 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1314 } 1315 adev->vcn.pause_state.jpeg = new_state->jpeg; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static bool vcn_v1_0_is_idle(void *handle) 1322 { 1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1324 1325 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1326 } 1327 1328 static int vcn_v1_0_wait_for_idle(void *handle) 1329 { 1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1331 int ret = 0; 1332 1333 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1334 UVD_STATUS__IDLE, ret); 1335 1336 return ret; 1337 } 1338 1339 static int vcn_v1_0_set_clockgating_state(void *handle, 1340 enum amd_clockgating_state state) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1344 1345 if (enable) { 1346 /* wait for STATUS to clear */ 1347 if (vcn_v1_0_is_idle(handle)) 1348 return -EBUSY; 1349 vcn_v1_0_enable_clock_gating(adev); 1350 } else { 1351 /* disable HW gating and enable Sw gating */ 1352 vcn_v1_0_disable_clock_gating(adev); 1353 } 1354 return 0; 1355 } 1356 1357 /** 1358 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1359 * 1360 * @ring: amdgpu_ring pointer 1361 * 1362 * Returns the current hardware read pointer 1363 */ 1364 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1365 { 1366 struct amdgpu_device *adev = ring->adev; 1367 1368 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1369 } 1370 1371 /** 1372 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1373 * 1374 * @ring: amdgpu_ring pointer 1375 * 1376 * Returns the current hardware write pointer 1377 */ 1378 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1379 { 1380 struct amdgpu_device *adev = ring->adev; 1381 1382 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1383 } 1384 1385 /** 1386 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1387 * 1388 * @ring: amdgpu_ring pointer 1389 * 1390 * Commits the write pointer to the hardware 1391 */ 1392 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1393 { 1394 struct amdgpu_device *adev = ring->adev; 1395 1396 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1397 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1398 lower_32_bits(ring->wptr) | 0x80000000); 1399 1400 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1401 } 1402 1403 /** 1404 * vcn_v1_0_dec_ring_insert_start - insert a start command 1405 * 1406 * @ring: amdgpu_ring pointer 1407 * 1408 * Write a start command to the ring. 1409 */ 1410 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1411 { 1412 struct amdgpu_device *adev = ring->adev; 1413 1414 amdgpu_ring_write(ring, 1415 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1416 amdgpu_ring_write(ring, 0); 1417 amdgpu_ring_write(ring, 1418 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1419 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1420 } 1421 1422 /** 1423 * vcn_v1_0_dec_ring_insert_end - insert a end command 1424 * 1425 * @ring: amdgpu_ring pointer 1426 * 1427 * Write a end command to the ring. 1428 */ 1429 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1430 { 1431 struct amdgpu_device *adev = ring->adev; 1432 1433 amdgpu_ring_write(ring, 1434 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1435 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1436 } 1437 1438 /** 1439 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1440 * 1441 * @ring: amdgpu_ring pointer 1442 * @fence: fence to emit 1443 * 1444 * Write a fence and a trap command to the ring. 1445 */ 1446 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1447 unsigned flags) 1448 { 1449 struct amdgpu_device *adev = ring->adev; 1450 1451 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1452 1453 amdgpu_ring_write(ring, 1454 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1455 amdgpu_ring_write(ring, seq); 1456 amdgpu_ring_write(ring, 1457 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1458 amdgpu_ring_write(ring, addr & 0xffffffff); 1459 amdgpu_ring_write(ring, 1460 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1461 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1462 amdgpu_ring_write(ring, 1463 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1464 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1465 1466 amdgpu_ring_write(ring, 1467 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1468 amdgpu_ring_write(ring, 0); 1469 amdgpu_ring_write(ring, 1470 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1471 amdgpu_ring_write(ring, 0); 1472 amdgpu_ring_write(ring, 1473 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1474 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1475 } 1476 1477 /** 1478 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1479 * 1480 * @ring: amdgpu_ring pointer 1481 * @ib: indirect buffer to execute 1482 * 1483 * Write ring commands to execute the indirect buffer 1484 */ 1485 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1486 struct amdgpu_job *job, 1487 struct amdgpu_ib *ib, 1488 uint32_t flags) 1489 { 1490 struct amdgpu_device *adev = ring->adev; 1491 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1492 1493 amdgpu_ring_write(ring, 1494 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1495 amdgpu_ring_write(ring, vmid); 1496 1497 amdgpu_ring_write(ring, 1498 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1499 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1500 amdgpu_ring_write(ring, 1501 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1502 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1503 amdgpu_ring_write(ring, 1504 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1505 amdgpu_ring_write(ring, ib->length_dw); 1506 } 1507 1508 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1509 uint32_t reg, uint32_t val, 1510 uint32_t mask) 1511 { 1512 struct amdgpu_device *adev = ring->adev; 1513 1514 amdgpu_ring_write(ring, 1515 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1516 amdgpu_ring_write(ring, reg << 2); 1517 amdgpu_ring_write(ring, 1518 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1519 amdgpu_ring_write(ring, val); 1520 amdgpu_ring_write(ring, 1521 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1522 amdgpu_ring_write(ring, mask); 1523 amdgpu_ring_write(ring, 1524 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1525 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1526 } 1527 1528 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1529 unsigned vmid, uint64_t pd_addr) 1530 { 1531 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1532 uint32_t data0, data1, mask; 1533 1534 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1535 1536 /* wait for register write */ 1537 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1538 data1 = lower_32_bits(pd_addr); 1539 mask = 0xffffffff; 1540 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1541 } 1542 1543 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1544 uint32_t reg, uint32_t val) 1545 { 1546 struct amdgpu_device *adev = ring->adev; 1547 1548 amdgpu_ring_write(ring, 1549 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1550 amdgpu_ring_write(ring, reg << 2); 1551 amdgpu_ring_write(ring, 1552 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1553 amdgpu_ring_write(ring, val); 1554 amdgpu_ring_write(ring, 1555 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1556 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1557 } 1558 1559 /** 1560 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1561 * 1562 * @ring: amdgpu_ring pointer 1563 * 1564 * Returns the current hardware enc read pointer 1565 */ 1566 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1567 { 1568 struct amdgpu_device *adev = ring->adev; 1569 1570 if (ring == &adev->vcn.inst->ring_enc[0]) 1571 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1572 else 1573 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1574 } 1575 1576 /** 1577 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1578 * 1579 * @ring: amdgpu_ring pointer 1580 * 1581 * Returns the current hardware enc write pointer 1582 */ 1583 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1584 { 1585 struct amdgpu_device *adev = ring->adev; 1586 1587 if (ring == &adev->vcn.inst->ring_enc[0]) 1588 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1589 else 1590 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1591 } 1592 1593 /** 1594 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1595 * 1596 * @ring: amdgpu_ring pointer 1597 * 1598 * Commits the enc write pointer to the hardware 1599 */ 1600 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1601 { 1602 struct amdgpu_device *adev = ring->adev; 1603 1604 if (ring == &adev->vcn.inst->ring_enc[0]) 1605 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1606 lower_32_bits(ring->wptr)); 1607 else 1608 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1609 lower_32_bits(ring->wptr)); 1610 } 1611 1612 /** 1613 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1614 * 1615 * @ring: amdgpu_ring pointer 1616 * @fence: fence to emit 1617 * 1618 * Write enc a fence and a trap command to the ring. 1619 */ 1620 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1621 u64 seq, unsigned flags) 1622 { 1623 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1624 1625 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1626 amdgpu_ring_write(ring, addr); 1627 amdgpu_ring_write(ring, upper_32_bits(addr)); 1628 amdgpu_ring_write(ring, seq); 1629 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1630 } 1631 1632 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1633 { 1634 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1635 } 1636 1637 /** 1638 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1639 * 1640 * @ring: amdgpu_ring pointer 1641 * @ib: indirect buffer to execute 1642 * 1643 * Write enc ring commands to execute the indirect buffer 1644 */ 1645 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1646 struct amdgpu_job *job, 1647 struct amdgpu_ib *ib, 1648 uint32_t flags) 1649 { 1650 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1651 1652 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1653 amdgpu_ring_write(ring, vmid); 1654 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1655 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1656 amdgpu_ring_write(ring, ib->length_dw); 1657 } 1658 1659 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1660 uint32_t reg, uint32_t val, 1661 uint32_t mask) 1662 { 1663 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1664 amdgpu_ring_write(ring, reg << 2); 1665 amdgpu_ring_write(ring, mask); 1666 amdgpu_ring_write(ring, val); 1667 } 1668 1669 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1670 unsigned int vmid, uint64_t pd_addr) 1671 { 1672 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1673 1674 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1675 1676 /* wait for reg writes */ 1677 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1678 lower_32_bits(pd_addr), 0xffffffff); 1679 } 1680 1681 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1682 uint32_t reg, uint32_t val) 1683 { 1684 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1685 amdgpu_ring_write(ring, reg << 2); 1686 amdgpu_ring_write(ring, val); 1687 } 1688 1689 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1690 struct amdgpu_irq_src *source, 1691 unsigned type, 1692 enum amdgpu_interrupt_state state) 1693 { 1694 return 0; 1695 } 1696 1697 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1698 struct amdgpu_irq_src *source, 1699 struct amdgpu_iv_entry *entry) 1700 { 1701 DRM_DEBUG("IH: VCN TRAP\n"); 1702 1703 switch (entry->src_id) { 1704 case 124: 1705 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1706 break; 1707 case 119: 1708 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1709 break; 1710 case 120: 1711 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1712 break; 1713 default: 1714 DRM_ERROR("Unhandled interrupt: %d %d\n", 1715 entry->src_id, entry->src_data[0]); 1716 break; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1723 { 1724 struct amdgpu_device *adev = ring->adev; 1725 int i; 1726 1727 WARN_ON(ring->wptr % 2 || count % 2); 1728 1729 for (i = 0; i < count / 2; i++) { 1730 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1731 amdgpu_ring_write(ring, 0); 1732 } 1733 } 1734 1735 static int vcn_v1_0_set_powergating_state(void *handle, 1736 enum amd_powergating_state state) 1737 { 1738 /* This doesn't actually powergate the VCN block. 1739 * That's done in the dpm code via the SMC. This 1740 * just re-inits the block as necessary. The actual 1741 * gating still happens in the dpm code. We should 1742 * revisit this when there is a cleaner line between 1743 * the smc and the hw blocks 1744 */ 1745 int ret; 1746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1747 1748 if(state == adev->vcn.cur_state) 1749 return 0; 1750 1751 if (state == AMD_PG_STATE_GATE) 1752 ret = vcn_v1_0_stop(adev); 1753 else 1754 ret = vcn_v1_0_start(adev); 1755 1756 if(!ret) 1757 adev->vcn.cur_state = state; 1758 return ret; 1759 } 1760 1761 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1762 .name = "vcn_v1_0", 1763 .early_init = vcn_v1_0_early_init, 1764 .late_init = NULL, 1765 .sw_init = vcn_v1_0_sw_init, 1766 .sw_fini = vcn_v1_0_sw_fini, 1767 .hw_init = vcn_v1_0_hw_init, 1768 .hw_fini = vcn_v1_0_hw_fini, 1769 .suspend = vcn_v1_0_suspend, 1770 .resume = vcn_v1_0_resume, 1771 .is_idle = vcn_v1_0_is_idle, 1772 .wait_for_idle = vcn_v1_0_wait_for_idle, 1773 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1774 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1775 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1776 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1777 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1778 .set_powergating_state = vcn_v1_0_set_powergating_state, 1779 }; 1780 1781 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1782 .type = AMDGPU_RING_TYPE_VCN_DEC, 1783 .align_mask = 0xf, 1784 .support_64bit_ptrs = false, 1785 .no_user_fence = true, 1786 .vmhub = AMDGPU_MMHUB_0, 1787 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1788 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1789 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1790 .emit_frame_size = 1791 6 + 6 + /* hdp invalidate / flush */ 1792 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1793 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1794 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1795 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1796 6, 1797 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1798 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1799 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1800 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1801 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1802 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1803 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1804 .insert_start = vcn_v1_0_dec_ring_insert_start, 1805 .insert_end = vcn_v1_0_dec_ring_insert_end, 1806 .pad_ib = amdgpu_ring_generic_pad_ib, 1807 .begin_use = amdgpu_vcn_ring_begin_use, 1808 .end_use = amdgpu_vcn_ring_end_use, 1809 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1810 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1811 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1812 }; 1813 1814 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1815 .type = AMDGPU_RING_TYPE_VCN_ENC, 1816 .align_mask = 0x3f, 1817 .nop = VCN_ENC_CMD_NO_OP, 1818 .support_64bit_ptrs = false, 1819 .no_user_fence = true, 1820 .vmhub = AMDGPU_MMHUB_0, 1821 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1822 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1823 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1824 .emit_frame_size = 1825 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1826 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1827 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1828 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1829 1, /* vcn_v1_0_enc_ring_insert_end */ 1830 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1831 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1832 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1833 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1834 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1835 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1836 .insert_nop = amdgpu_ring_insert_nop, 1837 .insert_end = vcn_v1_0_enc_ring_insert_end, 1838 .pad_ib = amdgpu_ring_generic_pad_ib, 1839 .begin_use = amdgpu_vcn_ring_begin_use, 1840 .end_use = amdgpu_vcn_ring_end_use, 1841 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1842 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1843 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1844 }; 1845 1846 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1847 { 1848 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1849 DRM_INFO("VCN decode is enabled in VM mode\n"); 1850 } 1851 1852 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1853 { 1854 int i; 1855 1856 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1857 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1858 1859 DRM_INFO("VCN encode is enabled in VM mode\n"); 1860 } 1861 1862 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1863 .set = vcn_v1_0_set_interrupt_state, 1864 .process = vcn_v1_0_process_interrupt, 1865 }; 1866 1867 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1868 { 1869 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 1870 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 1871 } 1872 1873 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1874 { 1875 .type = AMD_IP_BLOCK_TYPE_VCN, 1876 .major = 1, 1877 .minor = 0, 1878 .rev = 0, 1879 .funcs = &vcn_v1_0_ip_funcs, 1880 }; 1881