1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 32 #include "vcn/vcn_1_0_offset.h" 33 #include "vcn/vcn_1_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 40 #define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab 41 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 42 #define mmUVD_REG_XX_MASK 0x05ac 43 #define mmUVD_REG_XX_MASK_BASE_IDX 1 44 45 static int vcn_v1_0_stop(struct amdgpu_device *adev); 46 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 47 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 53 /** 54 * vcn_v1_0_early_init - set function pointers 55 * 56 * @handle: amdgpu_device pointer 57 * 58 * Set ring and irq function pointers 59 */ 60 static int vcn_v1_0_early_init(void *handle) 61 { 62 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 63 64 adev->vcn.num_enc_rings = 2; 65 66 vcn_v1_0_set_dec_ring_funcs(adev); 67 vcn_v1_0_set_enc_ring_funcs(adev); 68 vcn_v1_0_set_jpeg_ring_funcs(adev); 69 vcn_v1_0_set_irq_funcs(adev); 70 71 return 0; 72 } 73 74 /** 75 * vcn_v1_0_sw_init - sw init for VCN block 76 * 77 * @handle: amdgpu_device pointer 78 * 79 * Load firmware and sw initialization 80 */ 81 static int vcn_v1_0_sw_init(void *handle) 82 { 83 struct amdgpu_ring *ring; 84 int i, r; 85 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 86 87 /* VCN DEC TRAP */ 88 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq); 89 if (r) 90 return r; 91 92 /* VCN ENC TRAP */ 93 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 94 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 95 &adev->vcn.irq); 96 if (r) 97 return r; 98 } 99 100 /* VCN JPEG TRAP */ 101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq); 102 if (r) 103 return r; 104 105 r = amdgpu_vcn_sw_init(adev); 106 if (r) 107 return r; 108 109 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 110 const struct common_firmware_header *hdr; 111 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 112 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 113 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 114 adev->firmware.fw_size += 115 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 116 DRM_INFO("PSP loading VCN firmware\n"); 117 } 118 119 r = amdgpu_vcn_resume(adev); 120 if (r) 121 return r; 122 123 ring = &adev->vcn.ring_dec; 124 sprintf(ring->name, "vcn_dec"); 125 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 126 if (r) 127 return r; 128 129 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 130 ring = &adev->vcn.ring_enc[i]; 131 sprintf(ring->name, "vcn_enc%d", i); 132 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 133 if (r) 134 return r; 135 } 136 137 ring = &adev->vcn.ring_jpeg; 138 sprintf(ring->name, "vcn_jpeg"); 139 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 140 if (r) 141 return r; 142 143 return r; 144 } 145 146 /** 147 * vcn_v1_0_sw_fini - sw fini for VCN block 148 * 149 * @handle: amdgpu_device pointer 150 * 151 * VCN suspend and free up sw allocation 152 */ 153 static int vcn_v1_0_sw_fini(void *handle) 154 { 155 int r; 156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 157 158 r = amdgpu_vcn_suspend(adev); 159 if (r) 160 return r; 161 162 r = amdgpu_vcn_sw_fini(adev); 163 164 return r; 165 } 166 167 /** 168 * vcn_v1_0_hw_init - start and test VCN block 169 * 170 * @handle: amdgpu_device pointer 171 * 172 * Initialize the hardware, boot up the VCPU and do some testing 173 */ 174 static int vcn_v1_0_hw_init(void *handle) 175 { 176 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 177 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 178 int i, r; 179 180 ring->ready = true; 181 r = amdgpu_ring_test_ring(ring); 182 if (r) { 183 ring->ready = false; 184 goto done; 185 } 186 187 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 188 ring = &adev->vcn.ring_enc[i]; 189 ring->ready = true; 190 r = amdgpu_ring_test_ring(ring); 191 if (r) { 192 ring->ready = false; 193 goto done; 194 } 195 } 196 197 ring = &adev->vcn.ring_jpeg; 198 ring->ready = true; 199 r = amdgpu_ring_test_ring(ring); 200 if (r) { 201 ring->ready = false; 202 goto done; 203 } 204 205 done: 206 if (!r) 207 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 208 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 209 210 return r; 211 } 212 213 /** 214 * vcn_v1_0_hw_fini - stop the hardware block 215 * 216 * @handle: amdgpu_device pointer 217 * 218 * Stop the VCN block, mark ring as not ready any more 219 */ 220 static int vcn_v1_0_hw_fini(void *handle) 221 { 222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 223 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 224 225 if (RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 226 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 227 228 ring->ready = false; 229 230 return 0; 231 } 232 233 /** 234 * vcn_v1_0_suspend - suspend VCN block 235 * 236 * @handle: amdgpu_device pointer 237 * 238 * HW fini and suspend VCN block 239 */ 240 static int vcn_v1_0_suspend(void *handle) 241 { 242 int r; 243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 244 245 r = vcn_v1_0_hw_fini(adev); 246 if (r) 247 return r; 248 249 r = amdgpu_vcn_suspend(adev); 250 251 return r; 252 } 253 254 /** 255 * vcn_v1_0_resume - resume VCN block 256 * 257 * @handle: amdgpu_device pointer 258 * 259 * Resume firmware and hw init VCN block 260 */ 261 static int vcn_v1_0_resume(void *handle) 262 { 263 int r; 264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 265 266 r = amdgpu_vcn_resume(adev); 267 if (r) 268 return r; 269 270 r = vcn_v1_0_hw_init(adev); 271 272 return r; 273 } 274 275 /** 276 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 277 * 278 * @adev: amdgpu_device pointer 279 * 280 * Let the VCN memory controller know it's offsets 281 */ 282 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 283 { 284 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 285 uint32_t offset; 286 287 /* cache window 0: fw */ 288 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 289 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 290 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 291 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 292 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 293 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 294 offset = 0; 295 } else { 296 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 297 lower_32_bits(adev->vcn.gpu_addr)); 298 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 299 upper_32_bits(adev->vcn.gpu_addr)); 300 offset = size; 301 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 302 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 303 } 304 305 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 306 307 /* cache window 1: stack */ 308 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 309 lower_32_bits(adev->vcn.gpu_addr + offset)); 310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 311 upper_32_bits(adev->vcn.gpu_addr + offset)); 312 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 314 315 /* cache window 2: context */ 316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 317 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 319 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 321 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 322 323 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 324 adev->gfx.config.gb_addr_config); 325 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 326 adev->gfx.config.gb_addr_config); 327 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 328 adev->gfx.config.gb_addr_config); 329 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 330 adev->gfx.config.gb_addr_config); 331 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 332 adev->gfx.config.gb_addr_config); 333 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 334 adev->gfx.config.gb_addr_config); 335 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 336 adev->gfx.config.gb_addr_config); 337 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 338 adev->gfx.config.gb_addr_config); 339 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 340 adev->gfx.config.gb_addr_config); 341 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 342 adev->gfx.config.gb_addr_config); 343 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 344 adev->gfx.config.gb_addr_config); 345 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 346 adev->gfx.config.gb_addr_config); 347 } 348 349 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 350 { 351 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 352 uint32_t offset; 353 354 /* cache window 0: fw */ 355 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 356 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 357 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 358 0xFFFFFFFF, 0); 359 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 360 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 361 0xFFFFFFFF, 0); 362 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 363 0xFFFFFFFF, 0); 364 offset = 0; 365 } else { 366 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 367 lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); 368 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 369 upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); 370 offset = size; 371 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 372 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 373 } 374 375 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 376 377 /* cache window 1: stack */ 378 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 379 lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); 380 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 381 upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); 382 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 383 0xFFFFFFFF, 0); 384 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 385 0xFFFFFFFF, 0); 386 387 /* cache window 2: context */ 388 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 389 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 390 0xFFFFFFFF, 0); 391 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 392 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 393 0xFFFFFFFF, 0); 394 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 395 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 396 0xFFFFFFFF, 0); 397 398 /* VCN global tiling registers */ 399 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 400 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 401 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 402 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 403 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 404 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 405 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 406 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 407 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 408 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 409 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 410 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 411 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 412 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 413 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 414 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 415 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 416 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 417 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 418 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 419 } 420 421 /** 422 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 423 * 424 * @adev: amdgpu_device pointer 425 * @sw: enable SW clock gating 426 * 427 * Disable clock gating for VCN block 428 */ 429 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 430 { 431 uint32_t data; 432 433 /* JPEG disable CGC */ 434 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 435 436 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 437 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 438 else 439 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 440 441 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 442 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 443 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 444 445 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 446 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 447 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 448 449 /* UVD disable CGC */ 450 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 451 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 452 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 453 else 454 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 455 456 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 457 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 458 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 459 460 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 461 data &= ~(UVD_CGC_GATE__SYS_MASK 462 | UVD_CGC_GATE__UDEC_MASK 463 | UVD_CGC_GATE__MPEG2_MASK 464 | UVD_CGC_GATE__REGS_MASK 465 | UVD_CGC_GATE__RBC_MASK 466 | UVD_CGC_GATE__LMI_MC_MASK 467 | UVD_CGC_GATE__LMI_UMC_MASK 468 | UVD_CGC_GATE__IDCT_MASK 469 | UVD_CGC_GATE__MPRD_MASK 470 | UVD_CGC_GATE__MPC_MASK 471 | UVD_CGC_GATE__LBSI_MASK 472 | UVD_CGC_GATE__LRBBM_MASK 473 | UVD_CGC_GATE__UDEC_RE_MASK 474 | UVD_CGC_GATE__UDEC_CM_MASK 475 | UVD_CGC_GATE__UDEC_IT_MASK 476 | UVD_CGC_GATE__UDEC_DB_MASK 477 | UVD_CGC_GATE__UDEC_MP_MASK 478 | UVD_CGC_GATE__WCB_MASK 479 | UVD_CGC_GATE__VCPU_MASK 480 | UVD_CGC_GATE__SCPU_MASK); 481 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 482 483 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 484 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 485 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 486 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 487 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 488 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 489 | UVD_CGC_CTRL__SYS_MODE_MASK 490 | UVD_CGC_CTRL__UDEC_MODE_MASK 491 | UVD_CGC_CTRL__MPEG2_MODE_MASK 492 | UVD_CGC_CTRL__REGS_MODE_MASK 493 | UVD_CGC_CTRL__RBC_MODE_MASK 494 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 495 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 496 | UVD_CGC_CTRL__IDCT_MODE_MASK 497 | UVD_CGC_CTRL__MPRD_MODE_MASK 498 | UVD_CGC_CTRL__MPC_MODE_MASK 499 | UVD_CGC_CTRL__LBSI_MODE_MASK 500 | UVD_CGC_CTRL__LRBBM_MODE_MASK 501 | UVD_CGC_CTRL__WCB_MODE_MASK 502 | UVD_CGC_CTRL__VCPU_MODE_MASK 503 | UVD_CGC_CTRL__SCPU_MODE_MASK); 504 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 505 506 /* turn on */ 507 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 508 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 509 | UVD_SUVD_CGC_GATE__SIT_MASK 510 | UVD_SUVD_CGC_GATE__SMP_MASK 511 | UVD_SUVD_CGC_GATE__SCM_MASK 512 | UVD_SUVD_CGC_GATE__SDB_MASK 513 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 514 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 515 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 516 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 517 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 518 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 519 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 520 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 521 | UVD_SUVD_CGC_GATE__SCLR_MASK 522 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 523 | UVD_SUVD_CGC_GATE__ENT_MASK 524 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 525 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 526 | UVD_SUVD_CGC_GATE__SITE_MASK 527 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 528 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 529 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 530 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 531 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 532 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 533 534 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 535 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 536 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 537 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 538 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 539 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 540 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 541 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 542 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 543 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 544 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 545 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 546 } 547 548 /** 549 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 550 * 551 * @adev: amdgpu_device pointer 552 * @sw: enable SW clock gating 553 * 554 * Enable clock gating for VCN block 555 */ 556 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 557 { 558 uint32_t data = 0; 559 560 /* enable JPEG CGC */ 561 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 562 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 563 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 564 else 565 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 566 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 567 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 568 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 569 570 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 571 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 572 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 573 574 /* enable UVD CGC */ 575 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 576 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 577 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 578 else 579 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 580 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 581 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 582 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 583 584 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 585 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 586 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 587 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 588 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 589 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 590 | UVD_CGC_CTRL__SYS_MODE_MASK 591 | UVD_CGC_CTRL__UDEC_MODE_MASK 592 | UVD_CGC_CTRL__MPEG2_MODE_MASK 593 | UVD_CGC_CTRL__REGS_MODE_MASK 594 | UVD_CGC_CTRL__RBC_MODE_MASK 595 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 596 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 597 | UVD_CGC_CTRL__IDCT_MODE_MASK 598 | UVD_CGC_CTRL__MPRD_MODE_MASK 599 | UVD_CGC_CTRL__MPC_MODE_MASK 600 | UVD_CGC_CTRL__LBSI_MODE_MASK 601 | UVD_CGC_CTRL__LRBBM_MODE_MASK 602 | UVD_CGC_CTRL__WCB_MODE_MASK 603 | UVD_CGC_CTRL__VCPU_MODE_MASK 604 | UVD_CGC_CTRL__SCPU_MODE_MASK); 605 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 606 607 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 608 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 609 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 610 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 611 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 612 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 613 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 614 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 615 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 616 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 617 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 618 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 619 } 620 621 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 622 { 623 uint32_t reg_data = 0; 624 625 /* disable JPEG CGC */ 626 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 627 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 628 else 629 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 630 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 631 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 632 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 633 634 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 635 636 /* enable sw clock gating control */ 637 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 638 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 639 else 640 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 641 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 642 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 643 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 644 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 645 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 646 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 647 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 648 UVD_CGC_CTRL__SYS_MODE_MASK | 649 UVD_CGC_CTRL__UDEC_MODE_MASK | 650 UVD_CGC_CTRL__MPEG2_MODE_MASK | 651 UVD_CGC_CTRL__REGS_MODE_MASK | 652 UVD_CGC_CTRL__RBC_MODE_MASK | 653 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 654 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 655 UVD_CGC_CTRL__IDCT_MODE_MASK | 656 UVD_CGC_CTRL__MPRD_MODE_MASK | 657 UVD_CGC_CTRL__MPC_MODE_MASK | 658 UVD_CGC_CTRL__LBSI_MODE_MASK | 659 UVD_CGC_CTRL__LRBBM_MODE_MASK | 660 UVD_CGC_CTRL__WCB_MODE_MASK | 661 UVD_CGC_CTRL__VCPU_MODE_MASK | 662 UVD_CGC_CTRL__SCPU_MODE_MASK); 663 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 664 665 /* turn off clock gating */ 666 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 667 668 /* turn on SUVD clock gating */ 669 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 670 671 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 672 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 673 } 674 675 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 676 { 677 uint32_t data = 0; 678 int ret; 679 680 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 681 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 682 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 686 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 687 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 688 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 689 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 690 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 691 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 692 693 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 694 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 695 } else { 696 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 697 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 698 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 699 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 700 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 707 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 708 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 709 } 710 711 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 712 713 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 714 data &= ~0x103; 715 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 716 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 717 718 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 719 } 720 721 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 722 { 723 uint32_t data = 0; 724 int ret; 725 726 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 727 /* Before power off, this indicator has to be turned on */ 728 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 729 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 730 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 731 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 732 733 734 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 735 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 736 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 737 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 738 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 739 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 740 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 745 746 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 747 748 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 749 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 750 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 751 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 752 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 753 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 754 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 755 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 756 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 759 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 760 } 761 } 762 763 /** 764 * vcn_v1_0_start - start VCN block 765 * 766 * @adev: amdgpu_device pointer 767 * 768 * Setup and start the VCN block 769 */ 770 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 771 { 772 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 773 uint32_t rb_bufsz, tmp; 774 uint32_t lmi_swap_cntl; 775 int i, j, r; 776 777 /* disable byte swapping */ 778 lmi_swap_cntl = 0; 779 780 vcn_1_0_disable_static_power_gating(adev); 781 782 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 783 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 784 785 /* disable clock gating */ 786 vcn_v1_0_disable_clock_gating(adev); 787 788 /* disable interupt */ 789 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 790 ~UVD_MASTINT_EN__VCPU_EN_MASK); 791 792 /* initialize VCN memory controller */ 793 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 794 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 795 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 796 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 797 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 798 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 799 800 #ifdef __BIG_ENDIAN 801 /* swap (8 in 32) RB and IB */ 802 lmi_swap_cntl = 0xa; 803 #endif 804 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 805 806 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 807 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 808 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 809 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 810 811 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 812 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 813 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 814 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 815 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 816 817 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 818 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 819 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 820 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 821 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 822 823 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 824 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 825 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 826 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 827 828 vcn_v1_0_mc_resume_spg_mode(adev); 829 830 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10); 831 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 832 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); 833 834 /* enable VCPU clock */ 835 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 836 837 /* boot up the VCPU */ 838 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 839 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 840 841 /* enable UMC */ 842 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 843 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 844 845 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 846 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 847 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 848 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 849 850 for (i = 0; i < 10; ++i) { 851 uint32_t status; 852 853 for (j = 0; j < 100; ++j) { 854 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 855 if (status & UVD_STATUS__IDLE) 856 break; 857 mdelay(10); 858 } 859 r = 0; 860 if (status & UVD_STATUS__IDLE) 861 break; 862 863 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 864 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 865 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 866 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 867 mdelay(10); 868 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 869 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 870 mdelay(10); 871 r = -1; 872 } 873 874 if (r) { 875 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 876 return r; 877 } 878 /* enable master interrupt */ 879 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 880 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 881 882 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 883 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 884 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 885 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 886 887 /* clear the busy bit of UVD_STATUS */ 888 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 889 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 890 891 /* force RBC into idle state */ 892 rb_bufsz = order_base_2(ring->ring_size); 893 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 894 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 895 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 896 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 897 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 898 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 899 900 /* set the write pointer delay */ 901 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 902 903 /* set the wb address */ 904 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 905 (upper_32_bits(ring->gpu_addr) >> 2)); 906 907 /* programm the RB_BASE for ring buffer */ 908 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 909 lower_32_bits(ring->gpu_addr)); 910 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 911 upper_32_bits(ring->gpu_addr)); 912 913 /* Initialize the ring buffer's read and write pointers */ 914 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 915 916 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 917 918 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 919 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 920 lower_32_bits(ring->wptr)); 921 922 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 923 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 924 925 ring = &adev->vcn.ring_enc[0]; 926 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 927 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 928 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 929 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 930 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 931 932 ring = &adev->vcn.ring_enc[1]; 933 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 934 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 935 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 936 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 937 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 938 939 ring = &adev->vcn.ring_jpeg; 940 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 941 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 942 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 943 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); 944 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); 945 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); 946 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); 947 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 948 949 /* initialize wptr */ 950 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 951 952 /* copy patch commands to the jpeg ring */ 953 vcn_v1_0_jpeg_ring_set_patch_ring(ring, 954 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); 955 956 return 0; 957 } 958 959 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 960 { 961 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 962 uint32_t rb_bufsz, tmp; 963 uint32_t lmi_swap_cntl; 964 965 /* disable byte swapping */ 966 lmi_swap_cntl = 0; 967 968 vcn_1_0_enable_static_power_gating(adev); 969 970 /* enable dynamic power gating mode */ 971 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 972 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 973 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 974 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 975 976 /* enable clock gating */ 977 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 978 979 /* enable VCPU clock */ 980 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 981 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 982 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 983 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 984 985 /* disable interupt */ 986 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 987 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 988 989 /* initialize VCN memory controller */ 990 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 991 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 993 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 994 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 995 UVD_LMI_CTRL__REQ_MODE_MASK | 996 UVD_LMI_CTRL__CRC_RESET_MASK | 997 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 998 0x00100000L, 0xFFFFFFFF, 0); 999 1000 #ifdef __BIG_ENDIAN 1001 /* swap (8 in 32) RB and IB */ 1002 lmi_swap_cntl = 0xa; 1003 #endif 1004 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1005 1006 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, 1007 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1008 1009 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 1010 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1011 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1012 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1013 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1014 1015 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 1016 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1017 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1018 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1019 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1020 1021 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 1022 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1023 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1024 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1025 1026 vcn_v1_0_mc_resume_dpg_mode(adev); 1027 1028 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1029 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1030 1031 /* boot up the VCPU */ 1032 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1033 1034 /* enable UMC */ 1035 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1036 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1037 0xFFFFFFFF, 0); 1038 1039 /* enable master interrupt */ 1040 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1041 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1042 1043 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1044 /* setup mmUVD_LMI_CTRL */ 1045 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1046 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1047 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1048 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1049 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1050 UVD_LMI_CTRL__REQ_MODE_MASK | 1051 UVD_LMI_CTRL__CRC_RESET_MASK | 1052 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1053 0x00100000L, 0xFFFFFFFF, 1); 1054 1055 tmp = adev->gfx.config.gb_addr_config; 1056 /* setup VCN global tiling registers */ 1057 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1058 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1059 1060 /* enable System Interrupt for JRBC */ 1061 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, 1062 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1063 1064 /* force RBC into idle state */ 1065 rb_bufsz = order_base_2(ring->ring_size); 1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1069 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1070 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1072 1073 /* set the write pointer delay */ 1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1075 1076 /* set the wb address */ 1077 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1078 (upper_32_bits(ring->gpu_addr) >> 2)); 1079 1080 /* programm the RB_BASE for ring buffer */ 1081 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1082 lower_32_bits(ring->gpu_addr)); 1083 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1084 upper_32_bits(ring->gpu_addr)); 1085 1086 /* Initialize the ring buffer's read and write pointers */ 1087 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1088 1089 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1090 1091 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1092 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1093 lower_32_bits(ring->wptr)); 1094 1095 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1096 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1097 1098 /* initialize wptr */ 1099 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1100 1101 /* copy patch commands to the jpeg ring */ 1102 vcn_v1_0_jpeg_ring_set_patch_ring(ring, 1103 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); 1104 1105 return 0; 1106 } 1107 1108 static int vcn_v1_0_start(struct amdgpu_device *adev) 1109 { 1110 int r; 1111 1112 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1113 r = vcn_v1_0_start_dpg_mode(adev); 1114 else 1115 r = vcn_v1_0_start_spg_mode(adev); 1116 return r; 1117 } 1118 1119 /** 1120 * vcn_v1_0_stop - stop VCN block 1121 * 1122 * @adev: amdgpu_device pointer 1123 * 1124 * stop the VCN block 1125 */ 1126 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1127 { 1128 int ret_code, tmp; 1129 1130 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1131 1132 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1133 UVD_LMI_STATUS__READ_CLEAN_MASK | 1134 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1135 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1136 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1137 1138 /* put VCPU into reset */ 1139 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1140 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1141 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1142 1143 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1144 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1145 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1146 1147 /* disable VCPU clock */ 1148 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1149 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1150 1151 /* reset LMI UMC/LMI */ 1152 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1153 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1154 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1155 1156 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1157 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1158 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1159 1160 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1161 1162 vcn_v1_0_enable_clock_gating(adev); 1163 vcn_1_0_enable_static_power_gating(adev); 1164 return 0; 1165 } 1166 1167 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1168 { 1169 int ret_code = 0; 1170 1171 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1172 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1173 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1174 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1175 1176 if (!ret_code) { 1177 int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1178 /* wait for read ptr to be equal to write ptr */ 1179 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1180 1181 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1182 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1183 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1184 } 1185 1186 /* disable dynamic power gating mode */ 1187 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1188 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1189 1190 return 0; 1191 } 1192 1193 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1194 { 1195 int r; 1196 1197 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1198 r = vcn_v1_0_stop_dpg_mode(adev); 1199 else 1200 r = vcn_v1_0_stop_spg_mode(adev); 1201 1202 return r; 1203 } 1204 1205 static bool vcn_v1_0_is_idle(void *handle) 1206 { 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 1209 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1210 } 1211 1212 static int vcn_v1_0_wait_for_idle(void *handle) 1213 { 1214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1215 int ret = 0; 1216 1217 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1218 UVD_STATUS__IDLE, ret); 1219 1220 return ret; 1221 } 1222 1223 static int vcn_v1_0_set_clockgating_state(void *handle, 1224 enum amd_clockgating_state state) 1225 { 1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1227 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1228 1229 if (enable) { 1230 /* wait for STATUS to clear */ 1231 if (vcn_v1_0_is_idle(handle)) 1232 return -EBUSY; 1233 vcn_v1_0_enable_clock_gating(adev); 1234 } else { 1235 /* disable HW gating and enable Sw gating */ 1236 vcn_v1_0_disable_clock_gating(adev); 1237 } 1238 return 0; 1239 } 1240 1241 /** 1242 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1243 * 1244 * @ring: amdgpu_ring pointer 1245 * 1246 * Returns the current hardware read pointer 1247 */ 1248 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1249 { 1250 struct amdgpu_device *adev = ring->adev; 1251 1252 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1253 } 1254 1255 /** 1256 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1257 * 1258 * @ring: amdgpu_ring pointer 1259 * 1260 * Returns the current hardware write pointer 1261 */ 1262 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1263 { 1264 struct amdgpu_device *adev = ring->adev; 1265 1266 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1267 } 1268 1269 /** 1270 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1271 * 1272 * @ring: amdgpu_ring pointer 1273 * 1274 * Commits the write pointer to the hardware 1275 */ 1276 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1277 { 1278 struct amdgpu_device *adev = ring->adev; 1279 1280 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1281 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1282 lower_32_bits(ring->wptr) | 0x80000000); 1283 1284 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1285 } 1286 1287 /** 1288 * vcn_v1_0_dec_ring_insert_start - insert a start command 1289 * 1290 * @ring: amdgpu_ring pointer 1291 * 1292 * Write a start command to the ring. 1293 */ 1294 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1295 { 1296 struct amdgpu_device *adev = ring->adev; 1297 1298 amdgpu_ring_write(ring, 1299 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1300 amdgpu_ring_write(ring, 0); 1301 amdgpu_ring_write(ring, 1302 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1303 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1304 } 1305 1306 /** 1307 * vcn_v1_0_dec_ring_insert_end - insert a end command 1308 * 1309 * @ring: amdgpu_ring pointer 1310 * 1311 * Write a end command to the ring. 1312 */ 1313 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1314 { 1315 struct amdgpu_device *adev = ring->adev; 1316 1317 amdgpu_ring_write(ring, 1318 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1319 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1320 } 1321 1322 /** 1323 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1324 * 1325 * @ring: amdgpu_ring pointer 1326 * @fence: fence to emit 1327 * 1328 * Write a fence and a trap command to the ring. 1329 */ 1330 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1331 unsigned flags) 1332 { 1333 struct amdgpu_device *adev = ring->adev; 1334 1335 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1336 1337 amdgpu_ring_write(ring, 1338 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1339 amdgpu_ring_write(ring, seq); 1340 amdgpu_ring_write(ring, 1341 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1342 amdgpu_ring_write(ring, addr & 0xffffffff); 1343 amdgpu_ring_write(ring, 1344 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1345 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1346 amdgpu_ring_write(ring, 1347 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1348 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1349 1350 amdgpu_ring_write(ring, 1351 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1352 amdgpu_ring_write(ring, 0); 1353 amdgpu_ring_write(ring, 1354 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1355 amdgpu_ring_write(ring, 0); 1356 amdgpu_ring_write(ring, 1357 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1358 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1359 } 1360 1361 /** 1362 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1363 * 1364 * @ring: amdgpu_ring pointer 1365 * @ib: indirect buffer to execute 1366 * 1367 * Write ring commands to execute the indirect buffer 1368 */ 1369 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1370 struct amdgpu_ib *ib, 1371 unsigned vmid, bool ctx_switch) 1372 { 1373 struct amdgpu_device *adev = ring->adev; 1374 1375 amdgpu_ring_write(ring, 1376 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1377 amdgpu_ring_write(ring, vmid); 1378 1379 amdgpu_ring_write(ring, 1380 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1381 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1382 amdgpu_ring_write(ring, 1383 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1384 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1385 amdgpu_ring_write(ring, 1386 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1387 amdgpu_ring_write(ring, ib->length_dw); 1388 } 1389 1390 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1391 uint32_t reg, uint32_t val, 1392 uint32_t mask) 1393 { 1394 struct amdgpu_device *adev = ring->adev; 1395 1396 amdgpu_ring_write(ring, 1397 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1398 amdgpu_ring_write(ring, reg << 2); 1399 amdgpu_ring_write(ring, 1400 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1401 amdgpu_ring_write(ring, val); 1402 amdgpu_ring_write(ring, 1403 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1404 amdgpu_ring_write(ring, mask); 1405 amdgpu_ring_write(ring, 1406 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1407 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1408 } 1409 1410 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1411 unsigned vmid, uint64_t pd_addr) 1412 { 1413 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1414 uint32_t data0, data1, mask; 1415 1416 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1417 1418 /* wait for register write */ 1419 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1420 data1 = lower_32_bits(pd_addr); 1421 mask = 0xffffffff; 1422 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1423 } 1424 1425 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1426 uint32_t reg, uint32_t val) 1427 { 1428 struct amdgpu_device *adev = ring->adev; 1429 1430 amdgpu_ring_write(ring, 1431 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1432 amdgpu_ring_write(ring, reg << 2); 1433 amdgpu_ring_write(ring, 1434 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1435 amdgpu_ring_write(ring, val); 1436 amdgpu_ring_write(ring, 1437 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1438 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1439 } 1440 1441 /** 1442 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1443 * 1444 * @ring: amdgpu_ring pointer 1445 * 1446 * Returns the current hardware enc read pointer 1447 */ 1448 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1449 { 1450 struct amdgpu_device *adev = ring->adev; 1451 1452 if (ring == &adev->vcn.ring_enc[0]) 1453 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1454 else 1455 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1456 } 1457 1458 /** 1459 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1460 * 1461 * @ring: amdgpu_ring pointer 1462 * 1463 * Returns the current hardware enc write pointer 1464 */ 1465 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1466 { 1467 struct amdgpu_device *adev = ring->adev; 1468 1469 if (ring == &adev->vcn.ring_enc[0]) 1470 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1471 else 1472 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1473 } 1474 1475 /** 1476 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1477 * 1478 * @ring: amdgpu_ring pointer 1479 * 1480 * Commits the enc write pointer to the hardware 1481 */ 1482 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1483 { 1484 struct amdgpu_device *adev = ring->adev; 1485 1486 if (ring == &adev->vcn.ring_enc[0]) 1487 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1488 lower_32_bits(ring->wptr)); 1489 else 1490 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1491 lower_32_bits(ring->wptr)); 1492 } 1493 1494 /** 1495 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1496 * 1497 * @ring: amdgpu_ring pointer 1498 * @fence: fence to emit 1499 * 1500 * Write enc a fence and a trap command to the ring. 1501 */ 1502 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1503 u64 seq, unsigned flags) 1504 { 1505 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1506 1507 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1508 amdgpu_ring_write(ring, addr); 1509 amdgpu_ring_write(ring, upper_32_bits(addr)); 1510 amdgpu_ring_write(ring, seq); 1511 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1512 } 1513 1514 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1515 { 1516 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1517 } 1518 1519 /** 1520 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1521 * 1522 * @ring: amdgpu_ring pointer 1523 * @ib: indirect buffer to execute 1524 * 1525 * Write enc ring commands to execute the indirect buffer 1526 */ 1527 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1528 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) 1529 { 1530 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1531 amdgpu_ring_write(ring, vmid); 1532 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1533 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1534 amdgpu_ring_write(ring, ib->length_dw); 1535 } 1536 1537 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1538 uint32_t reg, uint32_t val, 1539 uint32_t mask) 1540 { 1541 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1542 amdgpu_ring_write(ring, reg << 2); 1543 amdgpu_ring_write(ring, mask); 1544 amdgpu_ring_write(ring, val); 1545 } 1546 1547 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1548 unsigned int vmid, uint64_t pd_addr) 1549 { 1550 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1551 1552 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1553 1554 /* wait for reg writes */ 1555 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1556 lower_32_bits(pd_addr), 0xffffffff); 1557 } 1558 1559 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1560 uint32_t reg, uint32_t val) 1561 { 1562 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1563 amdgpu_ring_write(ring, reg << 2); 1564 amdgpu_ring_write(ring, val); 1565 } 1566 1567 1568 /** 1569 * vcn_v1_0_jpeg_ring_get_rptr - get read pointer 1570 * 1571 * @ring: amdgpu_ring pointer 1572 * 1573 * Returns the current hardware read pointer 1574 */ 1575 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) 1576 { 1577 struct amdgpu_device *adev = ring->adev; 1578 1579 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); 1580 } 1581 1582 /** 1583 * vcn_v1_0_jpeg_ring_get_wptr - get write pointer 1584 * 1585 * @ring: amdgpu_ring pointer 1586 * 1587 * Returns the current hardware write pointer 1588 */ 1589 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) 1590 { 1591 struct amdgpu_device *adev = ring->adev; 1592 1593 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1594 } 1595 1596 /** 1597 * vcn_v1_0_jpeg_ring_set_wptr - set write pointer 1598 * 1599 * @ring: amdgpu_ring pointer 1600 * 1601 * Commits the write pointer to the hardware 1602 */ 1603 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) 1604 { 1605 struct amdgpu_device *adev = ring->adev; 1606 1607 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 1608 } 1609 1610 /** 1611 * vcn_v1_0_jpeg_ring_insert_start - insert a start command 1612 * 1613 * @ring: amdgpu_ring pointer 1614 * 1615 * Write a start command to the ring. 1616 */ 1617 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) 1618 { 1619 struct amdgpu_device *adev = ring->adev; 1620 1621 amdgpu_ring_write(ring, 1622 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1623 amdgpu_ring_write(ring, 0x68e04); 1624 1625 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1626 amdgpu_ring_write(ring, 0x80010000); 1627 } 1628 1629 /** 1630 * vcn_v1_0_jpeg_ring_insert_end - insert a end command 1631 * 1632 * @ring: amdgpu_ring pointer 1633 * 1634 * Write a end command to the ring. 1635 */ 1636 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) 1637 { 1638 struct amdgpu_device *adev = ring->adev; 1639 1640 amdgpu_ring_write(ring, 1641 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1642 amdgpu_ring_write(ring, 0x68e04); 1643 1644 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1645 amdgpu_ring_write(ring, 0x00010000); 1646 } 1647 1648 /** 1649 * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command 1650 * 1651 * @ring: amdgpu_ring pointer 1652 * @fence: fence to emit 1653 * 1654 * Write a fence and a trap command to the ring. 1655 */ 1656 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1657 unsigned flags) 1658 { 1659 struct amdgpu_device *adev = ring->adev; 1660 1661 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1662 1663 amdgpu_ring_write(ring, 1664 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0)); 1665 amdgpu_ring_write(ring, seq); 1666 1667 amdgpu_ring_write(ring, 1668 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0)); 1669 amdgpu_ring_write(ring, seq); 1670 1671 amdgpu_ring_write(ring, 1672 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1673 amdgpu_ring_write(ring, lower_32_bits(addr)); 1674 1675 amdgpu_ring_write(ring, 1676 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1677 amdgpu_ring_write(ring, upper_32_bits(addr)); 1678 1679 amdgpu_ring_write(ring, 1680 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); 1681 amdgpu_ring_write(ring, 0x8); 1682 1683 amdgpu_ring_write(ring, 1684 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 1685 amdgpu_ring_write(ring, 0); 1686 1687 amdgpu_ring_write(ring, 1688 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1689 amdgpu_ring_write(ring, 0x01400200); 1690 1691 amdgpu_ring_write(ring, 1692 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1693 amdgpu_ring_write(ring, seq); 1694 1695 amdgpu_ring_write(ring, 1696 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1697 amdgpu_ring_write(ring, lower_32_bits(addr)); 1698 1699 amdgpu_ring_write(ring, 1700 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1701 amdgpu_ring_write(ring, upper_32_bits(addr)); 1702 1703 amdgpu_ring_write(ring, 1704 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2)); 1705 amdgpu_ring_write(ring, 0xffffffff); 1706 1707 amdgpu_ring_write(ring, 1708 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1709 amdgpu_ring_write(ring, 0x3fbc); 1710 1711 amdgpu_ring_write(ring, 1712 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1713 amdgpu_ring_write(ring, 0x1); 1714 1715 /* emit trap */ 1716 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 1717 amdgpu_ring_write(ring, 0); 1718 } 1719 1720 /** 1721 * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer 1722 * 1723 * @ring: amdgpu_ring pointer 1724 * @ib: indirect buffer to execute 1725 * 1726 * Write ring commands to execute the indirect buffer. 1727 */ 1728 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, 1729 struct amdgpu_ib *ib, 1730 unsigned vmid, bool ctx_switch) 1731 { 1732 struct amdgpu_device *adev = ring->adev; 1733 1734 amdgpu_ring_write(ring, 1735 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); 1736 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1737 1738 amdgpu_ring_write(ring, 1739 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); 1740 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1741 1742 amdgpu_ring_write(ring, 1743 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1744 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1745 1746 amdgpu_ring_write(ring, 1747 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1748 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1749 1750 amdgpu_ring_write(ring, 1751 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); 1752 amdgpu_ring_write(ring, ib->length_dw); 1753 1754 amdgpu_ring_write(ring, 1755 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1756 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 1757 1758 amdgpu_ring_write(ring, 1759 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1760 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 1761 1762 amdgpu_ring_write(ring, 1763 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 1764 amdgpu_ring_write(ring, 0); 1765 1766 amdgpu_ring_write(ring, 1767 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1768 amdgpu_ring_write(ring, 0x01400200); 1769 1770 amdgpu_ring_write(ring, 1771 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1772 amdgpu_ring_write(ring, 0x2); 1773 1774 amdgpu_ring_write(ring, 1775 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 1776 amdgpu_ring_write(ring, 0x2); 1777 } 1778 1779 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, 1780 uint32_t reg, uint32_t val, 1781 uint32_t mask) 1782 { 1783 struct amdgpu_device *adev = ring->adev; 1784 uint32_t reg_offset = (reg << 2); 1785 1786 amdgpu_ring_write(ring, 1787 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1788 amdgpu_ring_write(ring, 0x01400200); 1789 1790 amdgpu_ring_write(ring, 1791 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1792 amdgpu_ring_write(ring, val); 1793 1794 amdgpu_ring_write(ring, 1795 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1796 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1797 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1798 amdgpu_ring_write(ring, 0); 1799 amdgpu_ring_write(ring, 1800 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 1801 } else { 1802 amdgpu_ring_write(ring, reg_offset); 1803 amdgpu_ring_write(ring, 1804 PACKETJ(0, 0, 0, PACKETJ_TYPE3)); 1805 } 1806 amdgpu_ring_write(ring, mask); 1807 } 1808 1809 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, 1810 unsigned vmid, uint64_t pd_addr) 1811 { 1812 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1813 uint32_t data0, data1, mask; 1814 1815 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1816 1817 /* wait for register write */ 1818 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1819 data1 = lower_32_bits(pd_addr); 1820 mask = 0xffffffff; 1821 vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); 1822 } 1823 1824 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, 1825 uint32_t reg, uint32_t val) 1826 { 1827 struct amdgpu_device *adev = ring->adev; 1828 uint32_t reg_offset = (reg << 2); 1829 1830 amdgpu_ring_write(ring, 1831 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1832 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1833 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1834 amdgpu_ring_write(ring, 0); 1835 amdgpu_ring_write(ring, 1836 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 1837 } else { 1838 amdgpu_ring_write(ring, reg_offset); 1839 amdgpu_ring_write(ring, 1840 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1841 } 1842 amdgpu_ring_write(ring, val); 1843 } 1844 1845 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) 1846 { 1847 int i; 1848 1849 WARN_ON(ring->wptr % 2 || count % 2); 1850 1851 for (i = 0; i < count / 2; i++) { 1852 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 1853 amdgpu_ring_write(ring, 0); 1854 } 1855 } 1856 1857 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) 1858 { 1859 struct amdgpu_device *adev = ring->adev; 1860 ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 1861 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1862 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1863 ring->ring[(*ptr)++] = 0; 1864 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); 1865 } else { 1866 ring->ring[(*ptr)++] = reg_offset; 1867 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); 1868 } 1869 ring->ring[(*ptr)++] = val; 1870 } 1871 1872 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) 1873 { 1874 struct amdgpu_device *adev = ring->adev; 1875 1876 uint32_t reg, reg_offset, val, mask, i; 1877 1878 // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1879 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); 1880 reg_offset = (reg << 2); 1881 val = lower_32_bits(ring->gpu_addr); 1882 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1883 1884 // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1885 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); 1886 reg_offset = (reg << 2); 1887 val = upper_32_bits(ring->gpu_addr); 1888 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1889 1890 // 3rd to 5th: issue MEM_READ commands 1891 for (i = 0; i <= 2; i++) { 1892 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); 1893 ring->ring[ptr++] = 0; 1894 } 1895 1896 // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability 1897 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 1898 reg_offset = (reg << 2); 1899 val = 0x13; 1900 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1901 1902 // 7th: program mmUVD_JRBC_RB_REF_DATA 1903 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA); 1904 reg_offset = (reg << 2); 1905 val = 0x1; 1906 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1907 1908 // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL 1909 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 1910 reg_offset = (reg << 2); 1911 val = 0x1; 1912 mask = 0x1; 1913 1914 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0); 1915 ring->ring[ptr++] = 0x01400200; 1916 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0); 1917 ring->ring[ptr++] = val; 1918 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 1919 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1920 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1921 ring->ring[ptr++] = 0; 1922 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); 1923 } else { 1924 ring->ring[ptr++] = reg_offset; 1925 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); 1926 } 1927 ring->ring[ptr++] = mask; 1928 1929 //9th to 21st: insert no-op 1930 for (i = 0; i <= 12; i++) { 1931 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 1932 ring->ring[ptr++] = 0; 1933 } 1934 1935 //22nd: reset mmUVD_JRBC_RB_RPTR 1936 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR); 1937 reg_offset = (reg << 2); 1938 val = 0; 1939 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1940 1941 //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch 1942 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 1943 reg_offset = (reg << 2); 1944 val = 0x12; 1945 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1946 } 1947 1948 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1949 struct amdgpu_irq_src *source, 1950 unsigned type, 1951 enum amdgpu_interrupt_state state) 1952 { 1953 return 0; 1954 } 1955 1956 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1957 struct amdgpu_irq_src *source, 1958 struct amdgpu_iv_entry *entry) 1959 { 1960 DRM_DEBUG("IH: VCN TRAP\n"); 1961 1962 switch (entry->src_id) { 1963 case 124: 1964 amdgpu_fence_process(&adev->vcn.ring_dec); 1965 break; 1966 case 119: 1967 amdgpu_fence_process(&adev->vcn.ring_enc[0]); 1968 break; 1969 case 120: 1970 amdgpu_fence_process(&adev->vcn.ring_enc[1]); 1971 break; 1972 case 126: 1973 amdgpu_fence_process(&adev->vcn.ring_jpeg); 1974 break; 1975 default: 1976 DRM_ERROR("Unhandled interrupt: %d %d\n", 1977 entry->src_id, entry->src_data[0]); 1978 break; 1979 } 1980 1981 return 0; 1982 } 1983 1984 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1985 { 1986 struct amdgpu_device *adev = ring->adev; 1987 int i; 1988 1989 WARN_ON(ring->wptr % 2 || count % 2); 1990 1991 for (i = 0; i < count / 2; i++) { 1992 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1993 amdgpu_ring_write(ring, 0); 1994 } 1995 } 1996 1997 static int vcn_v1_0_set_powergating_state(void *handle, 1998 enum amd_powergating_state state) 1999 { 2000 /* This doesn't actually powergate the VCN block. 2001 * That's done in the dpm code via the SMC. This 2002 * just re-inits the block as necessary. The actual 2003 * gating still happens in the dpm code. We should 2004 * revisit this when there is a cleaner line between 2005 * the smc and the hw blocks 2006 */ 2007 int ret; 2008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2009 2010 if(state == adev->vcn.cur_state) 2011 return 0; 2012 2013 if (state == AMD_PG_STATE_GATE) 2014 ret = vcn_v1_0_stop(adev); 2015 else 2016 ret = vcn_v1_0_start(adev); 2017 2018 if(!ret) 2019 adev->vcn.cur_state = state; 2020 return ret; 2021 } 2022 2023 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 2024 .name = "vcn_v1_0", 2025 .early_init = vcn_v1_0_early_init, 2026 .late_init = NULL, 2027 .sw_init = vcn_v1_0_sw_init, 2028 .sw_fini = vcn_v1_0_sw_fini, 2029 .hw_init = vcn_v1_0_hw_init, 2030 .hw_fini = vcn_v1_0_hw_fini, 2031 .suspend = vcn_v1_0_suspend, 2032 .resume = vcn_v1_0_resume, 2033 .is_idle = vcn_v1_0_is_idle, 2034 .wait_for_idle = vcn_v1_0_wait_for_idle, 2035 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 2036 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 2037 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 2038 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 2039 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 2040 .set_powergating_state = vcn_v1_0_set_powergating_state, 2041 }; 2042 2043 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 2044 .type = AMDGPU_RING_TYPE_VCN_DEC, 2045 .align_mask = 0xf, 2046 .support_64bit_ptrs = false, 2047 .vmhub = AMDGPU_MMHUB, 2048 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 2049 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 2050 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 2051 .emit_frame_size = 2052 6 + 6 + /* hdp invalidate / flush */ 2053 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2054 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2055 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 2056 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 2057 6, 2058 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 2059 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 2060 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 2061 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 2062 .test_ring = amdgpu_vcn_dec_ring_test_ring, 2063 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2064 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 2065 .insert_start = vcn_v1_0_dec_ring_insert_start, 2066 .insert_end = vcn_v1_0_dec_ring_insert_end, 2067 .pad_ib = amdgpu_ring_generic_pad_ib, 2068 .begin_use = amdgpu_vcn_ring_begin_use, 2069 .end_use = amdgpu_vcn_ring_end_use, 2070 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 2071 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 2072 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2073 }; 2074 2075 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 2076 .type = AMDGPU_RING_TYPE_VCN_ENC, 2077 .align_mask = 0x3f, 2078 .nop = VCN_ENC_CMD_NO_OP, 2079 .support_64bit_ptrs = false, 2080 .vmhub = AMDGPU_MMHUB, 2081 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 2082 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 2083 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 2084 .emit_frame_size = 2085 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2086 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2087 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 2088 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 2089 1, /* vcn_v1_0_enc_ring_insert_end */ 2090 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 2091 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 2092 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 2093 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 2094 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2095 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2096 .insert_nop = amdgpu_ring_insert_nop, 2097 .insert_end = vcn_v1_0_enc_ring_insert_end, 2098 .pad_ib = amdgpu_ring_generic_pad_ib, 2099 .begin_use = amdgpu_vcn_ring_begin_use, 2100 .end_use = amdgpu_vcn_ring_end_use, 2101 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 2102 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 2103 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2104 }; 2105 2106 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = { 2107 .type = AMDGPU_RING_TYPE_VCN_JPEG, 2108 .align_mask = 0xf, 2109 .nop = PACKET0(0x81ff, 0), 2110 .support_64bit_ptrs = false, 2111 .vmhub = AMDGPU_MMHUB, 2112 .extra_dw = 64, 2113 .get_rptr = vcn_v1_0_jpeg_ring_get_rptr, 2114 .get_wptr = vcn_v1_0_jpeg_ring_get_wptr, 2115 .set_wptr = vcn_v1_0_jpeg_ring_set_wptr, 2116 .emit_frame_size = 2117 6 + 6 + /* hdp invalidate / flush */ 2118 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2119 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2120 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */ 2121 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */ 2122 6, 2123 .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */ 2124 .emit_ib = vcn_v1_0_jpeg_ring_emit_ib, 2125 .emit_fence = vcn_v1_0_jpeg_ring_emit_fence, 2126 .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush, 2127 .test_ring = amdgpu_vcn_jpeg_ring_test_ring, 2128 .test_ib = amdgpu_vcn_jpeg_ring_test_ib, 2129 .insert_nop = vcn_v1_0_jpeg_ring_nop, 2130 .insert_start = vcn_v1_0_jpeg_ring_insert_start, 2131 .insert_end = vcn_v1_0_jpeg_ring_insert_end, 2132 .pad_ib = amdgpu_ring_generic_pad_ib, 2133 .begin_use = amdgpu_vcn_ring_begin_use, 2134 .end_use = amdgpu_vcn_ring_end_use, 2135 .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg, 2136 .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait, 2137 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2138 }; 2139 2140 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2141 { 2142 adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 2143 DRM_INFO("VCN decode is enabled in VM mode\n"); 2144 } 2145 2146 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2147 { 2148 int i; 2149 2150 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2151 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 2152 2153 DRM_INFO("VCN encode is enabled in VM mode\n"); 2154 } 2155 2156 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) 2157 { 2158 adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs; 2159 DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); 2160 } 2161 2162 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 2163 .set = vcn_v1_0_set_interrupt_state, 2164 .process = vcn_v1_0_process_interrupt, 2165 }; 2166 2167 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 2168 { 2169 adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2; 2170 adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; 2171 } 2172 2173 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 2174 { 2175 .type = AMD_IP_BLOCK_TYPE_VCN, 2176 .major = 1, 2177 .minor = 0, 2178 .rev = 0, 2179 .funcs = &vcn_v1_0_ip_funcs, 2180 }; 2181