1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "amdgpu_pm.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_common.h" 32 33 #include "vcn/vcn_1_0_offset.h" 34 #include "vcn/vcn_1_0_sh_mask.h" 35 #include "hdp/hdp_4_0_offset.h" 36 #include "mmhub/mmhub_9_1_offset.h" 37 #include "mmhub/mmhub_9_1_sh_mask.h" 38 39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 40 #include "jpeg_v1_0.h" 41 42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 44 #define mmUVD_REG_XX_MASK_1_0 0x05ac 45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 46 47 static int vcn_v1_0_stop(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 53 int inst_idx, struct dpg_pause_state *new_state); 54 55 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 56 57 /** 58 * vcn_v1_0_early_init - set function pointers 59 * 60 * @handle: amdgpu_device pointer 61 * 62 * Set ring and irq function pointers 63 */ 64 static int vcn_v1_0_early_init(void *handle) 65 { 66 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 67 68 adev->vcn.num_vcn_inst = 1; 69 adev->vcn.num_enc_rings = 2; 70 71 vcn_v1_0_set_dec_ring_funcs(adev); 72 vcn_v1_0_set_enc_ring_funcs(adev); 73 vcn_v1_0_set_irq_funcs(adev); 74 75 jpeg_v1_0_early_init(handle); 76 77 return 0; 78 } 79 80 /** 81 * vcn_v1_0_sw_init - sw init for VCN block 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Load firmware and sw initialization 86 */ 87 static int vcn_v1_0_sw_init(void *handle) 88 { 89 struct amdgpu_ring *ring; 90 int i, r; 91 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 92 93 /* VCN DEC TRAP */ 94 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 95 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 96 if (r) 97 return r; 98 99 /* VCN ENC TRAP */ 100 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 102 &adev->vcn.inst->irq); 103 if (r) 104 return r; 105 } 106 107 r = amdgpu_vcn_sw_init(adev); 108 if (r) 109 return r; 110 111 /* Override the work func */ 112 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 113 114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 115 const struct common_firmware_header *hdr; 116 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 117 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 118 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 119 adev->firmware.fw_size += 120 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 121 DRM_INFO("PSP loading VCN firmware\n"); 122 } 123 124 r = amdgpu_vcn_resume(adev); 125 if (r) 126 return r; 127 128 ring = &adev->vcn.inst->ring_dec; 129 sprintf(ring->name, "vcn_dec"); 130 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 131 AMDGPU_RING_PRIO_DEFAULT); 132 if (r) 133 return r; 134 135 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 136 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 137 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 138 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 139 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 140 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 141 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 142 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 143 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 144 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 145 146 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 147 ring = &adev->vcn.inst->ring_enc[i]; 148 sprintf(ring->name, "vcn_enc%d", i); 149 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 150 AMDGPU_RING_PRIO_DEFAULT); 151 if (r) 152 return r; 153 } 154 155 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 156 157 r = jpeg_v1_0_sw_init(handle); 158 159 return r; 160 } 161 162 /** 163 * vcn_v1_0_sw_fini - sw fini for VCN block 164 * 165 * @handle: amdgpu_device pointer 166 * 167 * VCN suspend and free up sw allocation 168 */ 169 static int vcn_v1_0_sw_fini(void *handle) 170 { 171 int r; 172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 173 174 r = amdgpu_vcn_suspend(adev); 175 if (r) 176 return r; 177 178 jpeg_v1_0_sw_fini(handle); 179 180 r = amdgpu_vcn_sw_fini(adev); 181 182 return r; 183 } 184 185 /** 186 * vcn_v1_0_hw_init - start and test VCN block 187 * 188 * @handle: amdgpu_device pointer 189 * 190 * Initialize the hardware, boot up the VCPU and do some testing 191 */ 192 static int vcn_v1_0_hw_init(void *handle) 193 { 194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 195 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 196 int i, r; 197 198 r = amdgpu_ring_test_helper(ring); 199 if (r) 200 goto done; 201 202 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 203 ring = &adev->vcn.inst->ring_enc[i]; 204 r = amdgpu_ring_test_helper(ring); 205 if (r) 206 goto done; 207 } 208 209 ring = &adev->jpeg.inst->ring_dec; 210 r = amdgpu_ring_test_helper(ring); 211 if (r) 212 goto done; 213 214 done: 215 if (!r) 216 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 217 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 218 219 return r; 220 } 221 222 /** 223 * vcn_v1_0_hw_fini - stop the hardware block 224 * 225 * @handle: amdgpu_device pointer 226 * 227 * Stop the VCN block, mark ring as not ready any more 228 */ 229 static int vcn_v1_0_hw_fini(void *handle) 230 { 231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 232 233 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 234 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 235 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 236 237 return 0; 238 } 239 240 /** 241 * vcn_v1_0_suspend - suspend VCN block 242 * 243 * @handle: amdgpu_device pointer 244 * 245 * HW fini and suspend VCN block 246 */ 247 static int vcn_v1_0_suspend(void *handle) 248 { 249 int r; 250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 251 252 r = vcn_v1_0_hw_fini(adev); 253 if (r) 254 return r; 255 256 r = amdgpu_vcn_suspend(adev); 257 258 return r; 259 } 260 261 /** 262 * vcn_v1_0_resume - resume VCN block 263 * 264 * @handle: amdgpu_device pointer 265 * 266 * Resume firmware and hw init VCN block 267 */ 268 static int vcn_v1_0_resume(void *handle) 269 { 270 int r; 271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 272 273 r = amdgpu_vcn_resume(adev); 274 if (r) 275 return r; 276 277 r = vcn_v1_0_hw_init(adev); 278 279 return r; 280 } 281 282 /** 283 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 284 * 285 * @adev: amdgpu_device pointer 286 * 287 * Let the VCN memory controller know it's offsets 288 */ 289 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 290 { 291 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 292 uint32_t offset; 293 294 /* cache window 0: fw */ 295 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 296 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 297 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 298 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 299 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 300 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 301 offset = 0; 302 } else { 303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 304 lower_32_bits(adev->vcn.inst->gpu_addr)); 305 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 306 upper_32_bits(adev->vcn.inst->gpu_addr)); 307 offset = size; 308 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 309 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 310 } 311 312 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 313 314 /* cache window 1: stack */ 315 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 316 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 317 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 318 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 319 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 321 322 /* cache window 2: context */ 323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 324 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 326 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 328 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 329 330 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 331 adev->gfx.config.gb_addr_config); 332 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 333 adev->gfx.config.gb_addr_config); 334 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 335 adev->gfx.config.gb_addr_config); 336 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 337 adev->gfx.config.gb_addr_config); 338 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 343 adev->gfx.config.gb_addr_config); 344 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 345 adev->gfx.config.gb_addr_config); 346 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 347 adev->gfx.config.gb_addr_config); 348 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 349 adev->gfx.config.gb_addr_config); 350 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 351 adev->gfx.config.gb_addr_config); 352 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 353 adev->gfx.config.gb_addr_config); 354 } 355 356 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 357 { 358 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 359 uint32_t offset; 360 361 /* cache window 0: fw */ 362 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 363 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 364 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 365 0xFFFFFFFF, 0); 366 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 367 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 368 0xFFFFFFFF, 0); 369 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 370 0xFFFFFFFF, 0); 371 offset = 0; 372 } else { 373 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 374 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 375 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 376 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 377 offset = size; 378 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 379 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 380 } 381 382 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 383 384 /* cache window 1: stack */ 385 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 386 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 387 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 388 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 389 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 390 0xFFFFFFFF, 0); 391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 392 0xFFFFFFFF, 0); 393 394 /* cache window 2: context */ 395 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 396 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 397 0xFFFFFFFF, 0); 398 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 399 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 400 0xFFFFFFFF, 0); 401 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 402 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 403 0xFFFFFFFF, 0); 404 405 /* VCN global tiling registers */ 406 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 407 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 408 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 409 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 410 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 411 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 412 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 413 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 414 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 416 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 417 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 418 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 419 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 421 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 422 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 423 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 424 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 425 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 426 } 427 428 /** 429 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 430 * 431 * @adev: amdgpu_device pointer 432 * @sw: enable SW clock gating 433 * 434 * Disable clock gating for VCN block 435 */ 436 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 437 { 438 uint32_t data; 439 440 /* JPEG disable CGC */ 441 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 442 443 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 444 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 445 else 446 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 447 448 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 449 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 450 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 451 452 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 453 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 454 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 455 456 /* UVD disable CGC */ 457 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 458 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 459 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 460 else 461 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 462 463 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 464 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 465 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 466 467 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 468 data &= ~(UVD_CGC_GATE__SYS_MASK 469 | UVD_CGC_GATE__UDEC_MASK 470 | UVD_CGC_GATE__MPEG2_MASK 471 | UVD_CGC_GATE__REGS_MASK 472 | UVD_CGC_GATE__RBC_MASK 473 | UVD_CGC_GATE__LMI_MC_MASK 474 | UVD_CGC_GATE__LMI_UMC_MASK 475 | UVD_CGC_GATE__IDCT_MASK 476 | UVD_CGC_GATE__MPRD_MASK 477 | UVD_CGC_GATE__MPC_MASK 478 | UVD_CGC_GATE__LBSI_MASK 479 | UVD_CGC_GATE__LRBBM_MASK 480 | UVD_CGC_GATE__UDEC_RE_MASK 481 | UVD_CGC_GATE__UDEC_CM_MASK 482 | UVD_CGC_GATE__UDEC_IT_MASK 483 | UVD_CGC_GATE__UDEC_DB_MASK 484 | UVD_CGC_GATE__UDEC_MP_MASK 485 | UVD_CGC_GATE__WCB_MASK 486 | UVD_CGC_GATE__VCPU_MASK 487 | UVD_CGC_GATE__SCPU_MASK); 488 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 489 490 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 491 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 492 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 493 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 494 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 495 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 496 | UVD_CGC_CTRL__SYS_MODE_MASK 497 | UVD_CGC_CTRL__UDEC_MODE_MASK 498 | UVD_CGC_CTRL__MPEG2_MODE_MASK 499 | UVD_CGC_CTRL__REGS_MODE_MASK 500 | UVD_CGC_CTRL__RBC_MODE_MASK 501 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 502 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 503 | UVD_CGC_CTRL__IDCT_MODE_MASK 504 | UVD_CGC_CTRL__MPRD_MODE_MASK 505 | UVD_CGC_CTRL__MPC_MODE_MASK 506 | UVD_CGC_CTRL__LBSI_MODE_MASK 507 | UVD_CGC_CTRL__LRBBM_MODE_MASK 508 | UVD_CGC_CTRL__WCB_MODE_MASK 509 | UVD_CGC_CTRL__VCPU_MODE_MASK 510 | UVD_CGC_CTRL__SCPU_MODE_MASK); 511 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 512 513 /* turn on */ 514 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 515 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 516 | UVD_SUVD_CGC_GATE__SIT_MASK 517 | UVD_SUVD_CGC_GATE__SMP_MASK 518 | UVD_SUVD_CGC_GATE__SCM_MASK 519 | UVD_SUVD_CGC_GATE__SDB_MASK 520 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 521 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 522 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 523 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 524 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 525 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 526 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 527 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 528 | UVD_SUVD_CGC_GATE__SCLR_MASK 529 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 530 | UVD_SUVD_CGC_GATE__ENT_MASK 531 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 532 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 533 | UVD_SUVD_CGC_GATE__SITE_MASK 534 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 535 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 536 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 537 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 538 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 539 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 540 541 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 542 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 543 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 544 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 545 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 546 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 547 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 548 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 549 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 550 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 551 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 552 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 553 } 554 555 /** 556 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 557 * 558 * @adev: amdgpu_device pointer 559 * @sw: enable SW clock gating 560 * 561 * Enable clock gating for VCN block 562 */ 563 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 564 { 565 uint32_t data = 0; 566 567 /* enable JPEG CGC */ 568 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 569 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 570 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 571 else 572 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 573 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 574 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 575 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 576 577 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 578 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 579 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 580 581 /* enable UVD CGC */ 582 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 583 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 584 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 585 else 586 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 587 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 588 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 589 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 590 591 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 592 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 593 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 594 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 595 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 596 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 597 | UVD_CGC_CTRL__SYS_MODE_MASK 598 | UVD_CGC_CTRL__UDEC_MODE_MASK 599 | UVD_CGC_CTRL__MPEG2_MODE_MASK 600 | UVD_CGC_CTRL__REGS_MODE_MASK 601 | UVD_CGC_CTRL__RBC_MODE_MASK 602 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 603 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 604 | UVD_CGC_CTRL__IDCT_MODE_MASK 605 | UVD_CGC_CTRL__MPRD_MODE_MASK 606 | UVD_CGC_CTRL__MPC_MODE_MASK 607 | UVD_CGC_CTRL__LBSI_MODE_MASK 608 | UVD_CGC_CTRL__LRBBM_MODE_MASK 609 | UVD_CGC_CTRL__WCB_MODE_MASK 610 | UVD_CGC_CTRL__VCPU_MODE_MASK 611 | UVD_CGC_CTRL__SCPU_MODE_MASK); 612 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 613 614 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 615 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 616 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 617 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 618 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 619 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 620 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 621 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 622 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 623 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 624 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 625 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 626 } 627 628 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 629 { 630 uint32_t reg_data = 0; 631 632 /* disable JPEG CGC */ 633 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 634 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 635 else 636 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 637 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 638 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 639 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 640 641 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 642 643 /* enable sw clock gating control */ 644 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 645 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 646 else 647 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 648 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 649 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 650 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 651 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 652 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 653 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 654 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 655 UVD_CGC_CTRL__SYS_MODE_MASK | 656 UVD_CGC_CTRL__UDEC_MODE_MASK | 657 UVD_CGC_CTRL__MPEG2_MODE_MASK | 658 UVD_CGC_CTRL__REGS_MODE_MASK | 659 UVD_CGC_CTRL__RBC_MODE_MASK | 660 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 661 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 662 UVD_CGC_CTRL__IDCT_MODE_MASK | 663 UVD_CGC_CTRL__MPRD_MODE_MASK | 664 UVD_CGC_CTRL__MPC_MODE_MASK | 665 UVD_CGC_CTRL__LBSI_MODE_MASK | 666 UVD_CGC_CTRL__LRBBM_MODE_MASK | 667 UVD_CGC_CTRL__WCB_MODE_MASK | 668 UVD_CGC_CTRL__VCPU_MODE_MASK | 669 UVD_CGC_CTRL__SCPU_MODE_MASK); 670 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 671 672 /* turn off clock gating */ 673 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 674 675 /* turn on SUVD clock gating */ 676 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 677 678 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 679 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 680 } 681 682 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 683 { 684 uint32_t data = 0; 685 int ret; 686 687 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 688 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 689 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 690 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 691 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 692 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 693 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 694 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 695 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 696 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 697 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 698 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 699 700 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 701 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 702 } else { 703 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 709 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 710 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 711 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 712 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 713 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 714 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 715 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 716 } 717 718 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 719 720 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 721 data &= ~0x103; 722 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 723 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 724 725 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 726 } 727 728 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 729 { 730 uint32_t data = 0; 731 int ret; 732 733 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 734 /* Before power off, this indicator has to be turned on */ 735 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 736 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 737 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 738 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 739 740 741 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 746 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 747 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 748 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 749 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 750 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 751 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 752 753 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 754 755 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 756 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 760 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 761 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 762 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 763 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 764 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 765 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 766 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 767 } 768 } 769 770 /** 771 * vcn_v1_0_start - start VCN block 772 * 773 * @adev: amdgpu_device pointer 774 * 775 * Setup and start the VCN block 776 */ 777 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 778 { 779 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 780 uint32_t rb_bufsz, tmp; 781 uint32_t lmi_swap_cntl; 782 int i, j, r; 783 784 /* disable byte swapping */ 785 lmi_swap_cntl = 0; 786 787 vcn_1_0_disable_static_power_gating(adev); 788 789 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 790 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 791 792 /* disable clock gating */ 793 vcn_v1_0_disable_clock_gating(adev); 794 795 /* disable interupt */ 796 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 797 ~UVD_MASTINT_EN__VCPU_EN_MASK); 798 799 /* initialize VCN memory controller */ 800 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 801 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 802 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 803 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 804 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 805 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 806 807 #ifdef __BIG_ENDIAN 808 /* swap (8 in 32) RB and IB */ 809 lmi_swap_cntl = 0xa; 810 #endif 811 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 812 813 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 814 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 815 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 816 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 817 818 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 819 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 820 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 821 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 822 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 823 824 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 825 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 826 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 827 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 828 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 829 830 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 831 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 832 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 833 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 834 835 vcn_v1_0_mc_resume_spg_mode(adev); 836 837 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 838 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 839 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 840 841 /* enable VCPU clock */ 842 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 843 844 /* boot up the VCPU */ 845 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 846 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 847 848 /* enable UMC */ 849 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 850 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 851 852 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 853 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 854 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 855 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 856 857 for (i = 0; i < 10; ++i) { 858 uint32_t status; 859 860 for (j = 0; j < 100; ++j) { 861 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 862 if (status & UVD_STATUS__IDLE) 863 break; 864 mdelay(10); 865 } 866 r = 0; 867 if (status & UVD_STATUS__IDLE) 868 break; 869 870 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 871 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 872 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 873 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 874 mdelay(10); 875 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 876 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 877 mdelay(10); 878 r = -1; 879 } 880 881 if (r) { 882 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 883 return r; 884 } 885 /* enable master interrupt */ 886 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 887 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 888 889 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 890 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 891 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 892 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 893 894 /* clear the busy bit of UVD_STATUS */ 895 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 896 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 897 898 /* force RBC into idle state */ 899 rb_bufsz = order_base_2(ring->ring_size); 900 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 901 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 902 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 903 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 904 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 905 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 906 907 /* set the write pointer delay */ 908 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 909 910 /* set the wb address */ 911 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 912 (upper_32_bits(ring->gpu_addr) >> 2)); 913 914 /* programm the RB_BASE for ring buffer */ 915 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 916 lower_32_bits(ring->gpu_addr)); 917 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 918 upper_32_bits(ring->gpu_addr)); 919 920 /* Initialize the ring buffer's read and write pointers */ 921 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 922 923 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 924 925 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 926 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 927 lower_32_bits(ring->wptr)); 928 929 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 930 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 931 932 ring = &adev->vcn.inst->ring_enc[0]; 933 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 934 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 935 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 936 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 937 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 938 939 ring = &adev->vcn.inst->ring_enc[1]; 940 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 941 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 942 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 943 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 944 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 945 946 jpeg_v1_0_start(adev, 0); 947 948 return 0; 949 } 950 951 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 952 { 953 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 954 uint32_t rb_bufsz, tmp; 955 uint32_t lmi_swap_cntl; 956 957 /* disable byte swapping */ 958 lmi_swap_cntl = 0; 959 960 vcn_1_0_enable_static_power_gating(adev); 961 962 /* enable dynamic power gating mode */ 963 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 964 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 965 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 966 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 967 968 /* enable clock gating */ 969 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 970 971 /* enable VCPU clock */ 972 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 973 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 974 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 975 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 976 977 /* disable interupt */ 978 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 979 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 980 981 /* initialize VCN memory controller */ 982 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 983 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 984 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 985 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 986 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 987 UVD_LMI_CTRL__REQ_MODE_MASK | 988 UVD_LMI_CTRL__CRC_RESET_MASK | 989 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 990 0x00100000L, 0xFFFFFFFF, 0); 991 992 #ifdef __BIG_ENDIAN 993 /* swap (8 in 32) RB and IB */ 994 lmi_swap_cntl = 0xa; 995 #endif 996 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 997 998 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, 999 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1000 1001 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, 1002 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1003 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1004 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1005 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1006 1007 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, 1008 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1009 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1010 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1011 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1012 1013 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, 1014 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1015 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1016 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1017 1018 vcn_v1_0_mc_resume_dpg_mode(adev); 1019 1020 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1021 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1022 1023 /* boot up the VCPU */ 1024 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1025 1026 /* enable UMC */ 1027 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, 1028 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1029 0xFFFFFFFF, 0); 1030 1031 /* enable master interrupt */ 1032 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 1033 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1034 1035 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1036 /* setup mmUVD_LMI_CTRL */ 1037 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1038 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1039 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1040 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1041 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1042 UVD_LMI_CTRL__REQ_MODE_MASK | 1043 UVD_LMI_CTRL__CRC_RESET_MASK | 1044 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1045 0x00100000L, 0xFFFFFFFF, 1); 1046 1047 tmp = adev->gfx.config.gb_addr_config; 1048 /* setup VCN global tiling registers */ 1049 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1050 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1051 1052 /* enable System Interrupt for JRBC */ 1053 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, 1054 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1055 1056 /* force RBC into idle state */ 1057 rb_bufsz = order_base_2(ring->ring_size); 1058 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1063 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1064 1065 /* set the write pointer delay */ 1066 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1067 1068 /* set the wb address */ 1069 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1070 (upper_32_bits(ring->gpu_addr) >> 2)); 1071 1072 /* programm the RB_BASE for ring buffer */ 1073 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1074 lower_32_bits(ring->gpu_addr)); 1075 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1076 upper_32_bits(ring->gpu_addr)); 1077 1078 /* Initialize the ring buffer's read and write pointers */ 1079 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1080 1081 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1082 1083 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1084 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1085 lower_32_bits(ring->wptr)); 1086 1087 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1088 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1089 1090 jpeg_v1_0_start(adev, 1); 1091 1092 return 0; 1093 } 1094 1095 static int vcn_v1_0_start(struct amdgpu_device *adev) 1096 { 1097 int r; 1098 1099 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1100 r = vcn_v1_0_start_dpg_mode(adev); 1101 else 1102 r = vcn_v1_0_start_spg_mode(adev); 1103 return r; 1104 } 1105 1106 /** 1107 * vcn_v1_0_stop - stop VCN block 1108 * 1109 * @adev: amdgpu_device pointer 1110 * 1111 * stop the VCN block 1112 */ 1113 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1114 { 1115 int ret_code, tmp; 1116 1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1118 1119 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1120 UVD_LMI_STATUS__READ_CLEAN_MASK | 1121 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1122 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1123 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1124 1125 /* put VCPU into reset */ 1126 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1127 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1128 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1129 1130 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1131 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1132 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1133 1134 /* disable VCPU clock */ 1135 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1136 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1137 1138 /* reset LMI UMC/LMI */ 1139 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1140 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1141 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1142 1143 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1144 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1145 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1146 1147 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1148 1149 vcn_v1_0_enable_clock_gating(adev); 1150 vcn_1_0_enable_static_power_gating(adev); 1151 return 0; 1152 } 1153 1154 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1155 { 1156 int ret_code = 0; 1157 uint32_t tmp; 1158 1159 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1160 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1161 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1162 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1163 1164 /* wait for read ptr to be equal to write ptr */ 1165 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1166 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1167 1168 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1169 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1170 1171 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1172 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1173 1174 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1175 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1176 1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1178 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1179 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1180 1181 /* disable dynamic power gating mode */ 1182 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1183 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1184 1185 return 0; 1186 } 1187 1188 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1189 { 1190 int r; 1191 1192 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1193 r = vcn_v1_0_stop_dpg_mode(adev); 1194 else 1195 r = vcn_v1_0_stop_spg_mode(adev); 1196 1197 return r; 1198 } 1199 1200 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1201 int inst_idx, struct dpg_pause_state *new_state) 1202 { 1203 int ret_code; 1204 uint32_t reg_data = 0; 1205 uint32_t reg_data2 = 0; 1206 struct amdgpu_ring *ring; 1207 1208 /* pause/unpause if state is changed */ 1209 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1210 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1211 adev->vcn.inst[inst_idx].pause_state.fw_based, 1212 adev->vcn.inst[inst_idx].pause_state.jpeg, 1213 new_state->fw_based, new_state->jpeg); 1214 1215 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1216 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1217 1218 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1219 ret_code = 0; 1220 1221 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1222 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1223 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1224 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1225 1226 if (!ret_code) { 1227 /* pause DPG non-jpeg */ 1228 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1229 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1230 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1231 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1232 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1233 1234 /* Restore */ 1235 ring = &adev->vcn.inst->ring_enc[0]; 1236 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1238 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1239 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1240 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1241 1242 ring = &adev->vcn.inst->ring_enc[1]; 1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1248 1249 ring = &adev->vcn.inst->ring_dec; 1250 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1251 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1252 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1253 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1254 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1255 } 1256 } else { 1257 /* unpause dpg non-jpeg, no need to wait */ 1258 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1259 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1260 } 1261 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1262 } 1263 1264 /* pause/unpause if state is changed */ 1265 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1266 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1267 adev->vcn.inst[inst_idx].pause_state.fw_based, 1268 adev->vcn.inst[inst_idx].pause_state.jpeg, 1269 new_state->fw_based, new_state->jpeg); 1270 1271 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1272 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1273 1274 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1275 ret_code = 0; 1276 1277 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1278 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1279 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1280 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1281 1282 if (!ret_code) { 1283 /* Make sure JPRG Snoop is disabled before sending the pause */ 1284 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1285 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1286 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1287 1288 /* pause DPG jpeg */ 1289 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1290 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1291 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1292 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1293 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); 1294 1295 /* Restore */ 1296 ring = &adev->jpeg.inst->ring_dec; 1297 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1298 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1299 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1300 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1301 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1302 lower_32_bits(ring->gpu_addr)); 1303 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1304 upper_32_bits(ring->gpu_addr)); 1305 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1306 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1307 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1308 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1309 1310 ring = &adev->vcn.inst->ring_dec; 1311 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1312 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1313 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1314 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1315 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1316 } 1317 } else { 1318 /* unpause dpg jpeg, no need to wait */ 1319 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1320 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1321 } 1322 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static bool vcn_v1_0_is_idle(void *handle) 1329 { 1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1331 1332 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1333 } 1334 1335 static int vcn_v1_0_wait_for_idle(void *handle) 1336 { 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 int ret = 0; 1339 1340 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1341 UVD_STATUS__IDLE, ret); 1342 1343 return ret; 1344 } 1345 1346 static int vcn_v1_0_set_clockgating_state(void *handle, 1347 enum amd_clockgating_state state) 1348 { 1349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1350 bool enable = (state == AMD_CG_STATE_GATE); 1351 1352 if (enable) { 1353 /* wait for STATUS to clear */ 1354 if (!vcn_v1_0_is_idle(handle)) 1355 return -EBUSY; 1356 vcn_v1_0_enable_clock_gating(adev); 1357 } else { 1358 /* disable HW gating and enable Sw gating */ 1359 vcn_v1_0_disable_clock_gating(adev); 1360 } 1361 return 0; 1362 } 1363 1364 /** 1365 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1366 * 1367 * @ring: amdgpu_ring pointer 1368 * 1369 * Returns the current hardware read pointer 1370 */ 1371 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1372 { 1373 struct amdgpu_device *adev = ring->adev; 1374 1375 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1376 } 1377 1378 /** 1379 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1380 * 1381 * @ring: amdgpu_ring pointer 1382 * 1383 * Returns the current hardware write pointer 1384 */ 1385 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1386 { 1387 struct amdgpu_device *adev = ring->adev; 1388 1389 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1390 } 1391 1392 /** 1393 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1394 * 1395 * @ring: amdgpu_ring pointer 1396 * 1397 * Commits the write pointer to the hardware 1398 */ 1399 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1400 { 1401 struct amdgpu_device *adev = ring->adev; 1402 1403 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1404 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1405 lower_32_bits(ring->wptr) | 0x80000000); 1406 1407 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1408 } 1409 1410 /** 1411 * vcn_v1_0_dec_ring_insert_start - insert a start command 1412 * 1413 * @ring: amdgpu_ring pointer 1414 * 1415 * Write a start command to the ring. 1416 */ 1417 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1418 { 1419 struct amdgpu_device *adev = ring->adev; 1420 1421 amdgpu_ring_write(ring, 1422 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1423 amdgpu_ring_write(ring, 0); 1424 amdgpu_ring_write(ring, 1425 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1426 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1427 } 1428 1429 /** 1430 * vcn_v1_0_dec_ring_insert_end - insert a end command 1431 * 1432 * @ring: amdgpu_ring pointer 1433 * 1434 * Write a end command to the ring. 1435 */ 1436 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1437 { 1438 struct amdgpu_device *adev = ring->adev; 1439 1440 amdgpu_ring_write(ring, 1441 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1442 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1443 } 1444 1445 /** 1446 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1447 * 1448 * @ring: amdgpu_ring pointer 1449 * @fence: fence to emit 1450 * 1451 * Write a fence and a trap command to the ring. 1452 */ 1453 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1454 unsigned flags) 1455 { 1456 struct amdgpu_device *adev = ring->adev; 1457 1458 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1459 1460 amdgpu_ring_write(ring, 1461 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1462 amdgpu_ring_write(ring, seq); 1463 amdgpu_ring_write(ring, 1464 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1465 amdgpu_ring_write(ring, addr & 0xffffffff); 1466 amdgpu_ring_write(ring, 1467 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1468 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1469 amdgpu_ring_write(ring, 1470 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1471 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1472 1473 amdgpu_ring_write(ring, 1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1475 amdgpu_ring_write(ring, 0); 1476 amdgpu_ring_write(ring, 1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1478 amdgpu_ring_write(ring, 0); 1479 amdgpu_ring_write(ring, 1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1481 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1482 } 1483 1484 /** 1485 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1486 * 1487 * @ring: amdgpu_ring pointer 1488 * @ib: indirect buffer to execute 1489 * 1490 * Write ring commands to execute the indirect buffer 1491 */ 1492 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1493 struct amdgpu_job *job, 1494 struct amdgpu_ib *ib, 1495 uint32_t flags) 1496 { 1497 struct amdgpu_device *adev = ring->adev; 1498 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1499 1500 amdgpu_ring_write(ring, 1501 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1502 amdgpu_ring_write(ring, vmid); 1503 1504 amdgpu_ring_write(ring, 1505 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1506 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1507 amdgpu_ring_write(ring, 1508 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1509 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1510 amdgpu_ring_write(ring, 1511 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1512 amdgpu_ring_write(ring, ib->length_dw); 1513 } 1514 1515 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1516 uint32_t reg, uint32_t val, 1517 uint32_t mask) 1518 { 1519 struct amdgpu_device *adev = ring->adev; 1520 1521 amdgpu_ring_write(ring, 1522 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1523 amdgpu_ring_write(ring, reg << 2); 1524 amdgpu_ring_write(ring, 1525 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1526 amdgpu_ring_write(ring, val); 1527 amdgpu_ring_write(ring, 1528 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1529 amdgpu_ring_write(ring, mask); 1530 amdgpu_ring_write(ring, 1531 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1532 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1533 } 1534 1535 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1536 unsigned vmid, uint64_t pd_addr) 1537 { 1538 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1539 uint32_t data0, data1, mask; 1540 1541 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1542 1543 /* wait for register write */ 1544 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1545 data1 = lower_32_bits(pd_addr); 1546 mask = 0xffffffff; 1547 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1548 } 1549 1550 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1551 uint32_t reg, uint32_t val) 1552 { 1553 struct amdgpu_device *adev = ring->adev; 1554 1555 amdgpu_ring_write(ring, 1556 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1557 amdgpu_ring_write(ring, reg << 2); 1558 amdgpu_ring_write(ring, 1559 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1560 amdgpu_ring_write(ring, val); 1561 amdgpu_ring_write(ring, 1562 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1563 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1564 } 1565 1566 /** 1567 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1568 * 1569 * @ring: amdgpu_ring pointer 1570 * 1571 * Returns the current hardware enc read pointer 1572 */ 1573 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1574 { 1575 struct amdgpu_device *adev = ring->adev; 1576 1577 if (ring == &adev->vcn.inst->ring_enc[0]) 1578 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1579 else 1580 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1581 } 1582 1583 /** 1584 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1585 * 1586 * @ring: amdgpu_ring pointer 1587 * 1588 * Returns the current hardware enc write pointer 1589 */ 1590 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1591 { 1592 struct amdgpu_device *adev = ring->adev; 1593 1594 if (ring == &adev->vcn.inst->ring_enc[0]) 1595 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1596 else 1597 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1598 } 1599 1600 /** 1601 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1602 * 1603 * @ring: amdgpu_ring pointer 1604 * 1605 * Commits the enc write pointer to the hardware 1606 */ 1607 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1608 { 1609 struct amdgpu_device *adev = ring->adev; 1610 1611 if (ring == &adev->vcn.inst->ring_enc[0]) 1612 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1613 lower_32_bits(ring->wptr)); 1614 else 1615 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1616 lower_32_bits(ring->wptr)); 1617 } 1618 1619 /** 1620 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1621 * 1622 * @ring: amdgpu_ring pointer 1623 * @fence: fence to emit 1624 * 1625 * Write enc a fence and a trap command to the ring. 1626 */ 1627 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1628 u64 seq, unsigned flags) 1629 { 1630 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1631 1632 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1633 amdgpu_ring_write(ring, addr); 1634 amdgpu_ring_write(ring, upper_32_bits(addr)); 1635 amdgpu_ring_write(ring, seq); 1636 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1637 } 1638 1639 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1640 { 1641 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1642 } 1643 1644 /** 1645 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1646 * 1647 * @ring: amdgpu_ring pointer 1648 * @ib: indirect buffer to execute 1649 * 1650 * Write enc ring commands to execute the indirect buffer 1651 */ 1652 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1653 struct amdgpu_job *job, 1654 struct amdgpu_ib *ib, 1655 uint32_t flags) 1656 { 1657 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1658 1659 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1660 amdgpu_ring_write(ring, vmid); 1661 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1662 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1663 amdgpu_ring_write(ring, ib->length_dw); 1664 } 1665 1666 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1667 uint32_t reg, uint32_t val, 1668 uint32_t mask) 1669 { 1670 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1671 amdgpu_ring_write(ring, reg << 2); 1672 amdgpu_ring_write(ring, mask); 1673 amdgpu_ring_write(ring, val); 1674 } 1675 1676 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1677 unsigned int vmid, uint64_t pd_addr) 1678 { 1679 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1680 1681 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1682 1683 /* wait for reg writes */ 1684 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1685 lower_32_bits(pd_addr), 0xffffffff); 1686 } 1687 1688 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1689 uint32_t reg, uint32_t val) 1690 { 1691 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1692 amdgpu_ring_write(ring, reg << 2); 1693 amdgpu_ring_write(ring, val); 1694 } 1695 1696 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1697 struct amdgpu_irq_src *source, 1698 unsigned type, 1699 enum amdgpu_interrupt_state state) 1700 { 1701 return 0; 1702 } 1703 1704 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1705 struct amdgpu_irq_src *source, 1706 struct amdgpu_iv_entry *entry) 1707 { 1708 DRM_DEBUG("IH: VCN TRAP\n"); 1709 1710 switch (entry->src_id) { 1711 case 124: 1712 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1713 break; 1714 case 119: 1715 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1716 break; 1717 case 120: 1718 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1719 break; 1720 default: 1721 DRM_ERROR("Unhandled interrupt: %d %d\n", 1722 entry->src_id, entry->src_data[0]); 1723 break; 1724 } 1725 1726 return 0; 1727 } 1728 1729 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1730 { 1731 struct amdgpu_device *adev = ring->adev; 1732 int i; 1733 1734 WARN_ON(ring->wptr % 2 || count % 2); 1735 1736 for (i = 0; i < count / 2; i++) { 1737 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1738 amdgpu_ring_write(ring, 0); 1739 } 1740 } 1741 1742 static int vcn_v1_0_set_powergating_state(void *handle, 1743 enum amd_powergating_state state) 1744 { 1745 /* This doesn't actually powergate the VCN block. 1746 * That's done in the dpm code via the SMC. This 1747 * just re-inits the block as necessary. The actual 1748 * gating still happens in the dpm code. We should 1749 * revisit this when there is a cleaner line between 1750 * the smc and the hw blocks 1751 */ 1752 int ret; 1753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1754 1755 if(state == adev->vcn.cur_state) 1756 return 0; 1757 1758 if (state == AMD_PG_STATE_GATE) 1759 ret = vcn_v1_0_stop(adev); 1760 else 1761 ret = vcn_v1_0_start(adev); 1762 1763 if(!ret) 1764 adev->vcn.cur_state = state; 1765 return ret; 1766 } 1767 1768 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1769 { 1770 struct amdgpu_device *adev = 1771 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1772 unsigned int fences = 0, i; 1773 1774 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1775 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1776 1777 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1778 struct dpg_pause_state new_state; 1779 1780 if (fences) 1781 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1782 else 1783 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1784 1785 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1786 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1787 else 1788 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1789 1790 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1791 } 1792 1793 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1794 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1795 1796 if (fences == 0) { 1797 amdgpu_gfx_off_ctrl(adev, true); 1798 if (adev->pm.dpm_enabled) 1799 amdgpu_dpm_enable_uvd(adev, false); 1800 else 1801 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1802 AMD_PG_STATE_GATE); 1803 } else { 1804 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1805 } 1806 } 1807 1808 void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1809 { 1810 struct amdgpu_device *adev = ring->adev; 1811 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1812 1813 if (set_clocks) { 1814 amdgpu_gfx_off_ctrl(adev, false); 1815 if (adev->pm.dpm_enabled) 1816 amdgpu_dpm_enable_uvd(adev, true); 1817 else 1818 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1819 AMD_PG_STATE_UNGATE); 1820 } 1821 1822 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1823 struct dpg_pause_state new_state; 1824 unsigned int fences = 0, i; 1825 1826 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1827 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1828 1829 if (fences) 1830 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1831 else 1832 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1833 1834 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1835 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1836 else 1837 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1838 1839 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1840 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1841 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1842 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1843 1844 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1845 } 1846 } 1847 1848 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1849 .name = "vcn_v1_0", 1850 .early_init = vcn_v1_0_early_init, 1851 .late_init = NULL, 1852 .sw_init = vcn_v1_0_sw_init, 1853 .sw_fini = vcn_v1_0_sw_fini, 1854 .hw_init = vcn_v1_0_hw_init, 1855 .hw_fini = vcn_v1_0_hw_fini, 1856 .suspend = vcn_v1_0_suspend, 1857 .resume = vcn_v1_0_resume, 1858 .is_idle = vcn_v1_0_is_idle, 1859 .wait_for_idle = vcn_v1_0_wait_for_idle, 1860 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1861 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1862 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1863 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1864 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1865 .set_powergating_state = vcn_v1_0_set_powergating_state, 1866 }; 1867 1868 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1869 .type = AMDGPU_RING_TYPE_VCN_DEC, 1870 .align_mask = 0xf, 1871 .support_64bit_ptrs = false, 1872 .no_user_fence = true, 1873 .vmhub = AMDGPU_MMHUB_0, 1874 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1875 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1876 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1877 .emit_frame_size = 1878 6 + 6 + /* hdp invalidate / flush */ 1879 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1880 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1881 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1882 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1883 6, 1884 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1885 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1886 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1887 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1888 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1889 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1890 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1891 .insert_start = vcn_v1_0_dec_ring_insert_start, 1892 .insert_end = vcn_v1_0_dec_ring_insert_end, 1893 .pad_ib = amdgpu_ring_generic_pad_ib, 1894 .begin_use = vcn_v1_0_ring_begin_use, 1895 .end_use = amdgpu_vcn_ring_end_use, 1896 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1897 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1898 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1899 }; 1900 1901 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1902 .type = AMDGPU_RING_TYPE_VCN_ENC, 1903 .align_mask = 0x3f, 1904 .nop = VCN_ENC_CMD_NO_OP, 1905 .support_64bit_ptrs = false, 1906 .no_user_fence = true, 1907 .vmhub = AMDGPU_MMHUB_0, 1908 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1909 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1910 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1911 .emit_frame_size = 1912 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1913 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1914 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1915 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1916 1, /* vcn_v1_0_enc_ring_insert_end */ 1917 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1918 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1919 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1920 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1921 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1922 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1923 .insert_nop = amdgpu_ring_insert_nop, 1924 .insert_end = vcn_v1_0_enc_ring_insert_end, 1925 .pad_ib = amdgpu_ring_generic_pad_ib, 1926 .begin_use = vcn_v1_0_ring_begin_use, 1927 .end_use = amdgpu_vcn_ring_end_use, 1928 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1929 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1930 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1931 }; 1932 1933 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1934 { 1935 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1936 DRM_INFO("VCN decode is enabled in VM mode\n"); 1937 } 1938 1939 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1940 { 1941 int i; 1942 1943 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1944 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1945 1946 DRM_INFO("VCN encode is enabled in VM mode\n"); 1947 } 1948 1949 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1950 .set = vcn_v1_0_set_interrupt_state, 1951 .process = vcn_v1_0_process_interrupt, 1952 }; 1953 1954 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1955 { 1956 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 1957 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 1958 } 1959 1960 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1961 { 1962 .type = AMD_IP_BLOCK_TYPE_VCN, 1963 .major = 1, 1964 .minor = 0, 1965 .rev = 0, 1966 .funcs = &vcn_v1_0_ip_funcs, 1967 }; 1968