1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu.h"
25 #include "vcn_sw_ring.h"
26 
27 void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
28 	u64 seq, uint32_t flags)
29 {
30 	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
31 
32 	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
33 	amdgpu_ring_write(ring, addr);
34 	amdgpu_ring_write(ring, upper_32_bits(addr));
35 	amdgpu_ring_write(ring, seq);
36 	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
37 }
38 
39 void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
40 {
41 	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
42 }
43 
44 void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
45 	struct amdgpu_ib *ib, uint32_t flags)
46 {
47 	uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
48 
49 	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
50 	amdgpu_ring_write(ring, vmid);
51 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
52 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
53 	amdgpu_ring_write(ring, ib->length_dw);
54 }
55 
56 void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
57 	uint32_t val, uint32_t mask)
58 {
59 	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
60 	amdgpu_ring_write(ring, reg << 2);
61 	amdgpu_ring_write(ring, mask);
62 	amdgpu_ring_write(ring, val);
63 }
64 
65 void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
66 	uint32_t vmid, uint64_t pd_addr)
67 {
68 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
69 	uint32_t data0, data1, mask;
70 
71 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
72 
73 	/* wait for register write */
74 	data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
75 	data1 = lower_32_bits(pd_addr);
76 	mask = 0xffffffff;
77 	vcn_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
78 }
79 
80 void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
81 	uint32_t val)
82 {
83 	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
84 	amdgpu_ring_write(ring,	reg << 2);
85 	amdgpu_ring_write(ring, val);
86 }
87