1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * All Rights Reserved. 4aaa36a97SAlex Deucher * 5aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6aaa36a97SAlex Deucher * copy of this software and associated documentation files (the 7aaa36a97SAlex Deucher * "Software"), to deal in the Software without restriction, including 8aaa36a97SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9aaa36a97SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10aaa36a97SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11aaa36a97SAlex Deucher * the following conditions: 12aaa36a97SAlex Deucher * 13aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16aaa36a97SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17aaa36a97SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18aaa36a97SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19aaa36a97SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20aaa36a97SAlex Deucher * 21aaa36a97SAlex Deucher * The above copyright notice and this permission notice (including the 22aaa36a97SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23aaa36a97SAlex Deucher * of the Software. 24aaa36a97SAlex Deucher * 25aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 26aaa36a97SAlex Deucher */ 27aaa36a97SAlex Deucher 28aaa36a97SAlex Deucher #include <linux/firmware.h> 29aaa36a97SAlex Deucher #include <drm/drmP.h> 30aaa36a97SAlex Deucher #include "amdgpu.h" 31aaa36a97SAlex Deucher #include "amdgpu_vce.h" 32aaa36a97SAlex Deucher #include "vid.h" 33aaa36a97SAlex Deucher #include "vce/vce_3_0_d.h" 34aaa36a97SAlex Deucher #include "vce/vce_3_0_sh_mask.h" 35be4f38e2SAlex Deucher #include "oss/oss_3_0_d.h" 36be4f38e2SAlex Deucher #include "oss/oss_3_0_sh_mask.h" 375bbc553aSLeo Liu #include "gca/gfx_8_0_d.h" 386a585777SAlex Deucher #include "smu/smu_7_1_2_d.h" 396a585777SAlex Deucher #include "smu/smu_7_1_2_sh_mask.h" 405bbc553aSLeo Liu 415bbc553aSLeo Liu #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 425bbc553aSLeo Liu #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 43aaa36a97SAlex Deucher 44e9822622SLeo Liu #define VCE_V3_0_FW_SIZE (384 * 1024) 45e9822622SLeo Liu #define VCE_V3_0_STACK_SIZE (64 * 1024) 46e9822622SLeo Liu #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) 47e9822622SLeo Liu 485bbc553aSLeo Liu static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); 49aaa36a97SAlex Deucher static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); 50aaa36a97SAlex Deucher static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51aaa36a97SAlex Deucher 52aaa36a97SAlex Deucher /** 53aaa36a97SAlex Deucher * vce_v3_0_ring_get_rptr - get read pointer 54aaa36a97SAlex Deucher * 55aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 56aaa36a97SAlex Deucher * 57aaa36a97SAlex Deucher * Returns the current hardware read pointer 58aaa36a97SAlex Deucher */ 59aaa36a97SAlex Deucher static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 60aaa36a97SAlex Deucher { 61aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 62aaa36a97SAlex Deucher 63aaa36a97SAlex Deucher if (ring == &adev->vce.ring[0]) 64aaa36a97SAlex Deucher return RREG32(mmVCE_RB_RPTR); 65aaa36a97SAlex Deucher else 66aaa36a97SAlex Deucher return RREG32(mmVCE_RB_RPTR2); 67aaa36a97SAlex Deucher } 68aaa36a97SAlex Deucher 69aaa36a97SAlex Deucher /** 70aaa36a97SAlex Deucher * vce_v3_0_ring_get_wptr - get write pointer 71aaa36a97SAlex Deucher * 72aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 73aaa36a97SAlex Deucher * 74aaa36a97SAlex Deucher * Returns the current hardware write pointer 75aaa36a97SAlex Deucher */ 76aaa36a97SAlex Deucher static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 77aaa36a97SAlex Deucher { 78aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 79aaa36a97SAlex Deucher 80aaa36a97SAlex Deucher if (ring == &adev->vce.ring[0]) 81aaa36a97SAlex Deucher return RREG32(mmVCE_RB_WPTR); 82aaa36a97SAlex Deucher else 83aaa36a97SAlex Deucher return RREG32(mmVCE_RB_WPTR2); 84aaa36a97SAlex Deucher } 85aaa36a97SAlex Deucher 86aaa36a97SAlex Deucher /** 87aaa36a97SAlex Deucher * vce_v3_0_ring_set_wptr - set write pointer 88aaa36a97SAlex Deucher * 89aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 90aaa36a97SAlex Deucher * 91aaa36a97SAlex Deucher * Commits the write pointer to the hardware 92aaa36a97SAlex Deucher */ 93aaa36a97SAlex Deucher static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 94aaa36a97SAlex Deucher { 95aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 96aaa36a97SAlex Deucher 97aaa36a97SAlex Deucher if (ring == &adev->vce.ring[0]) 98aaa36a97SAlex Deucher WREG32(mmVCE_RB_WPTR, ring->wptr); 99aaa36a97SAlex Deucher else 100aaa36a97SAlex Deucher WREG32(mmVCE_RB_WPTR2, ring->wptr); 101aaa36a97SAlex Deucher } 102aaa36a97SAlex Deucher 103aaa36a97SAlex Deucher /** 104aaa36a97SAlex Deucher * vce_v3_0_start - start VCE block 105aaa36a97SAlex Deucher * 106aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 107aaa36a97SAlex Deucher * 108aaa36a97SAlex Deucher * Setup and start the VCE block 109aaa36a97SAlex Deucher */ 110aaa36a97SAlex Deucher static int vce_v3_0_start(struct amdgpu_device *adev) 111aaa36a97SAlex Deucher { 112aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1135bbc553aSLeo Liu int idx, i, j, r; 114aaa36a97SAlex Deucher 1155bbc553aSLeo Liu mutex_lock(&adev->grbm_idx_mutex); 1165bbc553aSLeo Liu for (idx = 0; idx < 2; ++idx) { 1176a585777SAlex Deucher 1186a585777SAlex Deucher if (adev->vce.harvest_config & (1 << idx)) 1196a585777SAlex Deucher continue; 1206a585777SAlex Deucher 1215bbc553aSLeo Liu if(idx == 0) 1225bbc553aSLeo Liu WREG32_P(mmGRBM_GFX_INDEX, 0, 1235bbc553aSLeo Liu ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 1245bbc553aSLeo Liu else 1255bbc553aSLeo Liu WREG32_P(mmGRBM_GFX_INDEX, 1265bbc553aSLeo Liu GRBM_GFX_INDEX__VCE_INSTANCE_MASK, 1275bbc553aSLeo Liu ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 1285bbc553aSLeo Liu 1295bbc553aSLeo Liu vce_v3_0_mc_resume(adev, idx); 130aaa36a97SAlex Deucher 131aaa36a97SAlex Deucher /* set BUSY flag */ 132aaa36a97SAlex Deucher WREG32_P(mmVCE_STATUS, 1, ~1); 133aaa36a97SAlex Deucher 1345bbc553aSLeo Liu WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, 1355bbc553aSLeo Liu ~VCE_VCPU_CNTL__CLK_EN_MASK); 136aaa36a97SAlex Deucher 137aaa36a97SAlex Deucher WREG32_P(mmVCE_SOFT_RESET, 138aaa36a97SAlex Deucher VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 139aaa36a97SAlex Deucher ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 140aaa36a97SAlex Deucher 141aaa36a97SAlex Deucher mdelay(100); 142aaa36a97SAlex Deucher 1435bbc553aSLeo Liu WREG32_P(mmVCE_SOFT_RESET, 0, 1445bbc553aSLeo Liu ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 145aaa36a97SAlex Deucher 146aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 147aaa36a97SAlex Deucher uint32_t status; 148aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 149aaa36a97SAlex Deucher status = RREG32(mmVCE_STATUS); 150aaa36a97SAlex Deucher if (status & 2) 151aaa36a97SAlex Deucher break; 152aaa36a97SAlex Deucher mdelay(10); 153aaa36a97SAlex Deucher } 154aaa36a97SAlex Deucher r = 0; 155aaa36a97SAlex Deucher if (status & 2) 156aaa36a97SAlex Deucher break; 157aaa36a97SAlex Deucher 158aaa36a97SAlex Deucher DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); 1595bbc553aSLeo Liu WREG32_P(mmVCE_SOFT_RESET, 1605bbc553aSLeo Liu VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 161aaa36a97SAlex Deucher ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 162aaa36a97SAlex Deucher mdelay(10); 1635bbc553aSLeo Liu WREG32_P(mmVCE_SOFT_RESET, 0, 1645bbc553aSLeo Liu ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 165aaa36a97SAlex Deucher mdelay(10); 166aaa36a97SAlex Deucher r = -1; 167aaa36a97SAlex Deucher } 168aaa36a97SAlex Deucher 169aaa36a97SAlex Deucher /* clear BUSY flag */ 170aaa36a97SAlex Deucher WREG32_P(mmVCE_STATUS, 0, ~1); 171aaa36a97SAlex Deucher 172aaa36a97SAlex Deucher if (r) { 173aaa36a97SAlex Deucher DRM_ERROR("VCE not responding, giving up!!!\n"); 1745bbc553aSLeo Liu mutex_unlock(&adev->grbm_idx_mutex); 175aaa36a97SAlex Deucher return r; 176aaa36a97SAlex Deucher } 1775bbc553aSLeo Liu } 1785bbc553aSLeo Liu 1795bbc553aSLeo Liu WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 1805bbc553aSLeo Liu mutex_unlock(&adev->grbm_idx_mutex); 1815bbc553aSLeo Liu 1825bbc553aSLeo Liu ring = &adev->vce.ring[0]; 1835bbc553aSLeo Liu WREG32(mmVCE_RB_RPTR, ring->wptr); 1845bbc553aSLeo Liu WREG32(mmVCE_RB_WPTR, ring->wptr); 1855bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); 1865bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1875bbc553aSLeo Liu WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); 1885bbc553aSLeo Liu 1895bbc553aSLeo Liu ring = &adev->vce.ring[1]; 1905bbc553aSLeo Liu WREG32(mmVCE_RB_RPTR2, ring->wptr); 1915bbc553aSLeo Liu WREG32(mmVCE_RB_WPTR2, ring->wptr); 1925bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); 1935bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1945bbc553aSLeo Liu WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); 195aaa36a97SAlex Deucher 196aaa36a97SAlex Deucher return 0; 197aaa36a97SAlex Deucher } 198aaa36a97SAlex Deucher 1996a585777SAlex Deucher #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074 2006a585777SAlex Deucher #define VCE_HARVEST_FUSE_MACRO__SHIFT 27 2016a585777SAlex Deucher #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000 2026a585777SAlex Deucher 2036a585777SAlex Deucher static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) 2046a585777SAlex Deucher { 2056a585777SAlex Deucher u32 tmp; 2066a585777SAlex Deucher unsigned ret; 2076a585777SAlex Deucher 208cfaba566SSamuel Li /* Fiji, Stoney are single pipe */ 209cfaba566SSamuel Li if ((adev->asic_type == CHIP_FIJI) || 210cfaba566SSamuel Li (adev->asic_type == CHIP_STONEY)){ 211188a9bcdSAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE1; 212188a9bcdSAlex Deucher return ret; 213188a9bcdSAlex Deucher } 214188a9bcdSAlex Deucher 215188a9bcdSAlex Deucher /* Tonga and CZ are dual or single pipe */ 2162f7d10b3SJammy Zhou if (adev->flags & AMD_IS_APU) 2176a585777SAlex Deucher tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & 2186a585777SAlex Deucher VCE_HARVEST_FUSE_MACRO__MASK) >> 2196a585777SAlex Deucher VCE_HARVEST_FUSE_MACRO__SHIFT; 2206a585777SAlex Deucher else 2216a585777SAlex Deucher tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & 2226a585777SAlex Deucher CC_HARVEST_FUSES__VCE_DISABLE_MASK) >> 2236a585777SAlex Deucher CC_HARVEST_FUSES__VCE_DISABLE__SHIFT; 2246a585777SAlex Deucher 2256a585777SAlex Deucher switch (tmp) { 2266a585777SAlex Deucher case 1: 2276a585777SAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE0; 2286a585777SAlex Deucher break; 2296a585777SAlex Deucher case 2: 2306a585777SAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE1; 2316a585777SAlex Deucher break; 2326a585777SAlex Deucher case 3: 2336a585777SAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1; 2346a585777SAlex Deucher break; 2356a585777SAlex Deucher default: 2366a585777SAlex Deucher ret = 0; 2376a585777SAlex Deucher } 2386a585777SAlex Deucher 2396a585777SAlex Deucher return ret; 2406a585777SAlex Deucher } 2416a585777SAlex Deucher 2425fc3aeebSyanyang1 static int vce_v3_0_early_init(void *handle) 243aaa36a97SAlex Deucher { 2445fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2455fc3aeebSyanyang1 2466a585777SAlex Deucher adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); 2476a585777SAlex Deucher 2486a585777SAlex Deucher if ((adev->vce.harvest_config & 2496a585777SAlex Deucher (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) == 2506a585777SAlex Deucher (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) 2516a585777SAlex Deucher return -ENOENT; 2526a585777SAlex Deucher 253aaa36a97SAlex Deucher vce_v3_0_set_ring_funcs(adev); 254aaa36a97SAlex Deucher vce_v3_0_set_irq_funcs(adev); 255aaa36a97SAlex Deucher 256aaa36a97SAlex Deucher return 0; 257aaa36a97SAlex Deucher } 258aaa36a97SAlex Deucher 2595fc3aeebSyanyang1 static int vce_v3_0_sw_init(void *handle) 260aaa36a97SAlex Deucher { 2615fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 262aaa36a97SAlex Deucher struct amdgpu_ring *ring; 263aaa36a97SAlex Deucher int r; 264aaa36a97SAlex Deucher 265aaa36a97SAlex Deucher /* VCE */ 266aaa36a97SAlex Deucher r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); 267aaa36a97SAlex Deucher if (r) 268aaa36a97SAlex Deucher return r; 269aaa36a97SAlex Deucher 270e9822622SLeo Liu r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + 271e9822622SLeo Liu (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); 272aaa36a97SAlex Deucher if (r) 273aaa36a97SAlex Deucher return r; 274aaa36a97SAlex Deucher 275aaa36a97SAlex Deucher r = amdgpu_vce_resume(adev); 276aaa36a97SAlex Deucher if (r) 277aaa36a97SAlex Deucher return r; 278aaa36a97SAlex Deucher 279aaa36a97SAlex Deucher ring = &adev->vce.ring[0]; 280aaa36a97SAlex Deucher sprintf(ring->name, "vce0"); 281aaa36a97SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, 282aaa36a97SAlex Deucher &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); 283aaa36a97SAlex Deucher if (r) 284aaa36a97SAlex Deucher return r; 285aaa36a97SAlex Deucher 286aaa36a97SAlex Deucher ring = &adev->vce.ring[1]; 287aaa36a97SAlex Deucher sprintf(ring->name, "vce1"); 288aaa36a97SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, 289aaa36a97SAlex Deucher &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); 290aaa36a97SAlex Deucher if (r) 291aaa36a97SAlex Deucher return r; 292aaa36a97SAlex Deucher 293aaa36a97SAlex Deucher return r; 294aaa36a97SAlex Deucher } 295aaa36a97SAlex Deucher 2965fc3aeebSyanyang1 static int vce_v3_0_sw_fini(void *handle) 297aaa36a97SAlex Deucher { 298aaa36a97SAlex Deucher int r; 2995fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 300aaa36a97SAlex Deucher 301aaa36a97SAlex Deucher r = amdgpu_vce_suspend(adev); 302aaa36a97SAlex Deucher if (r) 303aaa36a97SAlex Deucher return r; 304aaa36a97SAlex Deucher 305aaa36a97SAlex Deucher r = amdgpu_vce_sw_fini(adev); 306aaa36a97SAlex Deucher if (r) 307aaa36a97SAlex Deucher return r; 308aaa36a97SAlex Deucher 309aaa36a97SAlex Deucher return r; 310aaa36a97SAlex Deucher } 311aaa36a97SAlex Deucher 3125fc3aeebSyanyang1 static int vce_v3_0_hw_init(void *handle) 313aaa36a97SAlex Deucher { 314aaa36a97SAlex Deucher struct amdgpu_ring *ring; 315aaa36a97SAlex Deucher int r; 3165fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 317aaa36a97SAlex Deucher 318aaa36a97SAlex Deucher r = vce_v3_0_start(adev); 319aaa36a97SAlex Deucher if (r) 320aaa36a97SAlex Deucher return r; 321aaa36a97SAlex Deucher 322aaa36a97SAlex Deucher ring = &adev->vce.ring[0]; 323aaa36a97SAlex Deucher ring->ready = true; 324aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 325aaa36a97SAlex Deucher if (r) { 326aaa36a97SAlex Deucher ring->ready = false; 327aaa36a97SAlex Deucher return r; 328aaa36a97SAlex Deucher } 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher ring = &adev->vce.ring[1]; 331aaa36a97SAlex Deucher ring->ready = true; 332aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 333aaa36a97SAlex Deucher if (r) { 334aaa36a97SAlex Deucher ring->ready = false; 335aaa36a97SAlex Deucher return r; 336aaa36a97SAlex Deucher } 337aaa36a97SAlex Deucher 338aaa36a97SAlex Deucher DRM_INFO("VCE initialized successfully.\n"); 339aaa36a97SAlex Deucher 340aaa36a97SAlex Deucher return 0; 341aaa36a97SAlex Deucher } 342aaa36a97SAlex Deucher 3435fc3aeebSyanyang1 static int vce_v3_0_hw_fini(void *handle) 344aaa36a97SAlex Deucher { 345aaa36a97SAlex Deucher return 0; 346aaa36a97SAlex Deucher } 347aaa36a97SAlex Deucher 3485fc3aeebSyanyang1 static int vce_v3_0_suspend(void *handle) 349aaa36a97SAlex Deucher { 350aaa36a97SAlex Deucher int r; 3515fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 352aaa36a97SAlex Deucher 353aaa36a97SAlex Deucher r = vce_v3_0_hw_fini(adev); 354aaa36a97SAlex Deucher if (r) 355aaa36a97SAlex Deucher return r; 356aaa36a97SAlex Deucher 357aaa36a97SAlex Deucher r = amdgpu_vce_suspend(adev); 358aaa36a97SAlex Deucher if (r) 359aaa36a97SAlex Deucher return r; 360aaa36a97SAlex Deucher 361aaa36a97SAlex Deucher return r; 362aaa36a97SAlex Deucher } 363aaa36a97SAlex Deucher 3645fc3aeebSyanyang1 static int vce_v3_0_resume(void *handle) 365aaa36a97SAlex Deucher { 366aaa36a97SAlex Deucher int r; 3675fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 368aaa36a97SAlex Deucher 369aaa36a97SAlex Deucher r = amdgpu_vce_resume(adev); 370aaa36a97SAlex Deucher if (r) 371aaa36a97SAlex Deucher return r; 372aaa36a97SAlex Deucher 373aaa36a97SAlex Deucher r = vce_v3_0_hw_init(adev); 374aaa36a97SAlex Deucher if (r) 375aaa36a97SAlex Deucher return r; 376aaa36a97SAlex Deucher 377aaa36a97SAlex Deucher return r; 378aaa36a97SAlex Deucher } 379aaa36a97SAlex Deucher 3805bbc553aSLeo Liu static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) 381aaa36a97SAlex Deucher { 382aaa36a97SAlex Deucher uint32_t offset, size; 383aaa36a97SAlex Deucher 384aaa36a97SAlex Deucher WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); 385aaa36a97SAlex Deucher WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); 386aaa36a97SAlex Deucher WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); 387aaa36a97SAlex Deucher WREG32(mmVCE_CLOCK_GATING_B, 0xf7); 388aaa36a97SAlex Deucher 389aaa36a97SAlex Deucher WREG32(mmVCE_LMI_CTRL, 0x00398000); 390aaa36a97SAlex Deucher WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); 391aaa36a97SAlex Deucher WREG32(mmVCE_LMI_SWAP_CNTL, 0); 392aaa36a97SAlex Deucher WREG32(mmVCE_LMI_SWAP_CNTL1, 0); 393aaa36a97SAlex Deucher WREG32(mmVCE_LMI_VM_CTRL, 0); 394aaa36a97SAlex Deucher 395aaa36a97SAlex Deucher WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); 396aaa36a97SAlex Deucher offset = AMDGPU_VCE_FIRMWARE_OFFSET; 397e9822622SLeo Liu size = VCE_V3_0_FW_SIZE; 398aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); 399aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_SIZE0, size); 400aaa36a97SAlex Deucher 4015bbc553aSLeo Liu if (idx == 0) { 402aaa36a97SAlex Deucher offset += size; 403e9822622SLeo Liu size = VCE_V3_0_STACK_SIZE; 404aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); 405aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_SIZE1, size); 406aaa36a97SAlex Deucher offset += size; 407e9822622SLeo Liu size = VCE_V3_0_DATA_SIZE; 408aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); 409aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_SIZE2, size); 4105bbc553aSLeo Liu } else { 4115bbc553aSLeo Liu offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE; 4125bbc553aSLeo Liu size = VCE_V3_0_STACK_SIZE; 4135bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff); 4145bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_SIZE1, size); 4155bbc553aSLeo Liu offset += size; 4165bbc553aSLeo Liu size = VCE_V3_0_DATA_SIZE; 4175bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff); 4185bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_SIZE2, size); 4195bbc553aSLeo Liu } 420aaa36a97SAlex Deucher 421aaa36a97SAlex Deucher WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); 422aaa36a97SAlex Deucher 423aaa36a97SAlex Deucher WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK, 424aaa36a97SAlex Deucher ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 425aaa36a97SAlex Deucher } 426aaa36a97SAlex Deucher 4275fc3aeebSyanyang1 static bool vce_v3_0_is_idle(void *handle) 428aaa36a97SAlex Deucher { 4295fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 430be4f38e2SAlex Deucher u32 mask = 0; 431be4f38e2SAlex Deucher int idx; 4325fc3aeebSyanyang1 433be4f38e2SAlex Deucher for (idx = 0; idx < 2; ++idx) { 434be4f38e2SAlex Deucher if (adev->vce.harvest_config & (1 << idx)) 435be4f38e2SAlex Deucher continue; 436be4f38e2SAlex Deucher 437be4f38e2SAlex Deucher if (idx == 0) 438be4f38e2SAlex Deucher mask |= SRBM_STATUS2__VCE0_BUSY_MASK; 439be4f38e2SAlex Deucher else 440be4f38e2SAlex Deucher mask |= SRBM_STATUS2__VCE1_BUSY_MASK; 441be4f38e2SAlex Deucher } 442be4f38e2SAlex Deucher 443be4f38e2SAlex Deucher return !(RREG32(mmSRBM_STATUS2) & mask); 444aaa36a97SAlex Deucher } 445aaa36a97SAlex Deucher 4465fc3aeebSyanyang1 static int vce_v3_0_wait_for_idle(void *handle) 447aaa36a97SAlex Deucher { 448aaa36a97SAlex Deucher unsigned i; 4495fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 450be4f38e2SAlex Deucher u32 mask = 0; 451be4f38e2SAlex Deucher int idx; 452be4f38e2SAlex Deucher 453be4f38e2SAlex Deucher for (idx = 0; idx < 2; ++idx) { 454be4f38e2SAlex Deucher if (adev->vce.harvest_config & (1 << idx)) 455be4f38e2SAlex Deucher continue; 456be4f38e2SAlex Deucher 457be4f38e2SAlex Deucher if (idx == 0) 458be4f38e2SAlex Deucher mask |= SRBM_STATUS2__VCE0_BUSY_MASK; 459be4f38e2SAlex Deucher else 460be4f38e2SAlex Deucher mask |= SRBM_STATUS2__VCE1_BUSY_MASK; 461be4f38e2SAlex Deucher } 462aaa36a97SAlex Deucher 463aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 464be4f38e2SAlex Deucher if (!(RREG32(mmSRBM_STATUS2) & mask)) 465aaa36a97SAlex Deucher return 0; 466aaa36a97SAlex Deucher } 467aaa36a97SAlex Deucher return -ETIMEDOUT; 468aaa36a97SAlex Deucher } 469aaa36a97SAlex Deucher 4705fc3aeebSyanyang1 static int vce_v3_0_soft_reset(void *handle) 471aaa36a97SAlex Deucher { 4725fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 473be4f38e2SAlex Deucher u32 mask = 0; 474be4f38e2SAlex Deucher int idx; 4755fc3aeebSyanyang1 476be4f38e2SAlex Deucher for (idx = 0; idx < 2; ++idx) { 477be4f38e2SAlex Deucher if (adev->vce.harvest_config & (1 << idx)) 478be4f38e2SAlex Deucher continue; 479be4f38e2SAlex Deucher 480be4f38e2SAlex Deucher if (idx == 0) 481be4f38e2SAlex Deucher mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK; 482be4f38e2SAlex Deucher else 483be4f38e2SAlex Deucher mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK; 484be4f38e2SAlex Deucher } 485be4f38e2SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, mask, 486be4f38e2SAlex Deucher ~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK | 487be4f38e2SAlex Deucher SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK)); 488aaa36a97SAlex Deucher mdelay(5); 489aaa36a97SAlex Deucher 490aaa36a97SAlex Deucher return vce_v3_0_start(adev); 491aaa36a97SAlex Deucher } 492aaa36a97SAlex Deucher 4935fc3aeebSyanyang1 static void vce_v3_0_print_status(void *handle) 494aaa36a97SAlex Deucher { 4955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4965fc3aeebSyanyang1 497aaa36a97SAlex Deucher dev_info(adev->dev, "VCE 3.0 registers\n"); 498aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_STATUS=0x%08X\n", 499aaa36a97SAlex Deucher RREG32(mmVCE_STATUS)); 500aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", 501aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CNTL)); 502aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", 503aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_OFFSET0)); 504aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", 505aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_SIZE0)); 506aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", 507aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_OFFSET1)); 508aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", 509aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_SIZE1)); 510aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", 511aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_OFFSET2)); 512aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", 513aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_SIZE2)); 514aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", 515aaa36a97SAlex Deucher RREG32(mmVCE_SOFT_RESET)); 516aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", 517aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_LO2)); 518aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", 519aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_HI2)); 520aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", 521aaa36a97SAlex Deucher RREG32(mmVCE_RB_SIZE2)); 522aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", 523aaa36a97SAlex Deucher RREG32(mmVCE_RB_RPTR2)); 524aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", 525aaa36a97SAlex Deucher RREG32(mmVCE_RB_WPTR2)); 526aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", 527aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_LO)); 528aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", 529aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_HI)); 530aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", 531aaa36a97SAlex Deucher RREG32(mmVCE_RB_SIZE)); 532aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", 533aaa36a97SAlex Deucher RREG32(mmVCE_RB_RPTR)); 534aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", 535aaa36a97SAlex Deucher RREG32(mmVCE_RB_WPTR)); 536aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", 537aaa36a97SAlex Deucher RREG32(mmVCE_CLOCK_GATING_A)); 538aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", 539aaa36a97SAlex Deucher RREG32(mmVCE_CLOCK_GATING_B)); 540aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", 541aaa36a97SAlex Deucher RREG32(mmVCE_UENC_CLOCK_GATING)); 542aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", 543aaa36a97SAlex Deucher RREG32(mmVCE_UENC_REG_CLOCK_GATING)); 544aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", 545aaa36a97SAlex Deucher RREG32(mmVCE_SYS_INT_EN)); 546aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", 547aaa36a97SAlex Deucher RREG32(mmVCE_LMI_CTRL2)); 548aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", 549aaa36a97SAlex Deucher RREG32(mmVCE_LMI_CTRL)); 550aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", 551aaa36a97SAlex Deucher RREG32(mmVCE_LMI_VM_CTRL)); 552aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", 553aaa36a97SAlex Deucher RREG32(mmVCE_LMI_SWAP_CNTL)); 554aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", 555aaa36a97SAlex Deucher RREG32(mmVCE_LMI_SWAP_CNTL1)); 556aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", 557aaa36a97SAlex Deucher RREG32(mmVCE_LMI_CACHE_CTRL)); 558aaa36a97SAlex Deucher } 559aaa36a97SAlex Deucher 560aaa36a97SAlex Deucher static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, 561aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 562aaa36a97SAlex Deucher unsigned type, 563aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 564aaa36a97SAlex Deucher { 565aaa36a97SAlex Deucher uint32_t val = 0; 566aaa36a97SAlex Deucher 567aaa36a97SAlex Deucher if (state == AMDGPU_IRQ_STATE_ENABLE) 568aaa36a97SAlex Deucher val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; 569aaa36a97SAlex Deucher 570aaa36a97SAlex Deucher WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 571aaa36a97SAlex Deucher return 0; 572aaa36a97SAlex Deucher } 573aaa36a97SAlex Deucher 574aaa36a97SAlex Deucher static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, 575aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 576aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 577aaa36a97SAlex Deucher { 578aaa36a97SAlex Deucher DRM_DEBUG("IH: VCE\n"); 579aaa36a97SAlex Deucher switch (entry->src_data) { 580aaa36a97SAlex Deucher case 0: 581aaa36a97SAlex Deucher amdgpu_fence_process(&adev->vce.ring[0]); 582aaa36a97SAlex Deucher break; 583aaa36a97SAlex Deucher case 1: 584aaa36a97SAlex Deucher amdgpu_fence_process(&adev->vce.ring[1]); 585aaa36a97SAlex Deucher break; 586aaa36a97SAlex Deucher default: 587aaa36a97SAlex Deucher DRM_ERROR("Unhandled interrupt: %d %d\n", 588aaa36a97SAlex Deucher entry->src_id, entry->src_data); 589aaa36a97SAlex Deucher break; 590aaa36a97SAlex Deucher } 591aaa36a97SAlex Deucher 592aaa36a97SAlex Deucher return 0; 593aaa36a97SAlex Deucher } 594aaa36a97SAlex Deucher 5955fc3aeebSyanyang1 static int vce_v3_0_set_clockgating_state(void *handle, 5965fc3aeebSyanyang1 enum amd_clockgating_state state) 597aaa36a97SAlex Deucher { 598aaa36a97SAlex Deucher return 0; 599aaa36a97SAlex Deucher } 600aaa36a97SAlex Deucher 6015fc3aeebSyanyang1 static int vce_v3_0_set_powergating_state(void *handle, 6025fc3aeebSyanyang1 enum amd_powergating_state state) 603aaa36a97SAlex Deucher { 604aaa36a97SAlex Deucher /* This doesn't actually powergate the VCE block. 605aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 606aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 607aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 608aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 609aaa36a97SAlex Deucher * the smc and the hw blocks 610aaa36a97SAlex Deucher */ 6115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6125fc3aeebSyanyang1 6135fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) 614aaa36a97SAlex Deucher /* XXX do we need a vce_v3_0_stop()? */ 615aaa36a97SAlex Deucher return 0; 616aaa36a97SAlex Deucher else 617aaa36a97SAlex Deucher return vce_v3_0_start(adev); 618aaa36a97SAlex Deucher } 619aaa36a97SAlex Deucher 6205fc3aeebSyanyang1 const struct amd_ip_funcs vce_v3_0_ip_funcs = { 621aaa36a97SAlex Deucher .early_init = vce_v3_0_early_init, 622aaa36a97SAlex Deucher .late_init = NULL, 623aaa36a97SAlex Deucher .sw_init = vce_v3_0_sw_init, 624aaa36a97SAlex Deucher .sw_fini = vce_v3_0_sw_fini, 625aaa36a97SAlex Deucher .hw_init = vce_v3_0_hw_init, 626aaa36a97SAlex Deucher .hw_fini = vce_v3_0_hw_fini, 627aaa36a97SAlex Deucher .suspend = vce_v3_0_suspend, 628aaa36a97SAlex Deucher .resume = vce_v3_0_resume, 629aaa36a97SAlex Deucher .is_idle = vce_v3_0_is_idle, 630aaa36a97SAlex Deucher .wait_for_idle = vce_v3_0_wait_for_idle, 631aaa36a97SAlex Deucher .soft_reset = vce_v3_0_soft_reset, 632aaa36a97SAlex Deucher .print_status = vce_v3_0_print_status, 633aaa36a97SAlex Deucher .set_clockgating_state = vce_v3_0_set_clockgating_state, 634aaa36a97SAlex Deucher .set_powergating_state = vce_v3_0_set_powergating_state, 635aaa36a97SAlex Deucher }; 636aaa36a97SAlex Deucher 637aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = { 638aaa36a97SAlex Deucher .get_rptr = vce_v3_0_ring_get_rptr, 639aaa36a97SAlex Deucher .get_wptr = vce_v3_0_ring_get_wptr, 640aaa36a97SAlex Deucher .set_wptr = vce_v3_0_ring_set_wptr, 641aaa36a97SAlex Deucher .parse_cs = amdgpu_vce_ring_parse_cs, 642aaa36a97SAlex Deucher .emit_ib = amdgpu_vce_ring_emit_ib, 643aaa36a97SAlex Deucher .emit_fence = amdgpu_vce_ring_emit_fence, 644aaa36a97SAlex Deucher .emit_semaphore = amdgpu_vce_ring_emit_semaphore, 645aaa36a97SAlex Deucher .test_ring = amdgpu_vce_ring_test_ring, 646aaa36a97SAlex Deucher .test_ib = amdgpu_vce_ring_test_ib, 647edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 648aaa36a97SAlex Deucher }; 649aaa36a97SAlex Deucher 650aaa36a97SAlex Deucher static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) 651aaa36a97SAlex Deucher { 652aaa36a97SAlex Deucher adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs; 653aaa36a97SAlex Deucher adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs; 654aaa36a97SAlex Deucher } 655aaa36a97SAlex Deucher 656aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = { 657aaa36a97SAlex Deucher .set = vce_v3_0_set_interrupt_state, 658aaa36a97SAlex Deucher .process = vce_v3_0_process_interrupt, 659aaa36a97SAlex Deucher }; 660aaa36a97SAlex Deucher 661aaa36a97SAlex Deucher static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev) 662aaa36a97SAlex Deucher { 663aaa36a97SAlex Deucher adev->vce.irq.num_types = 1; 664aaa36a97SAlex Deucher adev->vce.irq.funcs = &vce_v3_0_irq_funcs; 665aaa36a97SAlex Deucher }; 666