1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * All Rights Reserved. 4aaa36a97SAlex Deucher * 5aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6aaa36a97SAlex Deucher * copy of this software and associated documentation files (the 7aaa36a97SAlex Deucher * "Software"), to deal in the Software without restriction, including 8aaa36a97SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9aaa36a97SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10aaa36a97SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11aaa36a97SAlex Deucher * the following conditions: 12aaa36a97SAlex Deucher * 13aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16aaa36a97SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17aaa36a97SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18aaa36a97SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19aaa36a97SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20aaa36a97SAlex Deucher * 21aaa36a97SAlex Deucher * The above copyright notice and this permission notice (including the 22aaa36a97SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23aaa36a97SAlex Deucher * of the Software. 24aaa36a97SAlex Deucher * 25aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 26aaa36a97SAlex Deucher */ 27aaa36a97SAlex Deucher 28aaa36a97SAlex Deucher #include <linux/firmware.h> 29aaa36a97SAlex Deucher #include <drm/drmP.h> 30aaa36a97SAlex Deucher #include "amdgpu.h" 31aaa36a97SAlex Deucher #include "amdgpu_vce.h" 32aaa36a97SAlex Deucher #include "vid.h" 33aaa36a97SAlex Deucher #include "vce/vce_3_0_d.h" 34aaa36a97SAlex Deucher #include "vce/vce_3_0_sh_mask.h" 35aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 36aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 375bbc553aSLeo Liu #include "gca/gfx_8_0_d.h" 386a585777SAlex Deucher #include "smu/smu_7_1_2_d.h" 396a585777SAlex Deucher #include "smu/smu_7_1_2_sh_mask.h" 405bbc553aSLeo Liu 415bbc553aSLeo Liu #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 425bbc553aSLeo Liu #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 43aaa36a97SAlex Deucher 44e9822622SLeo Liu #define VCE_V3_0_FW_SIZE (384 * 1024) 45e9822622SLeo Liu #define VCE_V3_0_STACK_SIZE (64 * 1024) 46e9822622SLeo Liu #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) 47e9822622SLeo Liu 485bbc553aSLeo Liu static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); 49aaa36a97SAlex Deucher static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); 50aaa36a97SAlex Deucher static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51aaa36a97SAlex Deucher 52aaa36a97SAlex Deucher /** 53aaa36a97SAlex Deucher * vce_v3_0_ring_get_rptr - get read pointer 54aaa36a97SAlex Deucher * 55aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 56aaa36a97SAlex Deucher * 57aaa36a97SAlex Deucher * Returns the current hardware read pointer 58aaa36a97SAlex Deucher */ 59aaa36a97SAlex Deucher static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 60aaa36a97SAlex Deucher { 61aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 62aaa36a97SAlex Deucher 63aaa36a97SAlex Deucher if (ring == &adev->vce.ring[0]) 64aaa36a97SAlex Deucher return RREG32(mmVCE_RB_RPTR); 65aaa36a97SAlex Deucher else 66aaa36a97SAlex Deucher return RREG32(mmVCE_RB_RPTR2); 67aaa36a97SAlex Deucher } 68aaa36a97SAlex Deucher 69aaa36a97SAlex Deucher /** 70aaa36a97SAlex Deucher * vce_v3_0_ring_get_wptr - get write pointer 71aaa36a97SAlex Deucher * 72aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 73aaa36a97SAlex Deucher * 74aaa36a97SAlex Deucher * Returns the current hardware write pointer 75aaa36a97SAlex Deucher */ 76aaa36a97SAlex Deucher static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 77aaa36a97SAlex Deucher { 78aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 79aaa36a97SAlex Deucher 80aaa36a97SAlex Deucher if (ring == &adev->vce.ring[0]) 81aaa36a97SAlex Deucher return RREG32(mmVCE_RB_WPTR); 82aaa36a97SAlex Deucher else 83aaa36a97SAlex Deucher return RREG32(mmVCE_RB_WPTR2); 84aaa36a97SAlex Deucher } 85aaa36a97SAlex Deucher 86aaa36a97SAlex Deucher /** 87aaa36a97SAlex Deucher * vce_v3_0_ring_set_wptr - set write pointer 88aaa36a97SAlex Deucher * 89aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 90aaa36a97SAlex Deucher * 91aaa36a97SAlex Deucher * Commits the write pointer to the hardware 92aaa36a97SAlex Deucher */ 93aaa36a97SAlex Deucher static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 94aaa36a97SAlex Deucher { 95aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 96aaa36a97SAlex Deucher 97aaa36a97SAlex Deucher if (ring == &adev->vce.ring[0]) 98aaa36a97SAlex Deucher WREG32(mmVCE_RB_WPTR, ring->wptr); 99aaa36a97SAlex Deucher else 100aaa36a97SAlex Deucher WREG32(mmVCE_RB_WPTR2, ring->wptr); 101aaa36a97SAlex Deucher } 102aaa36a97SAlex Deucher 103aaa36a97SAlex Deucher /** 104aaa36a97SAlex Deucher * vce_v3_0_start - start VCE block 105aaa36a97SAlex Deucher * 106aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 107aaa36a97SAlex Deucher * 108aaa36a97SAlex Deucher * Setup and start the VCE block 109aaa36a97SAlex Deucher */ 110aaa36a97SAlex Deucher static int vce_v3_0_start(struct amdgpu_device *adev) 111aaa36a97SAlex Deucher { 112aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1135bbc553aSLeo Liu int idx, i, j, r; 114aaa36a97SAlex Deucher 1155bbc553aSLeo Liu mutex_lock(&adev->grbm_idx_mutex); 1165bbc553aSLeo Liu for (idx = 0; idx < 2; ++idx) { 1176a585777SAlex Deucher 1186a585777SAlex Deucher if (adev->vce.harvest_config & (1 << idx)) 1196a585777SAlex Deucher continue; 1206a585777SAlex Deucher 1215bbc553aSLeo Liu if(idx == 0) 1225bbc553aSLeo Liu WREG32_P(mmGRBM_GFX_INDEX, 0, 1235bbc553aSLeo Liu ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 1245bbc553aSLeo Liu else 1255bbc553aSLeo Liu WREG32_P(mmGRBM_GFX_INDEX, 1265bbc553aSLeo Liu GRBM_GFX_INDEX__VCE_INSTANCE_MASK, 1275bbc553aSLeo Liu ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 1285bbc553aSLeo Liu 1295bbc553aSLeo Liu vce_v3_0_mc_resume(adev, idx); 130aaa36a97SAlex Deucher 131aaa36a97SAlex Deucher /* set BUSY flag */ 132aaa36a97SAlex Deucher WREG32_P(mmVCE_STATUS, 1, ~1); 133aaa36a97SAlex Deucher 1345bbc553aSLeo Liu WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, 1355bbc553aSLeo Liu ~VCE_VCPU_CNTL__CLK_EN_MASK); 136aaa36a97SAlex Deucher 137aaa36a97SAlex Deucher WREG32_P(mmVCE_SOFT_RESET, 138aaa36a97SAlex Deucher VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 139aaa36a97SAlex Deucher ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 140aaa36a97SAlex Deucher 141aaa36a97SAlex Deucher mdelay(100); 142aaa36a97SAlex Deucher 1435bbc553aSLeo Liu WREG32_P(mmVCE_SOFT_RESET, 0, 1445bbc553aSLeo Liu ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 145aaa36a97SAlex Deucher 146aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 147aaa36a97SAlex Deucher uint32_t status; 148aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 149aaa36a97SAlex Deucher status = RREG32(mmVCE_STATUS); 150aaa36a97SAlex Deucher if (status & 2) 151aaa36a97SAlex Deucher break; 152aaa36a97SAlex Deucher mdelay(10); 153aaa36a97SAlex Deucher } 154aaa36a97SAlex Deucher r = 0; 155aaa36a97SAlex Deucher if (status & 2) 156aaa36a97SAlex Deucher break; 157aaa36a97SAlex Deucher 158aaa36a97SAlex Deucher DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); 1595bbc553aSLeo Liu WREG32_P(mmVCE_SOFT_RESET, 1605bbc553aSLeo Liu VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 161aaa36a97SAlex Deucher ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 162aaa36a97SAlex Deucher mdelay(10); 1635bbc553aSLeo Liu WREG32_P(mmVCE_SOFT_RESET, 0, 1645bbc553aSLeo Liu ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 165aaa36a97SAlex Deucher mdelay(10); 166aaa36a97SAlex Deucher r = -1; 167aaa36a97SAlex Deucher } 168aaa36a97SAlex Deucher 169aaa36a97SAlex Deucher /* clear BUSY flag */ 170aaa36a97SAlex Deucher WREG32_P(mmVCE_STATUS, 0, ~1); 171aaa36a97SAlex Deucher 172aaa36a97SAlex Deucher if (r) { 173aaa36a97SAlex Deucher DRM_ERROR("VCE not responding, giving up!!!\n"); 1745bbc553aSLeo Liu mutex_unlock(&adev->grbm_idx_mutex); 175aaa36a97SAlex Deucher return r; 176aaa36a97SAlex Deucher } 1775bbc553aSLeo Liu } 1785bbc553aSLeo Liu 1795bbc553aSLeo Liu WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 1805bbc553aSLeo Liu mutex_unlock(&adev->grbm_idx_mutex); 1815bbc553aSLeo Liu 1825bbc553aSLeo Liu ring = &adev->vce.ring[0]; 1835bbc553aSLeo Liu WREG32(mmVCE_RB_RPTR, ring->wptr); 1845bbc553aSLeo Liu WREG32(mmVCE_RB_WPTR, ring->wptr); 1855bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); 1865bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1875bbc553aSLeo Liu WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); 1885bbc553aSLeo Liu 1895bbc553aSLeo Liu ring = &adev->vce.ring[1]; 1905bbc553aSLeo Liu WREG32(mmVCE_RB_RPTR2, ring->wptr); 1915bbc553aSLeo Liu WREG32(mmVCE_RB_WPTR2, ring->wptr); 1925bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); 1935bbc553aSLeo Liu WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1945bbc553aSLeo Liu WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); 195aaa36a97SAlex Deucher 196aaa36a97SAlex Deucher return 0; 197aaa36a97SAlex Deucher } 198aaa36a97SAlex Deucher 1996a585777SAlex Deucher #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074 2006a585777SAlex Deucher #define VCE_HARVEST_FUSE_MACRO__SHIFT 27 2016a585777SAlex Deucher #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000 2026a585777SAlex Deucher 2036a585777SAlex Deucher static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) 2046a585777SAlex Deucher { 2056a585777SAlex Deucher u32 tmp; 2066a585777SAlex Deucher unsigned ret; 2076a585777SAlex Deucher 2082f7d10b3SJammy Zhou if (adev->flags & AMD_IS_APU) 2096a585777SAlex Deucher tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & 2106a585777SAlex Deucher VCE_HARVEST_FUSE_MACRO__MASK) >> 2116a585777SAlex Deucher VCE_HARVEST_FUSE_MACRO__SHIFT; 2126a585777SAlex Deucher else 2136a585777SAlex Deucher tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & 2146a585777SAlex Deucher CC_HARVEST_FUSES__VCE_DISABLE_MASK) >> 2156a585777SAlex Deucher CC_HARVEST_FUSES__VCE_DISABLE__SHIFT; 2166a585777SAlex Deucher 2176a585777SAlex Deucher switch (tmp) { 2186a585777SAlex Deucher case 1: 2196a585777SAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE0; 2206a585777SAlex Deucher break; 2216a585777SAlex Deucher case 2: 2226a585777SAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE1; 2236a585777SAlex Deucher break; 2246a585777SAlex Deucher case 3: 2256a585777SAlex Deucher ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1; 2266a585777SAlex Deucher break; 2276a585777SAlex Deucher default: 2286a585777SAlex Deucher ret = 0; 2296a585777SAlex Deucher } 2306a585777SAlex Deucher 2316a585777SAlex Deucher return ret; 2326a585777SAlex Deucher } 2336a585777SAlex Deucher 2345fc3aeebSyanyang1 static int vce_v3_0_early_init(void *handle) 235aaa36a97SAlex Deucher { 2365fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2375fc3aeebSyanyang1 2386a585777SAlex Deucher adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); 2396a585777SAlex Deucher 2406a585777SAlex Deucher if ((adev->vce.harvest_config & 2416a585777SAlex Deucher (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) == 2426a585777SAlex Deucher (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) 2436a585777SAlex Deucher return -ENOENT; 2446a585777SAlex Deucher 245aaa36a97SAlex Deucher vce_v3_0_set_ring_funcs(adev); 246aaa36a97SAlex Deucher vce_v3_0_set_irq_funcs(adev); 247aaa36a97SAlex Deucher 248aaa36a97SAlex Deucher return 0; 249aaa36a97SAlex Deucher } 250aaa36a97SAlex Deucher 2515fc3aeebSyanyang1 static int vce_v3_0_sw_init(void *handle) 252aaa36a97SAlex Deucher { 2535fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 254aaa36a97SAlex Deucher struct amdgpu_ring *ring; 255aaa36a97SAlex Deucher int r; 256aaa36a97SAlex Deucher 257aaa36a97SAlex Deucher /* VCE */ 258aaa36a97SAlex Deucher r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); 259aaa36a97SAlex Deucher if (r) 260aaa36a97SAlex Deucher return r; 261aaa36a97SAlex Deucher 262e9822622SLeo Liu r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + 263e9822622SLeo Liu (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); 264aaa36a97SAlex Deucher if (r) 265aaa36a97SAlex Deucher return r; 266aaa36a97SAlex Deucher 267aaa36a97SAlex Deucher r = amdgpu_vce_resume(adev); 268aaa36a97SAlex Deucher if (r) 269aaa36a97SAlex Deucher return r; 270aaa36a97SAlex Deucher 271aaa36a97SAlex Deucher ring = &adev->vce.ring[0]; 272aaa36a97SAlex Deucher sprintf(ring->name, "vce0"); 273aaa36a97SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, 274aaa36a97SAlex Deucher &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); 275aaa36a97SAlex Deucher if (r) 276aaa36a97SAlex Deucher return r; 277aaa36a97SAlex Deucher 278aaa36a97SAlex Deucher ring = &adev->vce.ring[1]; 279aaa36a97SAlex Deucher sprintf(ring->name, "vce1"); 280aaa36a97SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, 281aaa36a97SAlex Deucher &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); 282aaa36a97SAlex Deucher if (r) 283aaa36a97SAlex Deucher return r; 284aaa36a97SAlex Deucher 285aaa36a97SAlex Deucher return r; 286aaa36a97SAlex Deucher } 287aaa36a97SAlex Deucher 2885fc3aeebSyanyang1 static int vce_v3_0_sw_fini(void *handle) 289aaa36a97SAlex Deucher { 290aaa36a97SAlex Deucher int r; 2915fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 292aaa36a97SAlex Deucher 293aaa36a97SAlex Deucher r = amdgpu_vce_suspend(adev); 294aaa36a97SAlex Deucher if (r) 295aaa36a97SAlex Deucher return r; 296aaa36a97SAlex Deucher 297aaa36a97SAlex Deucher r = amdgpu_vce_sw_fini(adev); 298aaa36a97SAlex Deucher if (r) 299aaa36a97SAlex Deucher return r; 300aaa36a97SAlex Deucher 301aaa36a97SAlex Deucher return r; 302aaa36a97SAlex Deucher } 303aaa36a97SAlex Deucher 3045fc3aeebSyanyang1 static int vce_v3_0_hw_init(void *handle) 305aaa36a97SAlex Deucher { 306aaa36a97SAlex Deucher struct amdgpu_ring *ring; 307aaa36a97SAlex Deucher int r; 3085fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 309aaa36a97SAlex Deucher 310aaa36a97SAlex Deucher r = vce_v3_0_start(adev); 311aaa36a97SAlex Deucher if (r) 312aaa36a97SAlex Deucher return r; 313aaa36a97SAlex Deucher 314aaa36a97SAlex Deucher ring = &adev->vce.ring[0]; 315aaa36a97SAlex Deucher ring->ready = true; 316aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 317aaa36a97SAlex Deucher if (r) { 318aaa36a97SAlex Deucher ring->ready = false; 319aaa36a97SAlex Deucher return r; 320aaa36a97SAlex Deucher } 321aaa36a97SAlex Deucher 322aaa36a97SAlex Deucher ring = &adev->vce.ring[1]; 323aaa36a97SAlex Deucher ring->ready = true; 324aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 325aaa36a97SAlex Deucher if (r) { 326aaa36a97SAlex Deucher ring->ready = false; 327aaa36a97SAlex Deucher return r; 328aaa36a97SAlex Deucher } 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher DRM_INFO("VCE initialized successfully.\n"); 331aaa36a97SAlex Deucher 332aaa36a97SAlex Deucher return 0; 333aaa36a97SAlex Deucher } 334aaa36a97SAlex Deucher 3355fc3aeebSyanyang1 static int vce_v3_0_hw_fini(void *handle) 336aaa36a97SAlex Deucher { 337aaa36a97SAlex Deucher return 0; 338aaa36a97SAlex Deucher } 339aaa36a97SAlex Deucher 3405fc3aeebSyanyang1 static int vce_v3_0_suspend(void *handle) 341aaa36a97SAlex Deucher { 342aaa36a97SAlex Deucher int r; 3435fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 344aaa36a97SAlex Deucher 345aaa36a97SAlex Deucher r = vce_v3_0_hw_fini(adev); 346aaa36a97SAlex Deucher if (r) 347aaa36a97SAlex Deucher return r; 348aaa36a97SAlex Deucher 349aaa36a97SAlex Deucher r = amdgpu_vce_suspend(adev); 350aaa36a97SAlex Deucher if (r) 351aaa36a97SAlex Deucher return r; 352aaa36a97SAlex Deucher 353aaa36a97SAlex Deucher return r; 354aaa36a97SAlex Deucher } 355aaa36a97SAlex Deucher 3565fc3aeebSyanyang1 static int vce_v3_0_resume(void *handle) 357aaa36a97SAlex Deucher { 358aaa36a97SAlex Deucher int r; 3595fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 360aaa36a97SAlex Deucher 361aaa36a97SAlex Deucher r = amdgpu_vce_resume(adev); 362aaa36a97SAlex Deucher if (r) 363aaa36a97SAlex Deucher return r; 364aaa36a97SAlex Deucher 365aaa36a97SAlex Deucher r = vce_v3_0_hw_init(adev); 366aaa36a97SAlex Deucher if (r) 367aaa36a97SAlex Deucher return r; 368aaa36a97SAlex Deucher 369aaa36a97SAlex Deucher return r; 370aaa36a97SAlex Deucher } 371aaa36a97SAlex Deucher 3725bbc553aSLeo Liu static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) 373aaa36a97SAlex Deucher { 374aaa36a97SAlex Deucher uint32_t offset, size; 375aaa36a97SAlex Deucher 376aaa36a97SAlex Deucher WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); 377aaa36a97SAlex Deucher WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); 378aaa36a97SAlex Deucher WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); 379aaa36a97SAlex Deucher WREG32(mmVCE_CLOCK_GATING_B, 0xf7); 380aaa36a97SAlex Deucher 381aaa36a97SAlex Deucher WREG32(mmVCE_LMI_CTRL, 0x00398000); 382aaa36a97SAlex Deucher WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); 383aaa36a97SAlex Deucher WREG32(mmVCE_LMI_SWAP_CNTL, 0); 384aaa36a97SAlex Deucher WREG32(mmVCE_LMI_SWAP_CNTL1, 0); 385aaa36a97SAlex Deucher WREG32(mmVCE_LMI_VM_CTRL, 0); 386aaa36a97SAlex Deucher 387aaa36a97SAlex Deucher WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); 388aaa36a97SAlex Deucher offset = AMDGPU_VCE_FIRMWARE_OFFSET; 389e9822622SLeo Liu size = VCE_V3_0_FW_SIZE; 390aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); 391aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_SIZE0, size); 392aaa36a97SAlex Deucher 3935bbc553aSLeo Liu if (idx == 0) { 394aaa36a97SAlex Deucher offset += size; 395e9822622SLeo Liu size = VCE_V3_0_STACK_SIZE; 396aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); 397aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_SIZE1, size); 398aaa36a97SAlex Deucher offset += size; 399e9822622SLeo Liu size = VCE_V3_0_DATA_SIZE; 400aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); 401aaa36a97SAlex Deucher WREG32(mmVCE_VCPU_CACHE_SIZE2, size); 4025bbc553aSLeo Liu } else { 4035bbc553aSLeo Liu offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE; 4045bbc553aSLeo Liu size = VCE_V3_0_STACK_SIZE; 4055bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff); 4065bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_SIZE1, size); 4075bbc553aSLeo Liu offset += size; 4085bbc553aSLeo Liu size = VCE_V3_0_DATA_SIZE; 4095bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff); 4105bbc553aSLeo Liu WREG32(mmVCE_VCPU_CACHE_SIZE2, size); 4115bbc553aSLeo Liu } 412aaa36a97SAlex Deucher 413aaa36a97SAlex Deucher WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); 414aaa36a97SAlex Deucher 415aaa36a97SAlex Deucher WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK, 416aaa36a97SAlex Deucher ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 417aaa36a97SAlex Deucher } 418aaa36a97SAlex Deucher 4195fc3aeebSyanyang1 static bool vce_v3_0_is_idle(void *handle) 420aaa36a97SAlex Deucher { 4215fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4225fc3aeebSyanyang1 423aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); 424aaa36a97SAlex Deucher } 425aaa36a97SAlex Deucher 4265fc3aeebSyanyang1 static int vce_v3_0_wait_for_idle(void *handle) 427aaa36a97SAlex Deucher { 428aaa36a97SAlex Deucher unsigned i; 4295fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 430aaa36a97SAlex Deucher 431aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 432aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) 433aaa36a97SAlex Deucher return 0; 434aaa36a97SAlex Deucher } 435aaa36a97SAlex Deucher return -ETIMEDOUT; 436aaa36a97SAlex Deucher } 437aaa36a97SAlex Deucher 4385fc3aeebSyanyang1 static int vce_v3_0_soft_reset(void *handle) 439aaa36a97SAlex Deucher { 4405fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4415fc3aeebSyanyang1 442aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, 443aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); 444aaa36a97SAlex Deucher mdelay(5); 445aaa36a97SAlex Deucher 446aaa36a97SAlex Deucher return vce_v3_0_start(adev); 447aaa36a97SAlex Deucher } 448aaa36a97SAlex Deucher 4495fc3aeebSyanyang1 static void vce_v3_0_print_status(void *handle) 450aaa36a97SAlex Deucher { 4515fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4525fc3aeebSyanyang1 453aaa36a97SAlex Deucher dev_info(adev->dev, "VCE 3.0 registers\n"); 454aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_STATUS=0x%08X\n", 455aaa36a97SAlex Deucher RREG32(mmVCE_STATUS)); 456aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", 457aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CNTL)); 458aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", 459aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_OFFSET0)); 460aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", 461aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_SIZE0)); 462aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", 463aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_OFFSET1)); 464aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", 465aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_SIZE1)); 466aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", 467aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_OFFSET2)); 468aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", 469aaa36a97SAlex Deucher RREG32(mmVCE_VCPU_CACHE_SIZE2)); 470aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", 471aaa36a97SAlex Deucher RREG32(mmVCE_SOFT_RESET)); 472aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", 473aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_LO2)); 474aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", 475aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_HI2)); 476aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", 477aaa36a97SAlex Deucher RREG32(mmVCE_RB_SIZE2)); 478aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", 479aaa36a97SAlex Deucher RREG32(mmVCE_RB_RPTR2)); 480aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", 481aaa36a97SAlex Deucher RREG32(mmVCE_RB_WPTR2)); 482aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", 483aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_LO)); 484aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", 485aaa36a97SAlex Deucher RREG32(mmVCE_RB_BASE_HI)); 486aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", 487aaa36a97SAlex Deucher RREG32(mmVCE_RB_SIZE)); 488aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", 489aaa36a97SAlex Deucher RREG32(mmVCE_RB_RPTR)); 490aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", 491aaa36a97SAlex Deucher RREG32(mmVCE_RB_WPTR)); 492aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", 493aaa36a97SAlex Deucher RREG32(mmVCE_CLOCK_GATING_A)); 494aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", 495aaa36a97SAlex Deucher RREG32(mmVCE_CLOCK_GATING_B)); 496aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", 497aaa36a97SAlex Deucher RREG32(mmVCE_UENC_CLOCK_GATING)); 498aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", 499aaa36a97SAlex Deucher RREG32(mmVCE_UENC_REG_CLOCK_GATING)); 500aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", 501aaa36a97SAlex Deucher RREG32(mmVCE_SYS_INT_EN)); 502aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", 503aaa36a97SAlex Deucher RREG32(mmVCE_LMI_CTRL2)); 504aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", 505aaa36a97SAlex Deucher RREG32(mmVCE_LMI_CTRL)); 506aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", 507aaa36a97SAlex Deucher RREG32(mmVCE_LMI_VM_CTRL)); 508aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", 509aaa36a97SAlex Deucher RREG32(mmVCE_LMI_SWAP_CNTL)); 510aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", 511aaa36a97SAlex Deucher RREG32(mmVCE_LMI_SWAP_CNTL1)); 512aaa36a97SAlex Deucher dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", 513aaa36a97SAlex Deucher RREG32(mmVCE_LMI_CACHE_CTRL)); 514aaa36a97SAlex Deucher } 515aaa36a97SAlex Deucher 516aaa36a97SAlex Deucher static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, 517aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 518aaa36a97SAlex Deucher unsigned type, 519aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 520aaa36a97SAlex Deucher { 521aaa36a97SAlex Deucher uint32_t val = 0; 522aaa36a97SAlex Deucher 523aaa36a97SAlex Deucher if (state == AMDGPU_IRQ_STATE_ENABLE) 524aaa36a97SAlex Deucher val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; 525aaa36a97SAlex Deucher 526aaa36a97SAlex Deucher WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 527aaa36a97SAlex Deucher return 0; 528aaa36a97SAlex Deucher } 529aaa36a97SAlex Deucher 530aaa36a97SAlex Deucher static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, 531aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 532aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 533aaa36a97SAlex Deucher { 534aaa36a97SAlex Deucher DRM_DEBUG("IH: VCE\n"); 535aaa36a97SAlex Deucher switch (entry->src_data) { 536aaa36a97SAlex Deucher case 0: 537aaa36a97SAlex Deucher amdgpu_fence_process(&adev->vce.ring[0]); 538aaa36a97SAlex Deucher break; 539aaa36a97SAlex Deucher case 1: 540aaa36a97SAlex Deucher amdgpu_fence_process(&adev->vce.ring[1]); 541aaa36a97SAlex Deucher break; 542aaa36a97SAlex Deucher default: 543aaa36a97SAlex Deucher DRM_ERROR("Unhandled interrupt: %d %d\n", 544aaa36a97SAlex Deucher entry->src_id, entry->src_data); 545aaa36a97SAlex Deucher break; 546aaa36a97SAlex Deucher } 547aaa36a97SAlex Deucher 548aaa36a97SAlex Deucher return 0; 549aaa36a97SAlex Deucher } 550aaa36a97SAlex Deucher 5515fc3aeebSyanyang1 static int vce_v3_0_set_clockgating_state(void *handle, 5525fc3aeebSyanyang1 enum amd_clockgating_state state) 553aaa36a97SAlex Deucher { 554aaa36a97SAlex Deucher return 0; 555aaa36a97SAlex Deucher } 556aaa36a97SAlex Deucher 5575fc3aeebSyanyang1 static int vce_v3_0_set_powergating_state(void *handle, 5585fc3aeebSyanyang1 enum amd_powergating_state state) 559aaa36a97SAlex Deucher { 560aaa36a97SAlex Deucher /* This doesn't actually powergate the VCE block. 561aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 562aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 563aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 564aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 565aaa36a97SAlex Deucher * the smc and the hw blocks 566aaa36a97SAlex Deucher */ 5675fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5685fc3aeebSyanyang1 5695fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) 570aaa36a97SAlex Deucher /* XXX do we need a vce_v3_0_stop()? */ 571aaa36a97SAlex Deucher return 0; 572aaa36a97SAlex Deucher else 573aaa36a97SAlex Deucher return vce_v3_0_start(adev); 574aaa36a97SAlex Deucher } 575aaa36a97SAlex Deucher 5765fc3aeebSyanyang1 const struct amd_ip_funcs vce_v3_0_ip_funcs = { 577aaa36a97SAlex Deucher .early_init = vce_v3_0_early_init, 578aaa36a97SAlex Deucher .late_init = NULL, 579aaa36a97SAlex Deucher .sw_init = vce_v3_0_sw_init, 580aaa36a97SAlex Deucher .sw_fini = vce_v3_0_sw_fini, 581aaa36a97SAlex Deucher .hw_init = vce_v3_0_hw_init, 582aaa36a97SAlex Deucher .hw_fini = vce_v3_0_hw_fini, 583aaa36a97SAlex Deucher .suspend = vce_v3_0_suspend, 584aaa36a97SAlex Deucher .resume = vce_v3_0_resume, 585aaa36a97SAlex Deucher .is_idle = vce_v3_0_is_idle, 586aaa36a97SAlex Deucher .wait_for_idle = vce_v3_0_wait_for_idle, 587aaa36a97SAlex Deucher .soft_reset = vce_v3_0_soft_reset, 588aaa36a97SAlex Deucher .print_status = vce_v3_0_print_status, 589aaa36a97SAlex Deucher .set_clockgating_state = vce_v3_0_set_clockgating_state, 590aaa36a97SAlex Deucher .set_powergating_state = vce_v3_0_set_powergating_state, 591aaa36a97SAlex Deucher }; 592aaa36a97SAlex Deucher 593aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = { 594aaa36a97SAlex Deucher .get_rptr = vce_v3_0_ring_get_rptr, 595aaa36a97SAlex Deucher .get_wptr = vce_v3_0_ring_get_wptr, 596aaa36a97SAlex Deucher .set_wptr = vce_v3_0_ring_set_wptr, 597aaa36a97SAlex Deucher .parse_cs = amdgpu_vce_ring_parse_cs, 598aaa36a97SAlex Deucher .emit_ib = amdgpu_vce_ring_emit_ib, 599aaa36a97SAlex Deucher .emit_fence = amdgpu_vce_ring_emit_fence, 600aaa36a97SAlex Deucher .emit_semaphore = amdgpu_vce_ring_emit_semaphore, 601aaa36a97SAlex Deucher .test_ring = amdgpu_vce_ring_test_ring, 602aaa36a97SAlex Deucher .test_ib = amdgpu_vce_ring_test_ib, 603aaa36a97SAlex Deucher .is_lockup = amdgpu_ring_test_lockup, 604aaa36a97SAlex Deucher }; 605aaa36a97SAlex Deucher 606aaa36a97SAlex Deucher static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) 607aaa36a97SAlex Deucher { 608aaa36a97SAlex Deucher adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs; 609aaa36a97SAlex Deucher adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs; 610aaa36a97SAlex Deucher } 611aaa36a97SAlex Deucher 612aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = { 613aaa36a97SAlex Deucher .set = vce_v3_0_set_interrupt_state, 614aaa36a97SAlex Deucher .process = vce_v3_0_process_interrupt, 615aaa36a97SAlex Deucher }; 616aaa36a97SAlex Deucher 617aaa36a97SAlex Deucher static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev) 618aaa36a97SAlex Deucher { 619aaa36a97SAlex Deucher adev->vce.irq.num_types = 1; 620aaa36a97SAlex Deucher adev->vce.irq.funcs = &vce_v3_0_irq_funcs; 621aaa36a97SAlex Deucher }; 622