1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_uvd.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 #include "mmsch_v1_0.h" 32 33 #include "uvd/uvd_7_0_offset.h" 34 #include "uvd/uvd_7_0_sh_mask.h" 35 #include "vce/vce_4_0_offset.h" 36 #include "vce/vce_4_0_default.h" 37 #include "vce/vce_4_0_sh_mask.h" 38 #include "nbif/nbif_6_1_offset.h" 39 #include "hdp/hdp_4_0_offset.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "mmhub/mmhub_1_0_sh_mask.h" 42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 43 44 #define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 46 //UVD_PG0_CC_UVD_HARVESTING 47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 49 50 #define UVD7_MAX_HW_INSTANCES_VEGA20 2 51 52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int uvd_v7_0_start(struct amdgpu_device *adev); 56 static void uvd_v7_0_stop(struct amdgpu_device *adev); 57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 58 59 static int amdgpu_ih_clientid_uvds[] = { 60 SOC15_IH_CLIENTID_UVD, 61 SOC15_IH_CLIENTID_UVD1 62 }; 63 64 /** 65 * uvd_v7_0_ring_get_rptr - get read pointer 66 * 67 * @ring: amdgpu_ring pointer 68 * 69 * Returns the current hardware read pointer 70 */ 71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 72 { 73 struct amdgpu_device *adev = ring->adev; 74 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 76 } 77 78 /** 79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 80 * 81 * @ring: amdgpu_ring pointer 82 * 83 * Returns the current hardware enc read pointer 84 */ 85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 86 { 87 struct amdgpu_device *adev = ring->adev; 88 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 91 else 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 93 } 94 95 /** 96 * uvd_v7_0_ring_get_wptr - get write pointer 97 * 98 * @ring: amdgpu_ring pointer 99 * 100 * Returns the current hardware write pointer 101 */ 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 103 { 104 struct amdgpu_device *adev = ring->adev; 105 106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 107 } 108 109 /** 110 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 111 * 112 * @ring: amdgpu_ring pointer 113 * 114 * Returns the current hardware enc write pointer 115 */ 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 117 { 118 struct amdgpu_device *adev = ring->adev; 119 120 if (ring->use_doorbell) 121 return adev->wb.wb[ring->wptr_offs]; 122 123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 125 else 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 127 } 128 129 /** 130 * uvd_v7_0_ring_set_wptr - set write pointer 131 * 132 * @ring: amdgpu_ring pointer 133 * 134 * Commits the write pointer to the hardware 135 */ 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 137 { 138 struct amdgpu_device *adev = ring->adev; 139 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 141 } 142 143 /** 144 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 145 * 146 * @ring: amdgpu_ring pointer 147 * 148 * Commits the enc write pointer to the hardware 149 */ 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 151 { 152 struct amdgpu_device *adev = ring->adev; 153 154 if (ring->use_doorbell) { 155 /* XXX check if swapping is necessary on BE */ 156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 158 return; 159 } 160 161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 163 lower_32_bits(ring->wptr)); 164 else 165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 166 lower_32_bits(ring->wptr)); 167 } 168 169 /** 170 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 171 * 172 * @ring: the engine to test on 173 * 174 */ 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 176 { 177 struct amdgpu_device *adev = ring->adev; 178 uint32_t rptr = amdgpu_ring_get_rptr(ring); 179 unsigned i; 180 int r; 181 182 if (amdgpu_sriov_vf(adev)) 183 return 0; 184 185 r = amdgpu_ring_alloc(ring, 16); 186 if (r) { 187 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n", 188 ring->me, ring->idx, r); 189 return r; 190 } 191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 192 amdgpu_ring_commit(ring); 193 194 for (i = 0; i < adev->usec_timeout; i++) { 195 if (amdgpu_ring_get_rptr(ring) != rptr) 196 break; 197 DRM_UDELAY(1); 198 } 199 200 if (i < adev->usec_timeout) { 201 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n", 202 ring->me, ring->idx, i); 203 } else { 204 DRM_ERROR("amdgpu: (%d)ring %d test failed\n", 205 ring->me, ring->idx); 206 r = -ETIMEDOUT; 207 } 208 209 return r; 210 } 211 212 /** 213 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 214 * 215 * @adev: amdgpu_device pointer 216 * @ring: ring we should submit the msg to 217 * @handle: session handle to use 218 * @fence: optional fence to return 219 * 220 * Open up a stream for HW test 221 */ 222 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 223 struct dma_fence **fence) 224 { 225 const unsigned ib_size_dw = 16; 226 struct amdgpu_job *job; 227 struct amdgpu_ib *ib; 228 struct dma_fence *f = NULL; 229 uint64_t dummy; 230 int i, r; 231 232 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 233 if (r) 234 return r; 235 236 ib = &job->ibs[0]; 237 dummy = ib->gpu_addr + 1024; 238 239 ib->length_dw = 0; 240 ib->ptr[ib->length_dw++] = 0x00000018; 241 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 242 ib->ptr[ib->length_dw++] = handle; 243 ib->ptr[ib->length_dw++] = 0x00000000; 244 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 245 ib->ptr[ib->length_dw++] = dummy; 246 247 ib->ptr[ib->length_dw++] = 0x00000014; 248 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 249 ib->ptr[ib->length_dw++] = 0x0000001c; 250 ib->ptr[ib->length_dw++] = 0x00000000; 251 ib->ptr[ib->length_dw++] = 0x00000000; 252 253 ib->ptr[ib->length_dw++] = 0x00000008; 254 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 255 256 for (i = ib->length_dw; i < ib_size_dw; ++i) 257 ib->ptr[i] = 0x0; 258 259 r = amdgpu_job_submit_direct(job, ring, &f); 260 if (r) 261 goto err; 262 263 if (fence) 264 *fence = dma_fence_get(f); 265 dma_fence_put(f); 266 return 0; 267 268 err: 269 amdgpu_job_free(job); 270 return r; 271 } 272 273 /** 274 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 275 * 276 * @adev: amdgpu_device pointer 277 * @ring: ring we should submit the msg to 278 * @handle: session handle to use 279 * @fence: optional fence to return 280 * 281 * Close up a stream for HW test or if userspace failed to do so 282 */ 283 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 284 bool direct, struct dma_fence **fence) 285 { 286 const unsigned ib_size_dw = 16; 287 struct amdgpu_job *job; 288 struct amdgpu_ib *ib; 289 struct dma_fence *f = NULL; 290 uint64_t dummy; 291 int i, r; 292 293 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 294 if (r) 295 return r; 296 297 ib = &job->ibs[0]; 298 dummy = ib->gpu_addr + 1024; 299 300 ib->length_dw = 0; 301 ib->ptr[ib->length_dw++] = 0x00000018; 302 ib->ptr[ib->length_dw++] = 0x00000001; 303 ib->ptr[ib->length_dw++] = handle; 304 ib->ptr[ib->length_dw++] = 0x00000000; 305 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 306 ib->ptr[ib->length_dw++] = dummy; 307 308 ib->ptr[ib->length_dw++] = 0x00000014; 309 ib->ptr[ib->length_dw++] = 0x00000002; 310 ib->ptr[ib->length_dw++] = 0x0000001c; 311 ib->ptr[ib->length_dw++] = 0x00000000; 312 ib->ptr[ib->length_dw++] = 0x00000000; 313 314 ib->ptr[ib->length_dw++] = 0x00000008; 315 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 316 317 for (i = ib->length_dw; i < ib_size_dw; ++i) 318 ib->ptr[i] = 0x0; 319 320 if (direct) 321 r = amdgpu_job_submit_direct(job, ring, &f); 322 else 323 r = amdgpu_job_submit(job, &ring->adev->vce.entity, 324 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 325 if (r) 326 goto err; 327 328 if (fence) 329 *fence = dma_fence_get(f); 330 dma_fence_put(f); 331 return 0; 332 333 err: 334 amdgpu_job_free(job); 335 return r; 336 } 337 338 /** 339 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 340 * 341 * @ring: the engine to test on 342 * 343 */ 344 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 345 { 346 struct dma_fence *fence = NULL; 347 long r; 348 349 r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL); 350 if (r) { 351 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r); 352 goto error; 353 } 354 355 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence); 356 if (r) { 357 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r); 358 goto error; 359 } 360 361 r = dma_fence_wait_timeout(fence, false, timeout); 362 if (r == 0) { 363 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me); 364 r = -ETIMEDOUT; 365 } else if (r < 0) { 366 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r); 367 } else { 368 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx); 369 r = 0; 370 } 371 error: 372 dma_fence_put(fence); 373 return r; 374 } 375 376 static int uvd_v7_0_early_init(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 380 if (adev->asic_type == CHIP_VEGA20) { 381 u32 harvest; 382 int i; 383 384 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 385 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 386 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 387 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 388 adev->uvd.harvest_config |= 1 << i; 389 } 390 } 391 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 392 AMDGPU_UVD_HARVEST_UVD1)) 393 /* both instances are harvested, disable the block */ 394 return -ENOENT; 395 } else { 396 adev->uvd.num_uvd_inst = 1; 397 } 398 399 if (amdgpu_sriov_vf(adev)) 400 adev->uvd.num_enc_rings = 1; 401 else 402 adev->uvd.num_enc_rings = 2; 403 uvd_v7_0_set_ring_funcs(adev); 404 uvd_v7_0_set_enc_ring_funcs(adev); 405 uvd_v7_0_set_irq_funcs(adev); 406 407 return 0; 408 } 409 410 static int uvd_v7_0_sw_init(void *handle) 411 { 412 struct amdgpu_ring *ring; 413 414 int i, j, r; 415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 416 417 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 418 if (adev->uvd.harvest_config & (1 << j)) 419 continue; 420 /* UVD TRAP */ 421 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 422 if (r) 423 return r; 424 425 /* UVD ENC TRAP */ 426 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 427 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 428 if (r) 429 return r; 430 } 431 } 432 433 r = amdgpu_uvd_sw_init(adev); 434 if (r) 435 return r; 436 437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 438 const struct common_firmware_header *hdr; 439 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 440 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 441 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 442 adev->firmware.fw_size += 443 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 444 445 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { 446 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1; 447 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; 448 adev->firmware.fw_size += 449 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 450 } 451 DRM_INFO("PSP loading UVD firmware\n"); 452 } 453 454 r = amdgpu_uvd_resume(adev); 455 if (r) 456 return r; 457 458 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 459 if (adev->uvd.harvest_config & (1 << j)) 460 continue; 461 if (!amdgpu_sriov_vf(adev)) { 462 ring = &adev->uvd.inst[j].ring; 463 sprintf(ring->name, "uvd<%d>", j); 464 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); 465 if (r) 466 return r; 467 } 468 469 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 470 ring = &adev->uvd.inst[j].ring_enc[i]; 471 sprintf(ring->name, "uvd_enc%d<%d>", i, j); 472 if (amdgpu_sriov_vf(adev)) { 473 ring->use_doorbell = true; 474 475 /* currently only use the first enconding ring for 476 * sriov, so set unused location for other unused rings. 477 */ 478 if (i == 0) 479 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; 480 else 481 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; 482 } 483 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); 484 if (r) 485 return r; 486 } 487 } 488 489 r = amdgpu_uvd_entity_init(adev); 490 if (r) 491 return r; 492 493 r = amdgpu_virt_alloc_mm_table(adev); 494 if (r) 495 return r; 496 497 return r; 498 } 499 500 static int uvd_v7_0_sw_fini(void *handle) 501 { 502 int i, j, r; 503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 504 505 amdgpu_virt_free_mm_table(adev); 506 507 r = amdgpu_uvd_suspend(adev); 508 if (r) 509 return r; 510 511 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 512 if (adev->uvd.harvest_config & (1 << j)) 513 continue; 514 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 515 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 516 } 517 return amdgpu_uvd_sw_fini(adev); 518 } 519 520 /** 521 * uvd_v7_0_hw_init - start and test UVD block 522 * 523 * @adev: amdgpu_device pointer 524 * 525 * Initialize the hardware, boot up the VCPU and do some testing 526 */ 527 static int uvd_v7_0_hw_init(void *handle) 528 { 529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 530 struct amdgpu_ring *ring; 531 uint32_t tmp; 532 int i, j, r; 533 534 if (amdgpu_sriov_vf(adev)) 535 r = uvd_v7_0_sriov_start(adev); 536 else 537 r = uvd_v7_0_start(adev); 538 if (r) 539 goto done; 540 541 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 542 if (adev->uvd.harvest_config & (1 << j)) 543 continue; 544 ring = &adev->uvd.inst[j].ring; 545 546 if (!amdgpu_sriov_vf(adev)) { 547 ring->ready = true; 548 r = amdgpu_ring_test_ring(ring); 549 if (r) { 550 ring->ready = false; 551 goto done; 552 } 553 554 r = amdgpu_ring_alloc(ring, 10); 555 if (r) { 556 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); 557 goto done; 558 } 559 560 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 561 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 562 amdgpu_ring_write(ring, tmp); 563 amdgpu_ring_write(ring, 0xFFFFF); 564 565 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 566 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 567 amdgpu_ring_write(ring, tmp); 568 amdgpu_ring_write(ring, 0xFFFFF); 569 570 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 571 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 572 amdgpu_ring_write(ring, tmp); 573 amdgpu_ring_write(ring, 0xFFFFF); 574 575 /* Clear timeout status bits */ 576 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 577 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 578 amdgpu_ring_write(ring, 0x8); 579 580 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 581 mmUVD_SEMA_CNTL), 0)); 582 amdgpu_ring_write(ring, 3); 583 584 amdgpu_ring_commit(ring); 585 } 586 587 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 588 ring = &adev->uvd.inst[j].ring_enc[i]; 589 ring->ready = true; 590 r = amdgpu_ring_test_ring(ring); 591 if (r) { 592 ring->ready = false; 593 goto done; 594 } 595 } 596 } 597 done: 598 if (!r) 599 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 600 601 return r; 602 } 603 604 /** 605 * uvd_v7_0_hw_fini - stop the hardware block 606 * 607 * @adev: amdgpu_device pointer 608 * 609 * Stop the UVD block, mark ring as not ready any more 610 */ 611 static int uvd_v7_0_hw_fini(void *handle) 612 { 613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 614 int i; 615 616 if (!amdgpu_sriov_vf(adev)) 617 uvd_v7_0_stop(adev); 618 else { 619 /* full access mode, so don't touch any UVD register */ 620 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 621 } 622 623 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 624 if (adev->uvd.harvest_config & (1 << i)) 625 continue; 626 adev->uvd.inst[i].ring.ready = false; 627 } 628 629 return 0; 630 } 631 632 static int uvd_v7_0_suspend(void *handle) 633 { 634 int r; 635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 636 637 r = uvd_v7_0_hw_fini(adev); 638 if (r) 639 return r; 640 641 return amdgpu_uvd_suspend(adev); 642 } 643 644 static int uvd_v7_0_resume(void *handle) 645 { 646 int r; 647 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 648 649 r = amdgpu_uvd_resume(adev); 650 if (r) 651 return r; 652 653 return uvd_v7_0_hw_init(adev); 654 } 655 656 /** 657 * uvd_v7_0_mc_resume - memory controller programming 658 * 659 * @adev: amdgpu_device pointer 660 * 661 * Let the UVD memory controller know it's offsets 662 */ 663 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 664 { 665 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 666 uint32_t offset; 667 int i; 668 669 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 670 if (adev->uvd.harvest_config & (1 << i)) 671 continue; 672 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 673 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 674 i == 0 ? 675 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo: 676 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo); 677 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 678 i == 0 ? 679 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi: 680 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi); 681 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 682 offset = 0; 683 } else { 684 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 685 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 686 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 687 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 688 offset = size; 689 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 690 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 691 } 692 693 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 694 695 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 696 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 697 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 698 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 699 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 700 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 701 702 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 703 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 704 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 705 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 706 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 707 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 708 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 709 710 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 711 adev->gfx.config.gb_addr_config); 712 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 713 adev->gfx.config.gb_addr_config); 714 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 715 adev->gfx.config.gb_addr_config); 716 717 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 718 } 719 } 720 721 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 722 struct amdgpu_mm_table *table) 723 { 724 uint32_t data = 0, loop; 725 uint64_t addr = table->gpu_addr; 726 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 727 uint32_t size; 728 int i; 729 730 size = header->header_size + header->vce_table_size + header->uvd_table_size; 731 732 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 733 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 734 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 735 736 /* 2, update vmid of descriptor */ 737 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 738 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 739 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 740 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 741 742 /* 3, notify mmsch about the size of this descriptor */ 743 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 744 745 /* 4, set resp to zero */ 746 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 747 748 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 749 if (adev->uvd.harvest_config & (1 << i)) 750 continue; 751 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 752 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; 753 adev->uvd.inst[i].ring_enc[0].wptr = 0; 754 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 755 } 756 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 757 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 758 759 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 760 loop = 1000; 761 while ((data & 0x10000002) != 0x10000002) { 762 udelay(10); 763 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 764 loop--; 765 if (!loop) 766 break; 767 } 768 769 if (!loop) { 770 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 771 return -EBUSY; 772 } 773 774 return 0; 775 } 776 777 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 778 { 779 struct amdgpu_ring *ring; 780 uint32_t offset, size, tmp; 781 uint32_t table_size = 0; 782 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 783 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 784 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 785 struct mmsch_v1_0_cmd_end end = { {0} }; 786 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 787 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 788 uint8_t i = 0; 789 790 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 791 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 792 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 793 end.cmd_header.command_type = MMSCH_COMMAND__END; 794 795 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 796 header->version = MMSCH_VERSION; 797 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 798 799 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 800 header->uvd_table_offset = header->header_size; 801 else 802 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 803 804 init_table += header->uvd_table_offset; 805 806 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 807 if (adev->uvd.harvest_config & (1 << i)) 808 continue; 809 ring = &adev->uvd.inst[i].ring; 810 ring->wptr = 0; 811 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 812 813 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 814 0xFFFFFFFF, 0x00000004); 815 /* mc resume*/ 816 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 817 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 818 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 819 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 820 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 821 offset = 0; 822 } else { 823 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 824 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 825 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 826 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 827 offset = size; 828 } 829 830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 831 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 833 834 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 835 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 836 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 837 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 838 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 839 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 840 841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 842 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 843 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 844 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 845 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 846 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 847 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 848 849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 850 /* mc resume end*/ 851 852 /* disable clock gating */ 853 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 854 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 855 856 /* disable interupt */ 857 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 858 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 859 860 /* stall UMC and register bus before resetting VCPU */ 861 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 862 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 863 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 864 865 /* put LMI, VCPU, RBC etc... into reset */ 866 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 867 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 868 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 869 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 870 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 871 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 872 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 873 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 874 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 875 876 /* initialize UVD memory controller */ 877 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 878 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 879 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 880 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 881 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 882 UVD_LMI_CTRL__REQ_MODE_MASK | 883 0x00100000L)); 884 885 /* take all subblocks out of reset, except VCPU */ 886 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 887 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 888 889 /* enable VCPU clock */ 890 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 891 UVD_VCPU_CNTL__CLK_EN_MASK); 892 893 /* enable master interrupt */ 894 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 895 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 896 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 897 898 /* clear the bit 4 of UVD_STATUS */ 899 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 900 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 901 902 /* force RBC into idle state */ 903 size = order_base_2(ring->ring_size); 904 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 905 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 906 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 907 908 ring = &adev->uvd.inst[i].ring_enc[0]; 909 ring->wptr = 0; 910 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 911 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 912 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 913 914 /* boot up the VCPU */ 915 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 916 917 /* enable UMC */ 918 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 919 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 920 921 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 922 } 923 /* add end packet */ 924 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 925 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 926 header->uvd_table_size = table_size; 927 928 } 929 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 930 } 931 932 /** 933 * uvd_v7_0_start - start UVD block 934 * 935 * @adev: amdgpu_device pointer 936 * 937 * Setup and start the UVD block 938 */ 939 static int uvd_v7_0_start(struct amdgpu_device *adev) 940 { 941 struct amdgpu_ring *ring; 942 uint32_t rb_bufsz, tmp; 943 uint32_t lmi_swap_cntl; 944 uint32_t mp_swap_cntl; 945 int i, j, k, r; 946 947 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 948 if (adev->uvd.harvest_config & (1 << k)) 949 continue; 950 /* disable DPG */ 951 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 952 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 953 } 954 955 /* disable byte swapping */ 956 lmi_swap_cntl = 0; 957 mp_swap_cntl = 0; 958 959 uvd_v7_0_mc_resume(adev); 960 961 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 962 if (adev->uvd.harvest_config & (1 << k)) 963 continue; 964 ring = &adev->uvd.inst[k].ring; 965 /* disable clock gating */ 966 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 967 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 968 969 /* disable interupt */ 970 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 971 ~UVD_MASTINT_EN__VCPU_EN_MASK); 972 973 /* stall UMC and register bus before resetting VCPU */ 974 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 975 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 976 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 977 mdelay(1); 978 979 /* put LMI, VCPU, RBC etc... into reset */ 980 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 981 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 982 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 983 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 984 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 985 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 986 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 987 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 988 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 989 mdelay(5); 990 991 /* initialize UVD memory controller */ 992 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 993 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 994 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 995 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 996 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 997 UVD_LMI_CTRL__REQ_MODE_MASK | 998 0x00100000L); 999 1000 #ifdef __BIG_ENDIAN 1001 /* swap (8 in 32) RB and IB */ 1002 lmi_swap_cntl = 0xa; 1003 mp_swap_cntl = 0; 1004 #endif 1005 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1006 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 1007 1008 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 1009 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 1010 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 1011 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 1012 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 1013 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 1014 1015 /* take all subblocks out of reset, except VCPU */ 1016 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1017 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1018 mdelay(5); 1019 1020 /* enable VCPU clock */ 1021 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 1022 UVD_VCPU_CNTL__CLK_EN_MASK); 1023 1024 /* enable UMC */ 1025 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1026 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1027 1028 /* boot up the VCPU */ 1029 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1030 mdelay(10); 1031 1032 for (i = 0; i < 10; ++i) { 1033 uint32_t status; 1034 1035 for (j = 0; j < 100; ++j) { 1036 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1037 if (status & 2) 1038 break; 1039 mdelay(10); 1040 } 1041 r = 0; 1042 if (status & 2) 1043 break; 1044 1045 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1046 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1047 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1048 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1049 mdelay(10); 1050 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1051 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1052 mdelay(10); 1053 r = -1; 1054 } 1055 1056 if (r) { 1057 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1058 return r; 1059 } 1060 /* enable master interrupt */ 1061 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1062 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1063 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1064 1065 /* clear the bit 4 of UVD_STATUS */ 1066 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1067 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1068 1069 /* force RBC into idle state */ 1070 rb_bufsz = order_base_2(ring->ring_size); 1071 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1072 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1073 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1074 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1075 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1076 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1077 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1078 1079 /* set the write pointer delay */ 1080 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1081 1082 /* set the wb address */ 1083 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1084 (upper_32_bits(ring->gpu_addr) >> 2)); 1085 1086 /* programm the RB_BASE for ring buffer */ 1087 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1088 lower_32_bits(ring->gpu_addr)); 1089 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1090 upper_32_bits(ring->gpu_addr)); 1091 1092 /* Initialize the ring buffer's read and write pointers */ 1093 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1094 1095 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1096 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1097 lower_32_bits(ring->wptr)); 1098 1099 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1100 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1101 1102 ring = &adev->uvd.inst[k].ring_enc[0]; 1103 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1104 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1105 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1106 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1107 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1108 1109 ring = &adev->uvd.inst[k].ring_enc[1]; 1110 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1111 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1112 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1113 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1114 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1115 } 1116 return 0; 1117 } 1118 1119 /** 1120 * uvd_v7_0_stop - stop UVD block 1121 * 1122 * @adev: amdgpu_device pointer 1123 * 1124 * stop the UVD block 1125 */ 1126 static void uvd_v7_0_stop(struct amdgpu_device *adev) 1127 { 1128 uint8_t i = 0; 1129 1130 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1131 if (adev->uvd.harvest_config & (1 << i)) 1132 continue; 1133 /* force RBC into idle state */ 1134 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1135 1136 /* Stall UMC and register bus before resetting VCPU */ 1137 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1138 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1139 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1140 mdelay(1); 1141 1142 /* put VCPU into reset */ 1143 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1144 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1145 mdelay(5); 1146 1147 /* disable VCPU clock */ 1148 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1149 1150 /* Unstall UMC and register bus */ 1151 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1152 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1153 } 1154 } 1155 1156 /** 1157 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1158 * 1159 * @ring: amdgpu_ring pointer 1160 * @fence: fence to emit 1161 * 1162 * Write a fence and a trap command to the ring. 1163 */ 1164 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1165 unsigned flags) 1166 { 1167 struct amdgpu_device *adev = ring->adev; 1168 1169 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1170 1171 amdgpu_ring_write(ring, 1172 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1173 amdgpu_ring_write(ring, seq); 1174 amdgpu_ring_write(ring, 1175 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1176 amdgpu_ring_write(ring, addr & 0xffffffff); 1177 amdgpu_ring_write(ring, 1178 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1179 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1180 amdgpu_ring_write(ring, 1181 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1182 amdgpu_ring_write(ring, 0); 1183 1184 amdgpu_ring_write(ring, 1185 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1186 amdgpu_ring_write(ring, 0); 1187 amdgpu_ring_write(ring, 1188 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1189 amdgpu_ring_write(ring, 0); 1190 amdgpu_ring_write(ring, 1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1192 amdgpu_ring_write(ring, 2); 1193 } 1194 1195 /** 1196 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1197 * 1198 * @ring: amdgpu_ring pointer 1199 * @fence: fence to emit 1200 * 1201 * Write enc a fence and a trap command to the ring. 1202 */ 1203 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1204 u64 seq, unsigned flags) 1205 { 1206 1207 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1208 1209 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1210 amdgpu_ring_write(ring, addr); 1211 amdgpu_ring_write(ring, upper_32_bits(addr)); 1212 amdgpu_ring_write(ring, seq); 1213 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1214 } 1215 1216 /** 1217 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1218 * 1219 * @ring: amdgpu_ring pointer 1220 */ 1221 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1222 { 1223 /* The firmware doesn't seem to like touching registers at this point. */ 1224 } 1225 1226 /** 1227 * uvd_v7_0_ring_test_ring - register write test 1228 * 1229 * @ring: amdgpu_ring pointer 1230 * 1231 * Test if we can successfully write to the context register 1232 */ 1233 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1234 { 1235 struct amdgpu_device *adev = ring->adev; 1236 uint32_t tmp = 0; 1237 unsigned i; 1238 int r; 1239 1240 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1241 r = amdgpu_ring_alloc(ring, 3); 1242 if (r) { 1243 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n", 1244 ring->me, ring->idx, r); 1245 return r; 1246 } 1247 amdgpu_ring_write(ring, 1248 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1249 amdgpu_ring_write(ring, 0xDEADBEEF); 1250 amdgpu_ring_commit(ring); 1251 for (i = 0; i < adev->usec_timeout; i++) { 1252 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1253 if (tmp == 0xDEADBEEF) 1254 break; 1255 DRM_UDELAY(1); 1256 } 1257 1258 if (i < adev->usec_timeout) { 1259 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n", 1260 ring->me, ring->idx, i); 1261 } else { 1262 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n", 1263 ring->me, ring->idx, tmp); 1264 r = -EINVAL; 1265 } 1266 return r; 1267 } 1268 1269 /** 1270 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1271 * 1272 * @p: the CS parser with the IBs 1273 * @ib_idx: which IB to patch 1274 * 1275 */ 1276 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1277 uint32_t ib_idx) 1278 { 1279 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1280 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1281 unsigned i; 1282 1283 /* No patching necessary for the first instance */ 1284 if (!ring->me) 1285 return 0; 1286 1287 for (i = 0; i < ib->length_dw; i += 2) { 1288 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1289 1290 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1291 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1292 1293 amdgpu_set_ib_value(p, ib_idx, i, reg); 1294 } 1295 return 0; 1296 } 1297 1298 /** 1299 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1300 * 1301 * @ring: amdgpu_ring pointer 1302 * @ib: indirect buffer to execute 1303 * 1304 * Write ring commands to execute the indirect buffer 1305 */ 1306 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1307 struct amdgpu_ib *ib, 1308 unsigned vmid, bool ctx_switch) 1309 { 1310 struct amdgpu_device *adev = ring->adev; 1311 1312 amdgpu_ring_write(ring, 1313 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1314 amdgpu_ring_write(ring, vmid); 1315 1316 amdgpu_ring_write(ring, 1317 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1318 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1319 amdgpu_ring_write(ring, 1320 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1321 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1322 amdgpu_ring_write(ring, 1323 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1324 amdgpu_ring_write(ring, ib->length_dw); 1325 } 1326 1327 /** 1328 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1329 * 1330 * @ring: amdgpu_ring pointer 1331 * @ib: indirect buffer to execute 1332 * 1333 * Write enc ring commands to execute the indirect buffer 1334 */ 1335 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1336 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) 1337 { 1338 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1339 amdgpu_ring_write(ring, vmid); 1340 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1341 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1342 amdgpu_ring_write(ring, ib->length_dw); 1343 } 1344 1345 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1346 uint32_t reg, uint32_t val) 1347 { 1348 struct amdgpu_device *adev = ring->adev; 1349 1350 amdgpu_ring_write(ring, 1351 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1352 amdgpu_ring_write(ring, reg << 2); 1353 amdgpu_ring_write(ring, 1354 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1355 amdgpu_ring_write(ring, val); 1356 amdgpu_ring_write(ring, 1357 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1358 amdgpu_ring_write(ring, 8); 1359 } 1360 1361 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1362 uint32_t val, uint32_t mask) 1363 { 1364 struct amdgpu_device *adev = ring->adev; 1365 1366 amdgpu_ring_write(ring, 1367 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1368 amdgpu_ring_write(ring, reg << 2); 1369 amdgpu_ring_write(ring, 1370 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1371 amdgpu_ring_write(ring, val); 1372 amdgpu_ring_write(ring, 1373 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1374 amdgpu_ring_write(ring, mask); 1375 amdgpu_ring_write(ring, 1376 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1377 amdgpu_ring_write(ring, 12); 1378 } 1379 1380 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1381 unsigned vmid, uint64_t pd_addr) 1382 { 1383 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1384 uint32_t data0, data1, mask; 1385 1386 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1387 1388 /* wait for reg writes */ 1389 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1390 data1 = lower_32_bits(pd_addr); 1391 mask = 0xffffffff; 1392 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1393 } 1394 1395 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1396 { 1397 struct amdgpu_device *adev = ring->adev; 1398 int i; 1399 1400 WARN_ON(ring->wptr % 2 || count % 2); 1401 1402 for (i = 0; i < count / 2; i++) { 1403 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1404 amdgpu_ring_write(ring, 0); 1405 } 1406 } 1407 1408 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1409 { 1410 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1411 } 1412 1413 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1414 uint32_t reg, uint32_t val, 1415 uint32_t mask) 1416 { 1417 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1418 amdgpu_ring_write(ring, reg << 2); 1419 amdgpu_ring_write(ring, mask); 1420 amdgpu_ring_write(ring, val); 1421 } 1422 1423 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1424 unsigned int vmid, uint64_t pd_addr) 1425 { 1426 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1427 1428 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1429 1430 /* wait for reg writes */ 1431 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1432 lower_32_bits(pd_addr), 0xffffffff); 1433 } 1434 1435 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1436 uint32_t reg, uint32_t val) 1437 { 1438 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1439 amdgpu_ring_write(ring, reg << 2); 1440 amdgpu_ring_write(ring, val); 1441 } 1442 1443 #if 0 1444 static bool uvd_v7_0_is_idle(void *handle) 1445 { 1446 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1447 1448 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1449 } 1450 1451 static int uvd_v7_0_wait_for_idle(void *handle) 1452 { 1453 unsigned i; 1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1455 1456 for (i = 0; i < adev->usec_timeout; i++) { 1457 if (uvd_v7_0_is_idle(handle)) 1458 return 0; 1459 } 1460 return -ETIMEDOUT; 1461 } 1462 1463 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1464 static bool uvd_v7_0_check_soft_reset(void *handle) 1465 { 1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1467 u32 srbm_soft_reset = 0; 1468 u32 tmp = RREG32(mmSRBM_STATUS); 1469 1470 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1471 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1472 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & 1473 AMDGPU_UVD_STATUS_BUSY_MASK)) 1474 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1475 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1476 1477 if (srbm_soft_reset) { 1478 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; 1479 return true; 1480 } else { 1481 adev->uvd.inst[ring->me].srbm_soft_reset = 0; 1482 return false; 1483 } 1484 } 1485 1486 static int uvd_v7_0_pre_soft_reset(void *handle) 1487 { 1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1489 1490 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1491 return 0; 1492 1493 uvd_v7_0_stop(adev); 1494 return 0; 1495 } 1496 1497 static int uvd_v7_0_soft_reset(void *handle) 1498 { 1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1500 u32 srbm_soft_reset; 1501 1502 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1503 return 0; 1504 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; 1505 1506 if (srbm_soft_reset) { 1507 u32 tmp; 1508 1509 tmp = RREG32(mmSRBM_SOFT_RESET); 1510 tmp |= srbm_soft_reset; 1511 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1512 WREG32(mmSRBM_SOFT_RESET, tmp); 1513 tmp = RREG32(mmSRBM_SOFT_RESET); 1514 1515 udelay(50); 1516 1517 tmp &= ~srbm_soft_reset; 1518 WREG32(mmSRBM_SOFT_RESET, tmp); 1519 tmp = RREG32(mmSRBM_SOFT_RESET); 1520 1521 /* Wait a little for things to settle down */ 1522 udelay(50); 1523 } 1524 1525 return 0; 1526 } 1527 1528 static int uvd_v7_0_post_soft_reset(void *handle) 1529 { 1530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1531 1532 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1533 return 0; 1534 1535 mdelay(5); 1536 1537 return uvd_v7_0_start(adev); 1538 } 1539 #endif 1540 1541 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1542 struct amdgpu_irq_src *source, 1543 unsigned type, 1544 enum amdgpu_interrupt_state state) 1545 { 1546 // TODO 1547 return 0; 1548 } 1549 1550 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1551 struct amdgpu_irq_src *source, 1552 struct amdgpu_iv_entry *entry) 1553 { 1554 uint32_t ip_instance; 1555 1556 switch (entry->client_id) { 1557 case SOC15_IH_CLIENTID_UVD: 1558 ip_instance = 0; 1559 break; 1560 case SOC15_IH_CLIENTID_UVD1: 1561 ip_instance = 1; 1562 break; 1563 default: 1564 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1565 return 0; 1566 } 1567 1568 DRM_DEBUG("IH: UVD TRAP\n"); 1569 1570 switch (entry->src_id) { 1571 case 124: 1572 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1573 break; 1574 case 119: 1575 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1576 break; 1577 case 120: 1578 if (!amdgpu_sriov_vf(adev)) 1579 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1580 break; 1581 default: 1582 DRM_ERROR("Unhandled interrupt: %d %d\n", 1583 entry->src_id, entry->src_data[0]); 1584 break; 1585 } 1586 1587 return 0; 1588 } 1589 1590 #if 0 1591 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) 1592 { 1593 uint32_t data, data1, data2, suvd_flags; 1594 1595 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1596 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1597 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1598 1599 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1600 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1601 1602 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1603 UVD_SUVD_CGC_GATE__SIT_MASK | 1604 UVD_SUVD_CGC_GATE__SMP_MASK | 1605 UVD_SUVD_CGC_GATE__SCM_MASK | 1606 UVD_SUVD_CGC_GATE__SDB_MASK; 1607 1608 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1609 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1610 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1611 1612 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1613 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1614 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1615 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1616 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1617 UVD_CGC_CTRL__SYS_MODE_MASK | 1618 UVD_CGC_CTRL__UDEC_MODE_MASK | 1619 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1620 UVD_CGC_CTRL__REGS_MODE_MASK | 1621 UVD_CGC_CTRL__RBC_MODE_MASK | 1622 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1623 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1624 UVD_CGC_CTRL__IDCT_MODE_MASK | 1625 UVD_CGC_CTRL__MPRD_MODE_MASK | 1626 UVD_CGC_CTRL__MPC_MODE_MASK | 1627 UVD_CGC_CTRL__LBSI_MODE_MASK | 1628 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1629 UVD_CGC_CTRL__WCB_MODE_MASK | 1630 UVD_CGC_CTRL__VCPU_MODE_MASK | 1631 UVD_CGC_CTRL__JPEG_MODE_MASK | 1632 UVD_CGC_CTRL__JPEG2_MODE_MASK | 1633 UVD_CGC_CTRL__SCPU_MODE_MASK); 1634 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1635 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1636 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1637 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1638 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1639 data1 |= suvd_flags; 1640 1641 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); 1642 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); 1643 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1644 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); 1645 } 1646 1647 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) 1648 { 1649 uint32_t data, data1, cgc_flags, suvd_flags; 1650 1651 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); 1652 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1653 1654 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1655 UVD_CGC_GATE__UDEC_MASK | 1656 UVD_CGC_GATE__MPEG2_MASK | 1657 UVD_CGC_GATE__RBC_MASK | 1658 UVD_CGC_GATE__LMI_MC_MASK | 1659 UVD_CGC_GATE__IDCT_MASK | 1660 UVD_CGC_GATE__MPRD_MASK | 1661 UVD_CGC_GATE__MPC_MASK | 1662 UVD_CGC_GATE__LBSI_MASK | 1663 UVD_CGC_GATE__LRBBM_MASK | 1664 UVD_CGC_GATE__UDEC_RE_MASK | 1665 UVD_CGC_GATE__UDEC_CM_MASK | 1666 UVD_CGC_GATE__UDEC_IT_MASK | 1667 UVD_CGC_GATE__UDEC_DB_MASK | 1668 UVD_CGC_GATE__UDEC_MP_MASK | 1669 UVD_CGC_GATE__WCB_MASK | 1670 UVD_CGC_GATE__VCPU_MASK | 1671 UVD_CGC_GATE__SCPU_MASK | 1672 UVD_CGC_GATE__JPEG_MASK | 1673 UVD_CGC_GATE__JPEG2_MASK; 1674 1675 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1676 UVD_SUVD_CGC_GATE__SIT_MASK | 1677 UVD_SUVD_CGC_GATE__SMP_MASK | 1678 UVD_SUVD_CGC_GATE__SCM_MASK | 1679 UVD_SUVD_CGC_GATE__SDB_MASK; 1680 1681 data |= cgc_flags; 1682 data1 |= suvd_flags; 1683 1684 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); 1685 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1686 } 1687 1688 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 1689 { 1690 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1691 1692 if (enable) 1693 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1694 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1695 else 1696 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1697 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1698 1699 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 1700 } 1701 1702 1703 static int uvd_v7_0_set_clockgating_state(void *handle, 1704 enum amd_clockgating_state state) 1705 { 1706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1707 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1708 1709 uvd_v7_0_set_bypass_mode(adev, enable); 1710 1711 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 1712 return 0; 1713 1714 if (enable) { 1715 /* disable HW gating and enable Sw gating */ 1716 uvd_v7_0_set_sw_clock_gating(adev); 1717 } else { 1718 /* wait for STATUS to clear */ 1719 if (uvd_v7_0_wait_for_idle(handle)) 1720 return -EBUSY; 1721 1722 /* enable HW gates because UVD is idle */ 1723 /* uvd_v7_0_set_hw_clock_gating(adev); */ 1724 } 1725 1726 return 0; 1727 } 1728 1729 static int uvd_v7_0_set_powergating_state(void *handle, 1730 enum amd_powergating_state state) 1731 { 1732 /* This doesn't actually powergate the UVD block. 1733 * That's done in the dpm code via the SMC. This 1734 * just re-inits the block as necessary. The actual 1735 * gating still happens in the dpm code. We should 1736 * revisit this when there is a cleaner line between 1737 * the smc and the hw blocks 1738 */ 1739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1740 1741 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1742 return 0; 1743 1744 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1745 1746 if (state == AMD_PG_STATE_GATE) { 1747 uvd_v7_0_stop(adev); 1748 return 0; 1749 } else { 1750 return uvd_v7_0_start(adev); 1751 } 1752 } 1753 #endif 1754 1755 static int uvd_v7_0_set_clockgating_state(void *handle, 1756 enum amd_clockgating_state state) 1757 { 1758 /* needed for driver unload*/ 1759 return 0; 1760 } 1761 1762 const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1763 .name = "uvd_v7_0", 1764 .early_init = uvd_v7_0_early_init, 1765 .late_init = NULL, 1766 .sw_init = uvd_v7_0_sw_init, 1767 .sw_fini = uvd_v7_0_sw_fini, 1768 .hw_init = uvd_v7_0_hw_init, 1769 .hw_fini = uvd_v7_0_hw_fini, 1770 .suspend = uvd_v7_0_suspend, 1771 .resume = uvd_v7_0_resume, 1772 .is_idle = NULL /* uvd_v7_0_is_idle */, 1773 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, 1774 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, 1775 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, 1776 .soft_reset = NULL /* uvd_v7_0_soft_reset */, 1777 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, 1778 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1779 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1780 }; 1781 1782 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1783 .type = AMDGPU_RING_TYPE_UVD, 1784 .align_mask = 0xf, 1785 .support_64bit_ptrs = false, 1786 .vmhub = AMDGPU_MMHUB, 1787 .get_rptr = uvd_v7_0_ring_get_rptr, 1788 .get_wptr = uvd_v7_0_ring_get_wptr, 1789 .set_wptr = uvd_v7_0_ring_set_wptr, 1790 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1791 .emit_frame_size = 1792 6 + /* hdp invalidate */ 1793 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1794 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1795 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1796 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1797 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1798 .emit_ib = uvd_v7_0_ring_emit_ib, 1799 .emit_fence = uvd_v7_0_ring_emit_fence, 1800 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1801 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1802 .test_ring = uvd_v7_0_ring_test_ring, 1803 .test_ib = amdgpu_uvd_ring_test_ib, 1804 .insert_nop = uvd_v7_0_ring_insert_nop, 1805 .pad_ib = amdgpu_ring_generic_pad_ib, 1806 .begin_use = amdgpu_uvd_ring_begin_use, 1807 .end_use = amdgpu_uvd_ring_end_use, 1808 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1809 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1810 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1811 }; 1812 1813 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1814 .type = AMDGPU_RING_TYPE_UVD_ENC, 1815 .align_mask = 0x3f, 1816 .nop = HEVC_ENC_CMD_NO_OP, 1817 .support_64bit_ptrs = false, 1818 .vmhub = AMDGPU_MMHUB, 1819 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1820 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1821 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1822 .emit_frame_size = 1823 3 + 3 + /* hdp flush / invalidate */ 1824 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1825 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1826 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1827 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1828 1, /* uvd_v7_0_enc_ring_insert_end */ 1829 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1830 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1831 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1832 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1833 .test_ring = uvd_v7_0_enc_ring_test_ring, 1834 .test_ib = uvd_v7_0_enc_ring_test_ib, 1835 .insert_nop = amdgpu_ring_insert_nop, 1836 .insert_end = uvd_v7_0_enc_ring_insert_end, 1837 .pad_ib = amdgpu_ring_generic_pad_ib, 1838 .begin_use = amdgpu_uvd_ring_begin_use, 1839 .end_use = amdgpu_uvd_ring_end_use, 1840 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1841 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1842 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1843 }; 1844 1845 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1846 { 1847 int i; 1848 1849 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1850 if (adev->uvd.harvest_config & (1 << i)) 1851 continue; 1852 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1853 adev->uvd.inst[i].ring.me = i; 1854 DRM_INFO("UVD(%d) is enabled in VM mode\n", i); 1855 } 1856 } 1857 1858 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1859 { 1860 int i, j; 1861 1862 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1863 if (adev->uvd.harvest_config & (1 << j)) 1864 continue; 1865 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1866 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1867 adev->uvd.inst[j].ring_enc[i].me = j; 1868 } 1869 1870 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); 1871 } 1872 } 1873 1874 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1875 .set = uvd_v7_0_set_interrupt_state, 1876 .process = uvd_v7_0_process_interrupt, 1877 }; 1878 1879 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1880 { 1881 int i; 1882 1883 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1884 if (adev->uvd.harvest_config & (1 << i)) 1885 continue; 1886 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1887 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1888 } 1889 } 1890 1891 const struct amdgpu_ip_block_version uvd_v7_0_ip_block = 1892 { 1893 .type = AMD_IP_BLOCK_TYPE_UVD, 1894 .major = 7, 1895 .minor = 0, 1896 .rev = 0, 1897 .funcs = &uvd_v7_0_ip_funcs, 1898 }; 1899