1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_uvd.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 #include "mmsch_v1_0.h" 32 33 #include "uvd/uvd_7_0_offset.h" 34 #include "uvd/uvd_7_0_sh_mask.h" 35 #include "vce/vce_4_0_offset.h" 36 #include "vce/vce_4_0_default.h" 37 #include "vce/vce_4_0_sh_mask.h" 38 #include "nbif/nbif_6_1_offset.h" 39 #include "hdp/hdp_4_0_offset.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "mmhub/mmhub_1_0_sh_mask.h" 42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 43 44 #define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 46 //UVD_PG0_CC_UVD_HARVESTING 47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 49 50 #define UVD7_MAX_HW_INSTANCES_VEGA20 2 51 52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int uvd_v7_0_start(struct amdgpu_device *adev); 56 static void uvd_v7_0_stop(struct amdgpu_device *adev); 57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 58 59 static int amdgpu_ih_clientid_uvds[] = { 60 SOC15_IH_CLIENTID_UVD, 61 SOC15_IH_CLIENTID_UVD1 62 }; 63 64 /** 65 * uvd_v7_0_ring_get_rptr - get read pointer 66 * 67 * @ring: amdgpu_ring pointer 68 * 69 * Returns the current hardware read pointer 70 */ 71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 72 { 73 struct amdgpu_device *adev = ring->adev; 74 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 76 } 77 78 /** 79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 80 * 81 * @ring: amdgpu_ring pointer 82 * 83 * Returns the current hardware enc read pointer 84 */ 85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 86 { 87 struct amdgpu_device *adev = ring->adev; 88 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 91 else 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 93 } 94 95 /** 96 * uvd_v7_0_ring_get_wptr - get write pointer 97 * 98 * @ring: amdgpu_ring pointer 99 * 100 * Returns the current hardware write pointer 101 */ 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 103 { 104 struct amdgpu_device *adev = ring->adev; 105 106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 107 } 108 109 /** 110 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 111 * 112 * @ring: amdgpu_ring pointer 113 * 114 * Returns the current hardware enc write pointer 115 */ 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 117 { 118 struct amdgpu_device *adev = ring->adev; 119 120 if (ring->use_doorbell) 121 return adev->wb.wb[ring->wptr_offs]; 122 123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 125 else 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 127 } 128 129 /** 130 * uvd_v7_0_ring_set_wptr - set write pointer 131 * 132 * @ring: amdgpu_ring pointer 133 * 134 * Commits the write pointer to the hardware 135 */ 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 137 { 138 struct amdgpu_device *adev = ring->adev; 139 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 141 } 142 143 /** 144 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 145 * 146 * @ring: amdgpu_ring pointer 147 * 148 * Commits the enc write pointer to the hardware 149 */ 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 151 { 152 struct amdgpu_device *adev = ring->adev; 153 154 if (ring->use_doorbell) { 155 /* XXX check if swapping is necessary on BE */ 156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 158 return; 159 } 160 161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 163 lower_32_bits(ring->wptr)); 164 else 165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 166 lower_32_bits(ring->wptr)); 167 } 168 169 /** 170 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 171 * 172 * @ring: the engine to test on 173 * 174 */ 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 176 { 177 struct amdgpu_device *adev = ring->adev; 178 uint32_t rptr = amdgpu_ring_get_rptr(ring); 179 unsigned i; 180 int r; 181 182 if (amdgpu_sriov_vf(adev)) 183 return 0; 184 185 r = amdgpu_ring_alloc(ring, 16); 186 if (r) { 187 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n", 188 ring->me, ring->idx, r); 189 return r; 190 } 191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 192 amdgpu_ring_commit(ring); 193 194 for (i = 0; i < adev->usec_timeout; i++) { 195 if (amdgpu_ring_get_rptr(ring) != rptr) 196 break; 197 DRM_UDELAY(1); 198 } 199 200 if (i < adev->usec_timeout) { 201 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n", 202 ring->me, ring->idx, i); 203 } else { 204 DRM_ERROR("amdgpu: (%d)ring %d test failed\n", 205 ring->me, ring->idx); 206 r = -ETIMEDOUT; 207 } 208 209 return r; 210 } 211 212 /** 213 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 214 * 215 * @adev: amdgpu_device pointer 216 * @ring: ring we should submit the msg to 217 * @handle: session handle to use 218 * @fence: optional fence to return 219 * 220 * Open up a stream for HW test 221 */ 222 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 223 struct dma_fence **fence) 224 { 225 const unsigned ib_size_dw = 16; 226 struct amdgpu_job *job; 227 struct amdgpu_ib *ib; 228 struct dma_fence *f = NULL; 229 uint64_t dummy; 230 int i, r; 231 232 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 233 if (r) 234 return r; 235 236 ib = &job->ibs[0]; 237 dummy = ib->gpu_addr + 1024; 238 239 ib->length_dw = 0; 240 ib->ptr[ib->length_dw++] = 0x00000018; 241 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 242 ib->ptr[ib->length_dw++] = handle; 243 ib->ptr[ib->length_dw++] = 0x00000000; 244 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 245 ib->ptr[ib->length_dw++] = dummy; 246 247 ib->ptr[ib->length_dw++] = 0x00000014; 248 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 249 ib->ptr[ib->length_dw++] = 0x0000001c; 250 ib->ptr[ib->length_dw++] = 0x00000000; 251 ib->ptr[ib->length_dw++] = 0x00000000; 252 253 ib->ptr[ib->length_dw++] = 0x00000008; 254 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 255 256 for (i = ib->length_dw; i < ib_size_dw; ++i) 257 ib->ptr[i] = 0x0; 258 259 r = amdgpu_job_submit_direct(job, ring, &f); 260 if (r) 261 goto err; 262 263 if (fence) 264 *fence = dma_fence_get(f); 265 dma_fence_put(f); 266 return 0; 267 268 err: 269 amdgpu_job_free(job); 270 return r; 271 } 272 273 /** 274 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 275 * 276 * @adev: amdgpu_device pointer 277 * @ring: ring we should submit the msg to 278 * @handle: session handle to use 279 * @fence: optional fence to return 280 * 281 * Close up a stream for HW test or if userspace failed to do so 282 */ 283 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 284 bool direct, struct dma_fence **fence) 285 { 286 const unsigned ib_size_dw = 16; 287 struct amdgpu_job *job; 288 struct amdgpu_ib *ib; 289 struct dma_fence *f = NULL; 290 uint64_t dummy; 291 int i, r; 292 293 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 294 if (r) 295 return r; 296 297 ib = &job->ibs[0]; 298 dummy = ib->gpu_addr + 1024; 299 300 ib->length_dw = 0; 301 ib->ptr[ib->length_dw++] = 0x00000018; 302 ib->ptr[ib->length_dw++] = 0x00000001; 303 ib->ptr[ib->length_dw++] = handle; 304 ib->ptr[ib->length_dw++] = 0x00000000; 305 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 306 ib->ptr[ib->length_dw++] = dummy; 307 308 ib->ptr[ib->length_dw++] = 0x00000014; 309 ib->ptr[ib->length_dw++] = 0x00000002; 310 ib->ptr[ib->length_dw++] = 0x0000001c; 311 ib->ptr[ib->length_dw++] = 0x00000000; 312 ib->ptr[ib->length_dw++] = 0x00000000; 313 314 ib->ptr[ib->length_dw++] = 0x00000008; 315 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 316 317 for (i = ib->length_dw; i < ib_size_dw; ++i) 318 ib->ptr[i] = 0x0; 319 320 if (direct) 321 r = amdgpu_job_submit_direct(job, ring, &f); 322 else 323 r = amdgpu_job_submit(job, &ring->adev->vce.entity, 324 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 325 if (r) 326 goto err; 327 328 if (fence) 329 *fence = dma_fence_get(f); 330 dma_fence_put(f); 331 return 0; 332 333 err: 334 amdgpu_job_free(job); 335 return r; 336 } 337 338 /** 339 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 340 * 341 * @ring: the engine to test on 342 * 343 */ 344 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 345 { 346 struct dma_fence *fence = NULL; 347 long r; 348 349 r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL); 350 if (r) { 351 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r); 352 goto error; 353 } 354 355 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence); 356 if (r) { 357 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r); 358 goto error; 359 } 360 361 r = dma_fence_wait_timeout(fence, false, timeout); 362 if (r == 0) { 363 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me); 364 r = -ETIMEDOUT; 365 } else if (r < 0) { 366 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r); 367 } else { 368 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx); 369 r = 0; 370 } 371 error: 372 dma_fence_put(fence); 373 return r; 374 } 375 376 static int uvd_v7_0_early_init(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 380 if (adev->asic_type == CHIP_VEGA20) { 381 u32 harvest; 382 int i; 383 384 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 385 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 386 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 387 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 388 adev->uvd.harvest_config |= 1 << i; 389 } 390 } 391 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 392 AMDGPU_UVD_HARVEST_UVD1)) 393 /* both instances are harvested, disable the block */ 394 return -ENOENT; 395 } else { 396 adev->uvd.num_uvd_inst = 1; 397 } 398 399 if (amdgpu_sriov_vf(adev)) 400 adev->uvd.num_enc_rings = 1; 401 else 402 adev->uvd.num_enc_rings = 2; 403 uvd_v7_0_set_ring_funcs(adev); 404 uvd_v7_0_set_enc_ring_funcs(adev); 405 uvd_v7_0_set_irq_funcs(adev); 406 407 return 0; 408 } 409 410 static int uvd_v7_0_sw_init(void *handle) 411 { 412 struct amdgpu_ring *ring; 413 414 int i, j, r; 415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 416 417 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 418 if (adev->uvd.harvest_config & (1 << j)) 419 continue; 420 /* UVD TRAP */ 421 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 422 if (r) 423 return r; 424 425 /* UVD ENC TRAP */ 426 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 427 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 428 if (r) 429 return r; 430 } 431 } 432 433 r = amdgpu_uvd_sw_init(adev); 434 if (r) 435 return r; 436 437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 438 const struct common_firmware_header *hdr; 439 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 440 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 441 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 442 adev->firmware.fw_size += 443 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 444 DRM_INFO("PSP loading UVD firmware\n"); 445 } 446 447 r = amdgpu_uvd_resume(adev); 448 if (r) 449 return r; 450 451 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 452 if (adev->uvd.harvest_config & (1 << j)) 453 continue; 454 if (!amdgpu_sriov_vf(adev)) { 455 ring = &adev->uvd.inst[j].ring; 456 sprintf(ring->name, "uvd<%d>", j); 457 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); 458 if (r) 459 return r; 460 } 461 462 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 463 ring = &adev->uvd.inst[j].ring_enc[i]; 464 sprintf(ring->name, "uvd_enc%d<%d>", i, j); 465 if (amdgpu_sriov_vf(adev)) { 466 ring->use_doorbell = true; 467 468 /* currently only use the first enconding ring for 469 * sriov, so set unused location for other unused rings. 470 */ 471 if (i == 0) 472 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; 473 else 474 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; 475 } 476 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); 477 if (r) 478 return r; 479 } 480 } 481 482 r = amdgpu_uvd_entity_init(adev); 483 if (r) 484 return r; 485 486 r = amdgpu_virt_alloc_mm_table(adev); 487 if (r) 488 return r; 489 490 return r; 491 } 492 493 static int uvd_v7_0_sw_fini(void *handle) 494 { 495 int i, j, r; 496 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 497 498 amdgpu_virt_free_mm_table(adev); 499 500 r = amdgpu_uvd_suspend(adev); 501 if (r) 502 return r; 503 504 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 505 if (adev->uvd.harvest_config & (1 << j)) 506 continue; 507 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 508 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 509 } 510 return amdgpu_uvd_sw_fini(adev); 511 } 512 513 /** 514 * uvd_v7_0_hw_init - start and test UVD block 515 * 516 * @adev: amdgpu_device pointer 517 * 518 * Initialize the hardware, boot up the VCPU and do some testing 519 */ 520 static int uvd_v7_0_hw_init(void *handle) 521 { 522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 523 struct amdgpu_ring *ring; 524 uint32_t tmp; 525 int i, j, r; 526 527 if (amdgpu_sriov_vf(adev)) 528 r = uvd_v7_0_sriov_start(adev); 529 else 530 r = uvd_v7_0_start(adev); 531 if (r) 532 goto done; 533 534 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 535 if (adev->uvd.harvest_config & (1 << j)) 536 continue; 537 ring = &adev->uvd.inst[j].ring; 538 539 if (!amdgpu_sriov_vf(adev)) { 540 ring->ready = true; 541 r = amdgpu_ring_test_ring(ring); 542 if (r) { 543 ring->ready = false; 544 goto done; 545 } 546 547 r = amdgpu_ring_alloc(ring, 10); 548 if (r) { 549 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); 550 goto done; 551 } 552 553 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 554 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 555 amdgpu_ring_write(ring, tmp); 556 amdgpu_ring_write(ring, 0xFFFFF); 557 558 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 559 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 560 amdgpu_ring_write(ring, tmp); 561 amdgpu_ring_write(ring, 0xFFFFF); 562 563 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 564 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 565 amdgpu_ring_write(ring, tmp); 566 amdgpu_ring_write(ring, 0xFFFFF); 567 568 /* Clear timeout status bits */ 569 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 570 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 571 amdgpu_ring_write(ring, 0x8); 572 573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 574 mmUVD_SEMA_CNTL), 0)); 575 amdgpu_ring_write(ring, 3); 576 577 amdgpu_ring_commit(ring); 578 } 579 580 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 581 ring = &adev->uvd.inst[j].ring_enc[i]; 582 ring->ready = true; 583 r = amdgpu_ring_test_ring(ring); 584 if (r) { 585 ring->ready = false; 586 goto done; 587 } 588 } 589 } 590 done: 591 if (!r) 592 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 593 594 return r; 595 } 596 597 /** 598 * uvd_v7_0_hw_fini - stop the hardware block 599 * 600 * @adev: amdgpu_device pointer 601 * 602 * Stop the UVD block, mark ring as not ready any more 603 */ 604 static int uvd_v7_0_hw_fini(void *handle) 605 { 606 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 607 int i; 608 609 if (!amdgpu_sriov_vf(adev)) 610 uvd_v7_0_stop(adev); 611 else { 612 /* full access mode, so don't touch any UVD register */ 613 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 614 } 615 616 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 617 if (adev->uvd.harvest_config & (1 << i)) 618 continue; 619 adev->uvd.inst[i].ring.ready = false; 620 } 621 622 return 0; 623 } 624 625 static int uvd_v7_0_suspend(void *handle) 626 { 627 int r; 628 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 629 630 r = uvd_v7_0_hw_fini(adev); 631 if (r) 632 return r; 633 634 return amdgpu_uvd_suspend(adev); 635 } 636 637 static int uvd_v7_0_resume(void *handle) 638 { 639 int r; 640 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 641 642 r = amdgpu_uvd_resume(adev); 643 if (r) 644 return r; 645 646 return uvd_v7_0_hw_init(adev); 647 } 648 649 /** 650 * uvd_v7_0_mc_resume - memory controller programming 651 * 652 * @adev: amdgpu_device pointer 653 * 654 * Let the UVD memory controller know it's offsets 655 */ 656 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 657 { 658 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 659 uint32_t offset; 660 int i; 661 662 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 663 if (adev->uvd.harvest_config & (1 << i)) 664 continue; 665 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 666 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 667 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 668 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 669 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 670 offset = 0; 671 } else { 672 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 673 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 674 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 675 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 676 offset = size; 677 } 678 679 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 680 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 681 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 682 683 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 684 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 685 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 686 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 687 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 688 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 689 690 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 691 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 692 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 693 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 695 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 696 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 697 698 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 699 adev->gfx.config.gb_addr_config); 700 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 701 adev->gfx.config.gb_addr_config); 702 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 703 adev->gfx.config.gb_addr_config); 704 705 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 706 } 707 } 708 709 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 710 struct amdgpu_mm_table *table) 711 { 712 uint32_t data = 0, loop; 713 uint64_t addr = table->gpu_addr; 714 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 715 uint32_t size; 716 int i; 717 718 size = header->header_size + header->vce_table_size + header->uvd_table_size; 719 720 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 721 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 722 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 723 724 /* 2, update vmid of descriptor */ 725 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 726 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 727 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 728 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 729 730 /* 3, notify mmsch about the size of this descriptor */ 731 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 732 733 /* 4, set resp to zero */ 734 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 735 736 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 737 if (adev->uvd.harvest_config & (1 << i)) 738 continue; 739 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 740 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; 741 adev->uvd.inst[i].ring_enc[0].wptr = 0; 742 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 743 } 744 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 745 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 746 747 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 748 loop = 1000; 749 while ((data & 0x10000002) != 0x10000002) { 750 udelay(10); 751 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 752 loop--; 753 if (!loop) 754 break; 755 } 756 757 if (!loop) { 758 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 759 return -EBUSY; 760 } 761 762 return 0; 763 } 764 765 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 766 { 767 struct amdgpu_ring *ring; 768 uint32_t offset, size, tmp; 769 uint32_t table_size = 0; 770 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 771 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 772 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 773 struct mmsch_v1_0_cmd_end end = { {0} }; 774 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 775 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 776 uint8_t i = 0; 777 778 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 779 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 780 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 781 end.cmd_header.command_type = MMSCH_COMMAND__END; 782 783 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 784 header->version = MMSCH_VERSION; 785 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 786 787 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 788 header->uvd_table_offset = header->header_size; 789 else 790 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 791 792 init_table += header->uvd_table_offset; 793 794 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 795 if (adev->uvd.harvest_config & (1 << i)) 796 continue; 797 ring = &adev->uvd.inst[i].ring; 798 ring->wptr = 0; 799 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 800 801 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 802 0xFFFFFFFF, 0x00000004); 803 /* mc resume*/ 804 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 805 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 806 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 807 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 808 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 809 offset = 0; 810 } else { 811 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 812 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 813 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 814 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 815 offset = size; 816 } 817 818 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 819 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 820 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 821 822 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 823 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 824 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 825 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 826 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 827 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 828 829 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 830 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 831 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 832 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 834 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 835 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 836 837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 838 /* mc resume end*/ 839 840 /* disable clock gating */ 841 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 842 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 843 844 /* disable interupt */ 845 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 846 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 847 848 /* stall UMC and register bus before resetting VCPU */ 849 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 850 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 851 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 852 853 /* put LMI, VCPU, RBC etc... into reset */ 854 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 855 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 856 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 857 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 858 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 859 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 860 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 861 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 862 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 863 864 /* initialize UVD memory controller */ 865 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 866 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 867 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 868 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 869 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 870 UVD_LMI_CTRL__REQ_MODE_MASK | 871 0x00100000L)); 872 873 /* take all subblocks out of reset, except VCPU */ 874 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 875 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 876 877 /* enable VCPU clock */ 878 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 879 UVD_VCPU_CNTL__CLK_EN_MASK); 880 881 /* enable master interrupt */ 882 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 883 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 884 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 885 886 /* clear the bit 4 of UVD_STATUS */ 887 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 888 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 889 890 /* force RBC into idle state */ 891 size = order_base_2(ring->ring_size); 892 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 893 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 894 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 895 896 ring = &adev->uvd.inst[i].ring_enc[0]; 897 ring->wptr = 0; 898 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 899 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 900 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 901 902 /* boot up the VCPU */ 903 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 904 905 /* enable UMC */ 906 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 907 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 908 909 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 910 } 911 /* add end packet */ 912 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 913 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 914 header->uvd_table_size = table_size; 915 916 } 917 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 918 } 919 920 /** 921 * uvd_v7_0_start - start UVD block 922 * 923 * @adev: amdgpu_device pointer 924 * 925 * Setup and start the UVD block 926 */ 927 static int uvd_v7_0_start(struct amdgpu_device *adev) 928 { 929 struct amdgpu_ring *ring; 930 uint32_t rb_bufsz, tmp; 931 uint32_t lmi_swap_cntl; 932 uint32_t mp_swap_cntl; 933 int i, j, k, r; 934 935 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 936 if (adev->uvd.harvest_config & (1 << k)) 937 continue; 938 /* disable DPG */ 939 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 940 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 941 } 942 943 /* disable byte swapping */ 944 lmi_swap_cntl = 0; 945 mp_swap_cntl = 0; 946 947 uvd_v7_0_mc_resume(adev); 948 949 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 950 if (adev->uvd.harvest_config & (1 << k)) 951 continue; 952 ring = &adev->uvd.inst[k].ring; 953 /* disable clock gating */ 954 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 955 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 956 957 /* disable interupt */ 958 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 959 ~UVD_MASTINT_EN__VCPU_EN_MASK); 960 961 /* stall UMC and register bus before resetting VCPU */ 962 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 963 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 964 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 965 mdelay(1); 966 967 /* put LMI, VCPU, RBC etc... into reset */ 968 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 969 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 970 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 971 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 972 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 973 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 974 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 975 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 976 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 977 mdelay(5); 978 979 /* initialize UVD memory controller */ 980 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 981 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 982 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 983 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 984 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 985 UVD_LMI_CTRL__REQ_MODE_MASK | 986 0x00100000L); 987 988 #ifdef __BIG_ENDIAN 989 /* swap (8 in 32) RB and IB */ 990 lmi_swap_cntl = 0xa; 991 mp_swap_cntl = 0; 992 #endif 993 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 994 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 995 996 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 997 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 998 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 999 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 1000 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 1001 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 1002 1003 /* take all subblocks out of reset, except VCPU */ 1004 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1005 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1006 mdelay(5); 1007 1008 /* enable VCPU clock */ 1009 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 1010 UVD_VCPU_CNTL__CLK_EN_MASK); 1011 1012 /* enable UMC */ 1013 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1014 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1015 1016 /* boot up the VCPU */ 1017 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1018 mdelay(10); 1019 1020 for (i = 0; i < 10; ++i) { 1021 uint32_t status; 1022 1023 for (j = 0; j < 100; ++j) { 1024 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1025 if (status & 2) 1026 break; 1027 mdelay(10); 1028 } 1029 r = 0; 1030 if (status & 2) 1031 break; 1032 1033 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1034 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1035 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1036 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1037 mdelay(10); 1038 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1039 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1040 mdelay(10); 1041 r = -1; 1042 } 1043 1044 if (r) { 1045 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1046 return r; 1047 } 1048 /* enable master interrupt */ 1049 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1050 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1051 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1052 1053 /* clear the bit 4 of UVD_STATUS */ 1054 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1055 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1056 1057 /* force RBC into idle state */ 1058 rb_bufsz = order_base_2(ring->ring_size); 1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1065 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1066 1067 /* set the write pointer delay */ 1068 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1069 1070 /* set the wb address */ 1071 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1072 (upper_32_bits(ring->gpu_addr) >> 2)); 1073 1074 /* programm the RB_BASE for ring buffer */ 1075 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1076 lower_32_bits(ring->gpu_addr)); 1077 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1078 upper_32_bits(ring->gpu_addr)); 1079 1080 /* Initialize the ring buffer's read and write pointers */ 1081 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1082 1083 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1084 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1085 lower_32_bits(ring->wptr)); 1086 1087 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1088 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1089 1090 ring = &adev->uvd.inst[k].ring_enc[0]; 1091 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1092 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1093 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1094 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1095 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1096 1097 ring = &adev->uvd.inst[k].ring_enc[1]; 1098 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1099 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1100 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1101 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1102 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1103 } 1104 return 0; 1105 } 1106 1107 /** 1108 * uvd_v7_0_stop - stop UVD block 1109 * 1110 * @adev: amdgpu_device pointer 1111 * 1112 * stop the UVD block 1113 */ 1114 static void uvd_v7_0_stop(struct amdgpu_device *adev) 1115 { 1116 uint8_t i = 0; 1117 1118 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1119 if (adev->uvd.harvest_config & (1 << i)) 1120 continue; 1121 /* force RBC into idle state */ 1122 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1123 1124 /* Stall UMC and register bus before resetting VCPU */ 1125 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1126 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1127 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1128 mdelay(1); 1129 1130 /* put VCPU into reset */ 1131 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1132 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1133 mdelay(5); 1134 1135 /* disable VCPU clock */ 1136 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1137 1138 /* Unstall UMC and register bus */ 1139 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1140 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1141 } 1142 } 1143 1144 /** 1145 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1146 * 1147 * @ring: amdgpu_ring pointer 1148 * @fence: fence to emit 1149 * 1150 * Write a fence and a trap command to the ring. 1151 */ 1152 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1153 unsigned flags) 1154 { 1155 struct amdgpu_device *adev = ring->adev; 1156 1157 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1158 1159 amdgpu_ring_write(ring, 1160 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1161 amdgpu_ring_write(ring, seq); 1162 amdgpu_ring_write(ring, 1163 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1164 amdgpu_ring_write(ring, addr & 0xffffffff); 1165 amdgpu_ring_write(ring, 1166 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1167 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1168 amdgpu_ring_write(ring, 1169 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1170 amdgpu_ring_write(ring, 0); 1171 1172 amdgpu_ring_write(ring, 1173 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1174 amdgpu_ring_write(ring, 0); 1175 amdgpu_ring_write(ring, 1176 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1177 amdgpu_ring_write(ring, 0); 1178 amdgpu_ring_write(ring, 1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1180 amdgpu_ring_write(ring, 2); 1181 } 1182 1183 /** 1184 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1185 * 1186 * @ring: amdgpu_ring pointer 1187 * @fence: fence to emit 1188 * 1189 * Write enc a fence and a trap command to the ring. 1190 */ 1191 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1192 u64 seq, unsigned flags) 1193 { 1194 1195 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1196 1197 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1198 amdgpu_ring_write(ring, addr); 1199 amdgpu_ring_write(ring, upper_32_bits(addr)); 1200 amdgpu_ring_write(ring, seq); 1201 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1202 } 1203 1204 /** 1205 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1206 * 1207 * @ring: amdgpu_ring pointer 1208 */ 1209 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1210 { 1211 /* The firmware doesn't seem to like touching registers at this point. */ 1212 } 1213 1214 /** 1215 * uvd_v7_0_ring_test_ring - register write test 1216 * 1217 * @ring: amdgpu_ring pointer 1218 * 1219 * Test if we can successfully write to the context register 1220 */ 1221 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1222 { 1223 struct amdgpu_device *adev = ring->adev; 1224 uint32_t tmp = 0; 1225 unsigned i; 1226 int r; 1227 1228 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1229 r = amdgpu_ring_alloc(ring, 3); 1230 if (r) { 1231 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n", 1232 ring->me, ring->idx, r); 1233 return r; 1234 } 1235 amdgpu_ring_write(ring, 1236 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1237 amdgpu_ring_write(ring, 0xDEADBEEF); 1238 amdgpu_ring_commit(ring); 1239 for (i = 0; i < adev->usec_timeout; i++) { 1240 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1241 if (tmp == 0xDEADBEEF) 1242 break; 1243 DRM_UDELAY(1); 1244 } 1245 1246 if (i < adev->usec_timeout) { 1247 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n", 1248 ring->me, ring->idx, i); 1249 } else { 1250 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n", 1251 ring->me, ring->idx, tmp); 1252 r = -EINVAL; 1253 } 1254 return r; 1255 } 1256 1257 /** 1258 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1259 * 1260 * @p: the CS parser with the IBs 1261 * @ib_idx: which IB to patch 1262 * 1263 */ 1264 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1265 uint32_t ib_idx) 1266 { 1267 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1268 unsigned i; 1269 1270 /* No patching necessary for the first instance */ 1271 if (!p->ring->me) 1272 return 0; 1273 1274 for (i = 0; i < ib->length_dw; i += 2) { 1275 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1276 1277 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1278 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1279 1280 amdgpu_set_ib_value(p, ib_idx, i, reg); 1281 } 1282 return 0; 1283 } 1284 1285 /** 1286 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1287 * 1288 * @ring: amdgpu_ring pointer 1289 * @ib: indirect buffer to execute 1290 * 1291 * Write ring commands to execute the indirect buffer 1292 */ 1293 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1294 struct amdgpu_ib *ib, 1295 unsigned vmid, bool ctx_switch) 1296 { 1297 struct amdgpu_device *adev = ring->adev; 1298 1299 amdgpu_ring_write(ring, 1300 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1301 amdgpu_ring_write(ring, vmid); 1302 1303 amdgpu_ring_write(ring, 1304 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1305 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1306 amdgpu_ring_write(ring, 1307 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1308 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1309 amdgpu_ring_write(ring, 1310 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1311 amdgpu_ring_write(ring, ib->length_dw); 1312 } 1313 1314 /** 1315 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1316 * 1317 * @ring: amdgpu_ring pointer 1318 * @ib: indirect buffer to execute 1319 * 1320 * Write enc ring commands to execute the indirect buffer 1321 */ 1322 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1323 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) 1324 { 1325 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1326 amdgpu_ring_write(ring, vmid); 1327 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1328 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1329 amdgpu_ring_write(ring, ib->length_dw); 1330 } 1331 1332 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1333 uint32_t reg, uint32_t val) 1334 { 1335 struct amdgpu_device *adev = ring->adev; 1336 1337 amdgpu_ring_write(ring, 1338 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1339 amdgpu_ring_write(ring, reg << 2); 1340 amdgpu_ring_write(ring, 1341 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1342 amdgpu_ring_write(ring, val); 1343 amdgpu_ring_write(ring, 1344 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1345 amdgpu_ring_write(ring, 8); 1346 } 1347 1348 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1349 uint32_t val, uint32_t mask) 1350 { 1351 struct amdgpu_device *adev = ring->adev; 1352 1353 amdgpu_ring_write(ring, 1354 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1355 amdgpu_ring_write(ring, reg << 2); 1356 amdgpu_ring_write(ring, 1357 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1358 amdgpu_ring_write(ring, val); 1359 amdgpu_ring_write(ring, 1360 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1361 amdgpu_ring_write(ring, mask); 1362 amdgpu_ring_write(ring, 1363 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1364 amdgpu_ring_write(ring, 12); 1365 } 1366 1367 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1368 unsigned vmid, uint64_t pd_addr) 1369 { 1370 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1371 uint32_t data0, data1, mask; 1372 1373 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1374 1375 /* wait for reg writes */ 1376 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1377 data1 = lower_32_bits(pd_addr); 1378 mask = 0xffffffff; 1379 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1380 } 1381 1382 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1383 { 1384 struct amdgpu_device *adev = ring->adev; 1385 int i; 1386 1387 WARN_ON(ring->wptr % 2 || count % 2); 1388 1389 for (i = 0; i < count / 2; i++) { 1390 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1391 amdgpu_ring_write(ring, 0); 1392 } 1393 } 1394 1395 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1396 { 1397 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1398 } 1399 1400 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1401 uint32_t reg, uint32_t val, 1402 uint32_t mask) 1403 { 1404 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1405 amdgpu_ring_write(ring, reg << 2); 1406 amdgpu_ring_write(ring, mask); 1407 amdgpu_ring_write(ring, val); 1408 } 1409 1410 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1411 unsigned int vmid, uint64_t pd_addr) 1412 { 1413 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1414 1415 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1416 1417 /* wait for reg writes */ 1418 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1419 lower_32_bits(pd_addr), 0xffffffff); 1420 } 1421 1422 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1423 uint32_t reg, uint32_t val) 1424 { 1425 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1426 amdgpu_ring_write(ring, reg << 2); 1427 amdgpu_ring_write(ring, val); 1428 } 1429 1430 #if 0 1431 static bool uvd_v7_0_is_idle(void *handle) 1432 { 1433 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1434 1435 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1436 } 1437 1438 static int uvd_v7_0_wait_for_idle(void *handle) 1439 { 1440 unsigned i; 1441 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1442 1443 for (i = 0; i < adev->usec_timeout; i++) { 1444 if (uvd_v7_0_is_idle(handle)) 1445 return 0; 1446 } 1447 return -ETIMEDOUT; 1448 } 1449 1450 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1451 static bool uvd_v7_0_check_soft_reset(void *handle) 1452 { 1453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1454 u32 srbm_soft_reset = 0; 1455 u32 tmp = RREG32(mmSRBM_STATUS); 1456 1457 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1458 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1459 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & 1460 AMDGPU_UVD_STATUS_BUSY_MASK)) 1461 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1462 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1463 1464 if (srbm_soft_reset) { 1465 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; 1466 return true; 1467 } else { 1468 adev->uvd.inst[ring->me].srbm_soft_reset = 0; 1469 return false; 1470 } 1471 } 1472 1473 static int uvd_v7_0_pre_soft_reset(void *handle) 1474 { 1475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1476 1477 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1478 return 0; 1479 1480 uvd_v7_0_stop(adev); 1481 return 0; 1482 } 1483 1484 static int uvd_v7_0_soft_reset(void *handle) 1485 { 1486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1487 u32 srbm_soft_reset; 1488 1489 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1490 return 0; 1491 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; 1492 1493 if (srbm_soft_reset) { 1494 u32 tmp; 1495 1496 tmp = RREG32(mmSRBM_SOFT_RESET); 1497 tmp |= srbm_soft_reset; 1498 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1499 WREG32(mmSRBM_SOFT_RESET, tmp); 1500 tmp = RREG32(mmSRBM_SOFT_RESET); 1501 1502 udelay(50); 1503 1504 tmp &= ~srbm_soft_reset; 1505 WREG32(mmSRBM_SOFT_RESET, tmp); 1506 tmp = RREG32(mmSRBM_SOFT_RESET); 1507 1508 /* Wait a little for things to settle down */ 1509 udelay(50); 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int uvd_v7_0_post_soft_reset(void *handle) 1516 { 1517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1518 1519 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1520 return 0; 1521 1522 mdelay(5); 1523 1524 return uvd_v7_0_start(adev); 1525 } 1526 #endif 1527 1528 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1529 struct amdgpu_irq_src *source, 1530 unsigned type, 1531 enum amdgpu_interrupt_state state) 1532 { 1533 // TODO 1534 return 0; 1535 } 1536 1537 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1538 struct amdgpu_irq_src *source, 1539 struct amdgpu_iv_entry *entry) 1540 { 1541 uint32_t ip_instance; 1542 1543 switch (entry->client_id) { 1544 case SOC15_IH_CLIENTID_UVD: 1545 ip_instance = 0; 1546 break; 1547 case SOC15_IH_CLIENTID_UVD1: 1548 ip_instance = 1; 1549 break; 1550 default: 1551 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1552 return 0; 1553 } 1554 1555 DRM_DEBUG("IH: UVD TRAP\n"); 1556 1557 switch (entry->src_id) { 1558 case 124: 1559 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1560 break; 1561 case 119: 1562 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1563 break; 1564 case 120: 1565 if (!amdgpu_sriov_vf(adev)) 1566 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1567 break; 1568 default: 1569 DRM_ERROR("Unhandled interrupt: %d %d\n", 1570 entry->src_id, entry->src_data[0]); 1571 break; 1572 } 1573 1574 return 0; 1575 } 1576 1577 #if 0 1578 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) 1579 { 1580 uint32_t data, data1, data2, suvd_flags; 1581 1582 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1583 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1584 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1585 1586 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1587 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1588 1589 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1590 UVD_SUVD_CGC_GATE__SIT_MASK | 1591 UVD_SUVD_CGC_GATE__SMP_MASK | 1592 UVD_SUVD_CGC_GATE__SCM_MASK | 1593 UVD_SUVD_CGC_GATE__SDB_MASK; 1594 1595 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1596 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1597 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1598 1599 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1600 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1601 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1602 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1603 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1604 UVD_CGC_CTRL__SYS_MODE_MASK | 1605 UVD_CGC_CTRL__UDEC_MODE_MASK | 1606 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1607 UVD_CGC_CTRL__REGS_MODE_MASK | 1608 UVD_CGC_CTRL__RBC_MODE_MASK | 1609 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1610 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1611 UVD_CGC_CTRL__IDCT_MODE_MASK | 1612 UVD_CGC_CTRL__MPRD_MODE_MASK | 1613 UVD_CGC_CTRL__MPC_MODE_MASK | 1614 UVD_CGC_CTRL__LBSI_MODE_MASK | 1615 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1616 UVD_CGC_CTRL__WCB_MODE_MASK | 1617 UVD_CGC_CTRL__VCPU_MODE_MASK | 1618 UVD_CGC_CTRL__JPEG_MODE_MASK | 1619 UVD_CGC_CTRL__JPEG2_MODE_MASK | 1620 UVD_CGC_CTRL__SCPU_MODE_MASK); 1621 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1622 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1623 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1624 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1625 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1626 data1 |= suvd_flags; 1627 1628 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); 1629 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); 1630 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1631 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); 1632 } 1633 1634 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) 1635 { 1636 uint32_t data, data1, cgc_flags, suvd_flags; 1637 1638 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); 1639 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1640 1641 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1642 UVD_CGC_GATE__UDEC_MASK | 1643 UVD_CGC_GATE__MPEG2_MASK | 1644 UVD_CGC_GATE__RBC_MASK | 1645 UVD_CGC_GATE__LMI_MC_MASK | 1646 UVD_CGC_GATE__IDCT_MASK | 1647 UVD_CGC_GATE__MPRD_MASK | 1648 UVD_CGC_GATE__MPC_MASK | 1649 UVD_CGC_GATE__LBSI_MASK | 1650 UVD_CGC_GATE__LRBBM_MASK | 1651 UVD_CGC_GATE__UDEC_RE_MASK | 1652 UVD_CGC_GATE__UDEC_CM_MASK | 1653 UVD_CGC_GATE__UDEC_IT_MASK | 1654 UVD_CGC_GATE__UDEC_DB_MASK | 1655 UVD_CGC_GATE__UDEC_MP_MASK | 1656 UVD_CGC_GATE__WCB_MASK | 1657 UVD_CGC_GATE__VCPU_MASK | 1658 UVD_CGC_GATE__SCPU_MASK | 1659 UVD_CGC_GATE__JPEG_MASK | 1660 UVD_CGC_GATE__JPEG2_MASK; 1661 1662 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1663 UVD_SUVD_CGC_GATE__SIT_MASK | 1664 UVD_SUVD_CGC_GATE__SMP_MASK | 1665 UVD_SUVD_CGC_GATE__SCM_MASK | 1666 UVD_SUVD_CGC_GATE__SDB_MASK; 1667 1668 data |= cgc_flags; 1669 data1 |= suvd_flags; 1670 1671 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); 1672 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1673 } 1674 1675 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 1676 { 1677 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1678 1679 if (enable) 1680 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1681 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1682 else 1683 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1684 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1685 1686 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 1687 } 1688 1689 1690 static int uvd_v7_0_set_clockgating_state(void *handle, 1691 enum amd_clockgating_state state) 1692 { 1693 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1694 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1695 1696 uvd_v7_0_set_bypass_mode(adev, enable); 1697 1698 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 1699 return 0; 1700 1701 if (enable) { 1702 /* disable HW gating and enable Sw gating */ 1703 uvd_v7_0_set_sw_clock_gating(adev); 1704 } else { 1705 /* wait for STATUS to clear */ 1706 if (uvd_v7_0_wait_for_idle(handle)) 1707 return -EBUSY; 1708 1709 /* enable HW gates because UVD is idle */ 1710 /* uvd_v7_0_set_hw_clock_gating(adev); */ 1711 } 1712 1713 return 0; 1714 } 1715 1716 static int uvd_v7_0_set_powergating_state(void *handle, 1717 enum amd_powergating_state state) 1718 { 1719 /* This doesn't actually powergate the UVD block. 1720 * That's done in the dpm code via the SMC. This 1721 * just re-inits the block as necessary. The actual 1722 * gating still happens in the dpm code. We should 1723 * revisit this when there is a cleaner line between 1724 * the smc and the hw blocks 1725 */ 1726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1727 1728 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1729 return 0; 1730 1731 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1732 1733 if (state == AMD_PG_STATE_GATE) { 1734 uvd_v7_0_stop(adev); 1735 return 0; 1736 } else { 1737 return uvd_v7_0_start(adev); 1738 } 1739 } 1740 #endif 1741 1742 static int uvd_v7_0_set_clockgating_state(void *handle, 1743 enum amd_clockgating_state state) 1744 { 1745 /* needed for driver unload*/ 1746 return 0; 1747 } 1748 1749 const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1750 .name = "uvd_v7_0", 1751 .early_init = uvd_v7_0_early_init, 1752 .late_init = NULL, 1753 .sw_init = uvd_v7_0_sw_init, 1754 .sw_fini = uvd_v7_0_sw_fini, 1755 .hw_init = uvd_v7_0_hw_init, 1756 .hw_fini = uvd_v7_0_hw_fini, 1757 .suspend = uvd_v7_0_suspend, 1758 .resume = uvd_v7_0_resume, 1759 .is_idle = NULL /* uvd_v7_0_is_idle */, 1760 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, 1761 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, 1762 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, 1763 .soft_reset = NULL /* uvd_v7_0_soft_reset */, 1764 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, 1765 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1766 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1767 }; 1768 1769 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1770 .type = AMDGPU_RING_TYPE_UVD, 1771 .align_mask = 0xf, 1772 .support_64bit_ptrs = false, 1773 .vmhub = AMDGPU_MMHUB, 1774 .get_rptr = uvd_v7_0_ring_get_rptr, 1775 .get_wptr = uvd_v7_0_ring_get_wptr, 1776 .set_wptr = uvd_v7_0_ring_set_wptr, 1777 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1778 .emit_frame_size = 1779 6 + /* hdp invalidate */ 1780 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1781 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1782 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1783 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1784 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1785 .emit_ib = uvd_v7_0_ring_emit_ib, 1786 .emit_fence = uvd_v7_0_ring_emit_fence, 1787 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1788 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1789 .test_ring = uvd_v7_0_ring_test_ring, 1790 .test_ib = amdgpu_uvd_ring_test_ib, 1791 .insert_nop = uvd_v7_0_ring_insert_nop, 1792 .pad_ib = amdgpu_ring_generic_pad_ib, 1793 .begin_use = amdgpu_uvd_ring_begin_use, 1794 .end_use = amdgpu_uvd_ring_end_use, 1795 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1796 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1797 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1798 }; 1799 1800 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1801 .type = AMDGPU_RING_TYPE_UVD_ENC, 1802 .align_mask = 0x3f, 1803 .nop = HEVC_ENC_CMD_NO_OP, 1804 .support_64bit_ptrs = false, 1805 .vmhub = AMDGPU_MMHUB, 1806 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1807 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1808 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1809 .emit_frame_size = 1810 3 + 3 + /* hdp flush / invalidate */ 1811 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1812 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1813 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1814 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1815 1, /* uvd_v7_0_enc_ring_insert_end */ 1816 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1817 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1818 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1819 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1820 .test_ring = uvd_v7_0_enc_ring_test_ring, 1821 .test_ib = uvd_v7_0_enc_ring_test_ib, 1822 .insert_nop = amdgpu_ring_insert_nop, 1823 .insert_end = uvd_v7_0_enc_ring_insert_end, 1824 .pad_ib = amdgpu_ring_generic_pad_ib, 1825 .begin_use = amdgpu_uvd_ring_begin_use, 1826 .end_use = amdgpu_uvd_ring_end_use, 1827 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1828 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1829 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1830 }; 1831 1832 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1833 { 1834 int i; 1835 1836 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1837 if (adev->uvd.harvest_config & (1 << i)) 1838 continue; 1839 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1840 adev->uvd.inst[i].ring.me = i; 1841 DRM_INFO("UVD(%d) is enabled in VM mode\n", i); 1842 } 1843 } 1844 1845 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1846 { 1847 int i, j; 1848 1849 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1850 if (adev->uvd.harvest_config & (1 << j)) 1851 continue; 1852 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1853 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1854 adev->uvd.inst[j].ring_enc[i].me = j; 1855 } 1856 1857 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); 1858 } 1859 } 1860 1861 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1862 .set = uvd_v7_0_set_interrupt_state, 1863 .process = uvd_v7_0_process_interrupt, 1864 }; 1865 1866 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1867 { 1868 int i; 1869 1870 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1871 if (adev->uvd.harvest_config & (1 << i)) 1872 continue; 1873 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1874 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1875 } 1876 } 1877 1878 const struct amdgpu_ip_block_version uvd_v7_0_ip_block = 1879 { 1880 .type = AMD_IP_BLOCK_TYPE_UVD, 1881 .major = 7, 1882 .minor = 0, 1883 .rev = 0, 1884 .funcs = &uvd_v7_0_ip_funcs, 1885 }; 1886