1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_uvd.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 #include "mmsch_v1_0.h" 32 33 #include "uvd/uvd_7_0_offset.h" 34 #include "uvd/uvd_7_0_sh_mask.h" 35 #include "vce/vce_4_0_offset.h" 36 #include "vce/vce_4_0_default.h" 37 #include "vce/vce_4_0_sh_mask.h" 38 #include "nbif/nbif_6_1_offset.h" 39 #include "hdp/hdp_4_0_offset.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "mmhub/mmhub_1_0_sh_mask.h" 42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 43 44 #define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 46 //UVD_PG0_CC_UVD_HARVESTING 47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 49 50 #define UVD7_MAX_HW_INSTANCES_VEGA20 2 51 52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int uvd_v7_0_start(struct amdgpu_device *adev); 56 static void uvd_v7_0_stop(struct amdgpu_device *adev); 57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 58 59 static int amdgpu_ih_clientid_uvds[] = { 60 SOC15_IH_CLIENTID_UVD, 61 SOC15_IH_CLIENTID_UVD1 62 }; 63 64 /** 65 * uvd_v7_0_ring_get_rptr - get read pointer 66 * 67 * @ring: amdgpu_ring pointer 68 * 69 * Returns the current hardware read pointer 70 */ 71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 72 { 73 struct amdgpu_device *adev = ring->adev; 74 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 76 } 77 78 /** 79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 80 * 81 * @ring: amdgpu_ring pointer 82 * 83 * Returns the current hardware enc read pointer 84 */ 85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 86 { 87 struct amdgpu_device *adev = ring->adev; 88 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 91 else 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 93 } 94 95 /** 96 * uvd_v7_0_ring_get_wptr - get write pointer 97 * 98 * @ring: amdgpu_ring pointer 99 * 100 * Returns the current hardware write pointer 101 */ 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 103 { 104 struct amdgpu_device *adev = ring->adev; 105 106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 107 } 108 109 /** 110 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 111 * 112 * @ring: amdgpu_ring pointer 113 * 114 * Returns the current hardware enc write pointer 115 */ 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 117 { 118 struct amdgpu_device *adev = ring->adev; 119 120 if (ring->use_doorbell) 121 return adev->wb.wb[ring->wptr_offs]; 122 123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 125 else 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 127 } 128 129 /** 130 * uvd_v7_0_ring_set_wptr - set write pointer 131 * 132 * @ring: amdgpu_ring pointer 133 * 134 * Commits the write pointer to the hardware 135 */ 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 137 { 138 struct amdgpu_device *adev = ring->adev; 139 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 141 } 142 143 /** 144 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 145 * 146 * @ring: amdgpu_ring pointer 147 * 148 * Commits the enc write pointer to the hardware 149 */ 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 151 { 152 struct amdgpu_device *adev = ring->adev; 153 154 if (ring->use_doorbell) { 155 /* XXX check if swapping is necessary on BE */ 156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 158 return; 159 } 160 161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 163 lower_32_bits(ring->wptr)); 164 else 165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 166 lower_32_bits(ring->wptr)); 167 } 168 169 /** 170 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 171 * 172 * @ring: the engine to test on 173 * 174 */ 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 176 { 177 struct amdgpu_device *adev = ring->adev; 178 uint32_t rptr = amdgpu_ring_get_rptr(ring); 179 unsigned i; 180 int r; 181 182 if (amdgpu_sriov_vf(adev)) 183 return 0; 184 185 r = amdgpu_ring_alloc(ring, 16); 186 if (r) 187 return r; 188 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 189 amdgpu_ring_commit(ring); 190 191 for (i = 0; i < adev->usec_timeout; i++) { 192 if (amdgpu_ring_get_rptr(ring) != rptr) 193 break; 194 DRM_UDELAY(1); 195 } 196 197 if (i >= adev->usec_timeout) 198 r = -ETIMEDOUT; 199 200 return r; 201 } 202 203 /** 204 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 205 * 206 * @adev: amdgpu_device pointer 207 * @ring: ring we should submit the msg to 208 * @handle: session handle to use 209 * @fence: optional fence to return 210 * 211 * Open up a stream for HW test 212 */ 213 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 214 struct dma_fence **fence) 215 { 216 const unsigned ib_size_dw = 16; 217 struct amdgpu_job *job; 218 struct amdgpu_ib *ib; 219 struct dma_fence *f = NULL; 220 uint64_t dummy; 221 int i, r; 222 223 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 224 if (r) 225 return r; 226 227 ib = &job->ibs[0]; 228 dummy = ib->gpu_addr + 1024; 229 230 ib->length_dw = 0; 231 ib->ptr[ib->length_dw++] = 0x00000018; 232 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 233 ib->ptr[ib->length_dw++] = handle; 234 ib->ptr[ib->length_dw++] = 0x00000000; 235 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 236 ib->ptr[ib->length_dw++] = dummy; 237 238 ib->ptr[ib->length_dw++] = 0x00000014; 239 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 240 ib->ptr[ib->length_dw++] = 0x0000001c; 241 ib->ptr[ib->length_dw++] = 0x00000000; 242 ib->ptr[ib->length_dw++] = 0x00000000; 243 244 ib->ptr[ib->length_dw++] = 0x00000008; 245 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 246 247 for (i = ib->length_dw; i < ib_size_dw; ++i) 248 ib->ptr[i] = 0x0; 249 250 r = amdgpu_job_submit_direct(job, ring, &f); 251 if (r) 252 goto err; 253 254 if (fence) 255 *fence = dma_fence_get(f); 256 dma_fence_put(f); 257 return 0; 258 259 err: 260 amdgpu_job_free(job); 261 return r; 262 } 263 264 /** 265 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 266 * 267 * @adev: amdgpu_device pointer 268 * @ring: ring we should submit the msg to 269 * @handle: session handle to use 270 * @fence: optional fence to return 271 * 272 * Close up a stream for HW test or if userspace failed to do so 273 */ 274 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 275 struct dma_fence **fence) 276 { 277 const unsigned ib_size_dw = 16; 278 struct amdgpu_job *job; 279 struct amdgpu_ib *ib; 280 struct dma_fence *f = NULL; 281 uint64_t dummy; 282 int i, r; 283 284 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 285 if (r) 286 return r; 287 288 ib = &job->ibs[0]; 289 dummy = ib->gpu_addr + 1024; 290 291 ib->length_dw = 0; 292 ib->ptr[ib->length_dw++] = 0x00000018; 293 ib->ptr[ib->length_dw++] = 0x00000001; 294 ib->ptr[ib->length_dw++] = handle; 295 ib->ptr[ib->length_dw++] = 0x00000000; 296 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 297 ib->ptr[ib->length_dw++] = dummy; 298 299 ib->ptr[ib->length_dw++] = 0x00000014; 300 ib->ptr[ib->length_dw++] = 0x00000002; 301 ib->ptr[ib->length_dw++] = 0x0000001c; 302 ib->ptr[ib->length_dw++] = 0x00000000; 303 ib->ptr[ib->length_dw++] = 0x00000000; 304 305 ib->ptr[ib->length_dw++] = 0x00000008; 306 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 307 308 for (i = ib->length_dw; i < ib_size_dw; ++i) 309 ib->ptr[i] = 0x0; 310 311 r = amdgpu_job_submit_direct(job, ring, &f); 312 if (r) 313 goto err; 314 315 if (fence) 316 *fence = dma_fence_get(f); 317 dma_fence_put(f); 318 return 0; 319 320 err: 321 amdgpu_job_free(job); 322 return r; 323 } 324 325 /** 326 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 327 * 328 * @ring: the engine to test on 329 * 330 */ 331 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 332 { 333 struct dma_fence *fence = NULL; 334 long r; 335 336 r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL); 337 if (r) 338 goto error; 339 340 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence); 341 if (r) 342 goto error; 343 344 r = dma_fence_wait_timeout(fence, false, timeout); 345 if (r == 0) 346 r = -ETIMEDOUT; 347 else if (r > 0) 348 r = 0; 349 350 error: 351 dma_fence_put(fence); 352 return r; 353 } 354 355 static int uvd_v7_0_early_init(void *handle) 356 { 357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 358 359 if (adev->asic_type == CHIP_VEGA20) { 360 u32 harvest; 361 int i; 362 363 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 364 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 365 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 366 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 367 adev->uvd.harvest_config |= 1 << i; 368 } 369 } 370 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 371 AMDGPU_UVD_HARVEST_UVD1)) 372 /* both instances are harvested, disable the block */ 373 return -ENOENT; 374 } else { 375 adev->uvd.num_uvd_inst = 1; 376 } 377 378 if (amdgpu_sriov_vf(adev)) 379 adev->uvd.num_enc_rings = 1; 380 else 381 adev->uvd.num_enc_rings = 2; 382 uvd_v7_0_set_ring_funcs(adev); 383 uvd_v7_0_set_enc_ring_funcs(adev); 384 uvd_v7_0_set_irq_funcs(adev); 385 386 return 0; 387 } 388 389 static int uvd_v7_0_sw_init(void *handle) 390 { 391 struct amdgpu_ring *ring; 392 393 int i, j, r; 394 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 395 396 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 397 if (adev->uvd.harvest_config & (1 << j)) 398 continue; 399 /* UVD TRAP */ 400 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 401 if (r) 402 return r; 403 404 /* UVD ENC TRAP */ 405 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 406 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 407 if (r) 408 return r; 409 } 410 } 411 412 r = amdgpu_uvd_sw_init(adev); 413 if (r) 414 return r; 415 416 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 417 const struct common_firmware_header *hdr; 418 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 419 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 420 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 421 adev->firmware.fw_size += 422 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 423 424 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { 425 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1; 426 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; 427 adev->firmware.fw_size += 428 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 429 } 430 DRM_INFO("PSP loading UVD firmware\n"); 431 } 432 433 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 434 if (adev->uvd.harvest_config & (1 << j)) 435 continue; 436 if (!amdgpu_sriov_vf(adev)) { 437 ring = &adev->uvd.inst[j].ring; 438 sprintf(ring->name, "uvd_%d", ring->me); 439 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); 440 if (r) 441 return r; 442 } 443 444 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 445 ring = &adev->uvd.inst[j].ring_enc[i]; 446 sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i); 447 if (amdgpu_sriov_vf(adev)) { 448 ring->use_doorbell = true; 449 450 /* currently only use the first enconding ring for 451 * sriov, so set unused location for other unused rings. 452 */ 453 if (i == 0) 454 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2; 455 else 456 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1; 457 } 458 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); 459 if (r) 460 return r; 461 } 462 } 463 464 r = amdgpu_uvd_resume(adev); 465 if (r) 466 return r; 467 468 r = amdgpu_uvd_entity_init(adev); 469 if (r) 470 return r; 471 472 r = amdgpu_virt_alloc_mm_table(adev); 473 if (r) 474 return r; 475 476 return r; 477 } 478 479 static int uvd_v7_0_sw_fini(void *handle) 480 { 481 int i, j, r; 482 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 483 484 amdgpu_virt_free_mm_table(adev); 485 486 r = amdgpu_uvd_suspend(adev); 487 if (r) 488 return r; 489 490 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 491 if (adev->uvd.harvest_config & (1 << j)) 492 continue; 493 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 494 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 495 } 496 return amdgpu_uvd_sw_fini(adev); 497 } 498 499 /** 500 * uvd_v7_0_hw_init - start and test UVD block 501 * 502 * @adev: amdgpu_device pointer 503 * 504 * Initialize the hardware, boot up the VCPU and do some testing 505 */ 506 static int uvd_v7_0_hw_init(void *handle) 507 { 508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 509 struct amdgpu_ring *ring; 510 uint32_t tmp; 511 int i, j, r; 512 513 if (amdgpu_sriov_vf(adev)) 514 r = uvd_v7_0_sriov_start(adev); 515 else 516 r = uvd_v7_0_start(adev); 517 if (r) 518 goto done; 519 520 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 521 if (adev->uvd.harvest_config & (1 << j)) 522 continue; 523 ring = &adev->uvd.inst[j].ring; 524 525 if (!amdgpu_sriov_vf(adev)) { 526 r = amdgpu_ring_test_helper(ring); 527 if (r) 528 goto done; 529 530 r = amdgpu_ring_alloc(ring, 10); 531 if (r) { 532 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); 533 goto done; 534 } 535 536 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 537 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 538 amdgpu_ring_write(ring, tmp); 539 amdgpu_ring_write(ring, 0xFFFFF); 540 541 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 542 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 543 amdgpu_ring_write(ring, tmp); 544 amdgpu_ring_write(ring, 0xFFFFF); 545 546 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 547 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 548 amdgpu_ring_write(ring, tmp); 549 amdgpu_ring_write(ring, 0xFFFFF); 550 551 /* Clear timeout status bits */ 552 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 553 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 554 amdgpu_ring_write(ring, 0x8); 555 556 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 557 mmUVD_SEMA_CNTL), 0)); 558 amdgpu_ring_write(ring, 3); 559 560 amdgpu_ring_commit(ring); 561 } 562 563 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 564 ring = &adev->uvd.inst[j].ring_enc[i]; 565 r = amdgpu_ring_test_helper(ring); 566 if (r) 567 goto done; 568 } 569 } 570 done: 571 if (!r) 572 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 573 574 return r; 575 } 576 577 /** 578 * uvd_v7_0_hw_fini - stop the hardware block 579 * 580 * @adev: amdgpu_device pointer 581 * 582 * Stop the UVD block, mark ring as not ready any more 583 */ 584 static int uvd_v7_0_hw_fini(void *handle) 585 { 586 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 587 int i; 588 589 if (!amdgpu_sriov_vf(adev)) 590 uvd_v7_0_stop(adev); 591 else { 592 /* full access mode, so don't touch any UVD register */ 593 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 594 } 595 596 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 597 if (adev->uvd.harvest_config & (1 << i)) 598 continue; 599 adev->uvd.inst[i].ring.sched.ready = false; 600 } 601 602 return 0; 603 } 604 605 static int uvd_v7_0_suspend(void *handle) 606 { 607 int r; 608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 609 610 r = uvd_v7_0_hw_fini(adev); 611 if (r) 612 return r; 613 614 return amdgpu_uvd_suspend(adev); 615 } 616 617 static int uvd_v7_0_resume(void *handle) 618 { 619 int r; 620 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 621 622 r = amdgpu_uvd_resume(adev); 623 if (r) 624 return r; 625 626 return uvd_v7_0_hw_init(adev); 627 } 628 629 /** 630 * uvd_v7_0_mc_resume - memory controller programming 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * Let the UVD memory controller know it's offsets 635 */ 636 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 637 { 638 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 639 uint32_t offset; 640 int i; 641 642 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 643 if (adev->uvd.harvest_config & (1 << i)) 644 continue; 645 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 646 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 647 i == 0 ? 648 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo: 649 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo); 650 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 651 i == 0 ? 652 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi: 653 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi); 654 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 655 offset = 0; 656 } else { 657 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 658 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 659 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 660 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 661 offset = size; 662 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 663 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 664 } 665 666 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 667 668 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 669 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 670 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 671 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 672 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 673 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 674 675 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 676 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 677 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 678 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 679 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 680 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 681 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 682 683 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 684 adev->gfx.config.gb_addr_config); 685 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 686 adev->gfx.config.gb_addr_config); 687 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 688 adev->gfx.config.gb_addr_config); 689 690 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 691 } 692 } 693 694 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 695 struct amdgpu_mm_table *table) 696 { 697 uint32_t data = 0, loop; 698 uint64_t addr = table->gpu_addr; 699 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 700 uint32_t size; 701 int i; 702 703 size = header->header_size + header->vce_table_size + header->uvd_table_size; 704 705 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 706 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 707 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 708 709 /* 2, update vmid of descriptor */ 710 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 711 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 712 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 713 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 714 715 /* 3, notify mmsch about the size of this descriptor */ 716 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 717 718 /* 4, set resp to zero */ 719 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 720 721 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 722 if (adev->uvd.harvest_config & (1 << i)) 723 continue; 724 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 725 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; 726 adev->uvd.inst[i].ring_enc[0].wptr = 0; 727 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 728 } 729 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 730 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 731 732 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 733 loop = 1000; 734 while ((data & 0x10000002) != 0x10000002) { 735 udelay(10); 736 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 737 loop--; 738 if (!loop) 739 break; 740 } 741 742 if (!loop) { 743 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 744 return -EBUSY; 745 } 746 747 return 0; 748 } 749 750 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 751 { 752 struct amdgpu_ring *ring; 753 uint32_t offset, size, tmp; 754 uint32_t table_size = 0; 755 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 756 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 757 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 758 struct mmsch_v1_0_cmd_end end = { {0} }; 759 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 760 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 761 uint8_t i = 0; 762 763 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 764 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 765 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 766 end.cmd_header.command_type = MMSCH_COMMAND__END; 767 768 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 769 header->version = MMSCH_VERSION; 770 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 771 772 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 773 header->uvd_table_offset = header->header_size; 774 else 775 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 776 777 init_table += header->uvd_table_offset; 778 779 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 780 if (adev->uvd.harvest_config & (1 << i)) 781 continue; 782 ring = &adev->uvd.inst[i].ring; 783 ring->wptr = 0; 784 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 785 786 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 787 0xFFFFFFFF, 0x00000004); 788 /* mc resume*/ 789 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 790 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 791 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 792 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo); 793 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 794 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 795 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi); 796 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); 797 offset = 0; 798 } else { 799 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 800 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 801 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 802 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 803 offset = size; 804 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 805 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 806 807 } 808 809 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 810 811 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 812 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 813 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 814 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 815 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 816 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 817 818 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 819 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 820 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 821 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 822 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 823 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 824 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 825 826 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 827 /* mc resume end*/ 828 829 /* disable clock gating */ 830 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 831 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 832 833 /* disable interupt */ 834 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 835 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 836 837 /* stall UMC and register bus before resetting VCPU */ 838 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 839 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 840 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 841 842 /* put LMI, VCPU, RBC etc... into reset */ 843 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 844 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 845 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 846 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 847 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 848 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 849 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 850 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 851 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 852 853 /* initialize UVD memory controller */ 854 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 855 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 856 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 857 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 858 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 859 UVD_LMI_CTRL__REQ_MODE_MASK | 860 0x00100000L)); 861 862 /* take all subblocks out of reset, except VCPU */ 863 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 864 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 865 866 /* enable VCPU clock */ 867 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 868 UVD_VCPU_CNTL__CLK_EN_MASK); 869 870 /* enable master interrupt */ 871 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 872 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 873 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 874 875 /* clear the bit 4 of UVD_STATUS */ 876 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 877 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 878 879 /* force RBC into idle state */ 880 size = order_base_2(ring->ring_size); 881 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 882 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 883 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 884 885 ring = &adev->uvd.inst[i].ring_enc[0]; 886 ring->wptr = 0; 887 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 888 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 889 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 890 891 /* boot up the VCPU */ 892 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 893 894 /* enable UMC */ 895 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 896 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 897 898 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 899 } 900 /* add end packet */ 901 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 902 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 903 header->uvd_table_size = table_size; 904 905 } 906 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 907 } 908 909 /** 910 * uvd_v7_0_start - start UVD block 911 * 912 * @adev: amdgpu_device pointer 913 * 914 * Setup and start the UVD block 915 */ 916 static int uvd_v7_0_start(struct amdgpu_device *adev) 917 { 918 struct amdgpu_ring *ring; 919 uint32_t rb_bufsz, tmp; 920 uint32_t lmi_swap_cntl; 921 uint32_t mp_swap_cntl; 922 int i, j, k, r; 923 924 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 925 if (adev->uvd.harvest_config & (1 << k)) 926 continue; 927 /* disable DPG */ 928 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 929 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 930 } 931 932 /* disable byte swapping */ 933 lmi_swap_cntl = 0; 934 mp_swap_cntl = 0; 935 936 uvd_v7_0_mc_resume(adev); 937 938 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 939 if (adev->uvd.harvest_config & (1 << k)) 940 continue; 941 ring = &adev->uvd.inst[k].ring; 942 /* disable clock gating */ 943 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 944 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 945 946 /* disable interupt */ 947 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 948 ~UVD_MASTINT_EN__VCPU_EN_MASK); 949 950 /* stall UMC and register bus before resetting VCPU */ 951 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 952 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 953 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 954 mdelay(1); 955 956 /* put LMI, VCPU, RBC etc... into reset */ 957 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 958 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 959 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 960 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 961 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 962 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 963 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 964 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 965 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 966 mdelay(5); 967 968 /* initialize UVD memory controller */ 969 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 970 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 971 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 972 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 973 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 974 UVD_LMI_CTRL__REQ_MODE_MASK | 975 0x00100000L); 976 977 #ifdef __BIG_ENDIAN 978 /* swap (8 in 32) RB and IB */ 979 lmi_swap_cntl = 0xa; 980 mp_swap_cntl = 0; 981 #endif 982 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 983 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 984 985 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 986 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 987 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 988 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 989 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 990 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 991 992 /* take all subblocks out of reset, except VCPU */ 993 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 994 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 995 mdelay(5); 996 997 /* enable VCPU clock */ 998 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 999 UVD_VCPU_CNTL__CLK_EN_MASK); 1000 1001 /* enable UMC */ 1002 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1003 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1004 1005 /* boot up the VCPU */ 1006 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1007 mdelay(10); 1008 1009 for (i = 0; i < 10; ++i) { 1010 uint32_t status; 1011 1012 for (j = 0; j < 100; ++j) { 1013 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1014 if (status & 2) 1015 break; 1016 mdelay(10); 1017 } 1018 r = 0; 1019 if (status & 2) 1020 break; 1021 1022 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1023 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1024 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1025 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1026 mdelay(10); 1027 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1028 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1029 mdelay(10); 1030 r = -1; 1031 } 1032 1033 if (r) { 1034 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1035 return r; 1036 } 1037 /* enable master interrupt */ 1038 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1039 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1040 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1041 1042 /* clear the bit 4 of UVD_STATUS */ 1043 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1044 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1045 1046 /* force RBC into idle state */ 1047 rb_bufsz = order_base_2(ring->ring_size); 1048 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1049 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1050 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1051 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1052 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1053 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1054 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1055 1056 /* set the write pointer delay */ 1057 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1058 1059 /* set the wb address */ 1060 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1061 (upper_32_bits(ring->gpu_addr) >> 2)); 1062 1063 /* programm the RB_BASE for ring buffer */ 1064 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1065 lower_32_bits(ring->gpu_addr)); 1066 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1067 upper_32_bits(ring->gpu_addr)); 1068 1069 /* Initialize the ring buffer's read and write pointers */ 1070 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1071 1072 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1073 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1074 lower_32_bits(ring->wptr)); 1075 1076 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1077 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1078 1079 ring = &adev->uvd.inst[k].ring_enc[0]; 1080 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1081 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1082 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1083 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1084 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1085 1086 ring = &adev->uvd.inst[k].ring_enc[1]; 1087 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1088 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1089 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1090 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1091 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1092 } 1093 return 0; 1094 } 1095 1096 /** 1097 * uvd_v7_0_stop - stop UVD block 1098 * 1099 * @adev: amdgpu_device pointer 1100 * 1101 * stop the UVD block 1102 */ 1103 static void uvd_v7_0_stop(struct amdgpu_device *adev) 1104 { 1105 uint8_t i = 0; 1106 1107 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1108 if (adev->uvd.harvest_config & (1 << i)) 1109 continue; 1110 /* force RBC into idle state */ 1111 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1112 1113 /* Stall UMC and register bus before resetting VCPU */ 1114 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1115 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1116 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1117 mdelay(1); 1118 1119 /* put VCPU into reset */ 1120 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1121 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1122 mdelay(5); 1123 1124 /* disable VCPU clock */ 1125 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1126 1127 /* Unstall UMC and register bus */ 1128 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1129 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1130 } 1131 } 1132 1133 /** 1134 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1135 * 1136 * @ring: amdgpu_ring pointer 1137 * @fence: fence to emit 1138 * 1139 * Write a fence and a trap command to the ring. 1140 */ 1141 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1142 unsigned flags) 1143 { 1144 struct amdgpu_device *adev = ring->adev; 1145 1146 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1147 1148 amdgpu_ring_write(ring, 1149 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1150 amdgpu_ring_write(ring, seq); 1151 amdgpu_ring_write(ring, 1152 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1153 amdgpu_ring_write(ring, addr & 0xffffffff); 1154 amdgpu_ring_write(ring, 1155 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1156 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1157 amdgpu_ring_write(ring, 1158 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1159 amdgpu_ring_write(ring, 0); 1160 1161 amdgpu_ring_write(ring, 1162 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1163 amdgpu_ring_write(ring, 0); 1164 amdgpu_ring_write(ring, 1165 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1166 amdgpu_ring_write(ring, 0); 1167 amdgpu_ring_write(ring, 1168 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1169 amdgpu_ring_write(ring, 2); 1170 } 1171 1172 /** 1173 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1174 * 1175 * @ring: amdgpu_ring pointer 1176 * @fence: fence to emit 1177 * 1178 * Write enc a fence and a trap command to the ring. 1179 */ 1180 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1181 u64 seq, unsigned flags) 1182 { 1183 1184 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1185 1186 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1187 amdgpu_ring_write(ring, addr); 1188 amdgpu_ring_write(ring, upper_32_bits(addr)); 1189 amdgpu_ring_write(ring, seq); 1190 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1191 } 1192 1193 /** 1194 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1195 * 1196 * @ring: amdgpu_ring pointer 1197 */ 1198 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1199 { 1200 /* The firmware doesn't seem to like touching registers at this point. */ 1201 } 1202 1203 /** 1204 * uvd_v7_0_ring_test_ring - register write test 1205 * 1206 * @ring: amdgpu_ring pointer 1207 * 1208 * Test if we can successfully write to the context register 1209 */ 1210 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1211 { 1212 struct amdgpu_device *adev = ring->adev; 1213 uint32_t tmp = 0; 1214 unsigned i; 1215 int r; 1216 1217 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1218 r = amdgpu_ring_alloc(ring, 3); 1219 if (r) 1220 return r; 1221 1222 amdgpu_ring_write(ring, 1223 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1224 amdgpu_ring_write(ring, 0xDEADBEEF); 1225 amdgpu_ring_commit(ring); 1226 for (i = 0; i < adev->usec_timeout; i++) { 1227 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1228 if (tmp == 0xDEADBEEF) 1229 break; 1230 DRM_UDELAY(1); 1231 } 1232 1233 if (i >= adev->usec_timeout) 1234 r = -ETIMEDOUT; 1235 1236 return r; 1237 } 1238 1239 /** 1240 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1241 * 1242 * @p: the CS parser with the IBs 1243 * @ib_idx: which IB to patch 1244 * 1245 */ 1246 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1247 uint32_t ib_idx) 1248 { 1249 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1250 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1251 unsigned i; 1252 1253 /* No patching necessary for the first instance */ 1254 if (!ring->me) 1255 return 0; 1256 1257 for (i = 0; i < ib->length_dw; i += 2) { 1258 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1259 1260 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1261 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1262 1263 amdgpu_set_ib_value(p, ib_idx, i, reg); 1264 } 1265 return 0; 1266 } 1267 1268 /** 1269 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1270 * 1271 * @ring: amdgpu_ring pointer 1272 * @ib: indirect buffer to execute 1273 * 1274 * Write ring commands to execute the indirect buffer 1275 */ 1276 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1277 struct amdgpu_job *job, 1278 struct amdgpu_ib *ib, 1279 uint32_t flags) 1280 { 1281 struct amdgpu_device *adev = ring->adev; 1282 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1283 1284 amdgpu_ring_write(ring, 1285 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1286 amdgpu_ring_write(ring, vmid); 1287 1288 amdgpu_ring_write(ring, 1289 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1290 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1291 amdgpu_ring_write(ring, 1292 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1293 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1294 amdgpu_ring_write(ring, 1295 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1296 amdgpu_ring_write(ring, ib->length_dw); 1297 } 1298 1299 /** 1300 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1301 * 1302 * @ring: amdgpu_ring pointer 1303 * @ib: indirect buffer to execute 1304 * 1305 * Write enc ring commands to execute the indirect buffer 1306 */ 1307 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1308 struct amdgpu_job *job, 1309 struct amdgpu_ib *ib, 1310 uint32_t flags) 1311 { 1312 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1313 1314 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1315 amdgpu_ring_write(ring, vmid); 1316 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1317 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1318 amdgpu_ring_write(ring, ib->length_dw); 1319 } 1320 1321 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1322 uint32_t reg, uint32_t val) 1323 { 1324 struct amdgpu_device *adev = ring->adev; 1325 1326 amdgpu_ring_write(ring, 1327 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1328 amdgpu_ring_write(ring, reg << 2); 1329 amdgpu_ring_write(ring, 1330 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1331 amdgpu_ring_write(ring, val); 1332 amdgpu_ring_write(ring, 1333 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1334 amdgpu_ring_write(ring, 8); 1335 } 1336 1337 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1338 uint32_t val, uint32_t mask) 1339 { 1340 struct amdgpu_device *adev = ring->adev; 1341 1342 amdgpu_ring_write(ring, 1343 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1344 amdgpu_ring_write(ring, reg << 2); 1345 amdgpu_ring_write(ring, 1346 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1347 amdgpu_ring_write(ring, val); 1348 amdgpu_ring_write(ring, 1349 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1350 amdgpu_ring_write(ring, mask); 1351 amdgpu_ring_write(ring, 1352 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1353 amdgpu_ring_write(ring, 12); 1354 } 1355 1356 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1357 unsigned vmid, uint64_t pd_addr) 1358 { 1359 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1360 uint32_t data0, data1, mask; 1361 1362 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1363 1364 /* wait for reg writes */ 1365 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1366 data1 = lower_32_bits(pd_addr); 1367 mask = 0xffffffff; 1368 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1369 } 1370 1371 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1372 { 1373 struct amdgpu_device *adev = ring->adev; 1374 int i; 1375 1376 WARN_ON(ring->wptr % 2 || count % 2); 1377 1378 for (i = 0; i < count / 2; i++) { 1379 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1380 amdgpu_ring_write(ring, 0); 1381 } 1382 } 1383 1384 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1385 { 1386 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1387 } 1388 1389 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1390 uint32_t reg, uint32_t val, 1391 uint32_t mask) 1392 { 1393 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1394 amdgpu_ring_write(ring, reg << 2); 1395 amdgpu_ring_write(ring, mask); 1396 amdgpu_ring_write(ring, val); 1397 } 1398 1399 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1400 unsigned int vmid, uint64_t pd_addr) 1401 { 1402 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1403 1404 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1405 1406 /* wait for reg writes */ 1407 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1408 lower_32_bits(pd_addr), 0xffffffff); 1409 } 1410 1411 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1412 uint32_t reg, uint32_t val) 1413 { 1414 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1415 amdgpu_ring_write(ring, reg << 2); 1416 amdgpu_ring_write(ring, val); 1417 } 1418 1419 #if 0 1420 static bool uvd_v7_0_is_idle(void *handle) 1421 { 1422 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1423 1424 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1425 } 1426 1427 static int uvd_v7_0_wait_for_idle(void *handle) 1428 { 1429 unsigned i; 1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1431 1432 for (i = 0; i < adev->usec_timeout; i++) { 1433 if (uvd_v7_0_is_idle(handle)) 1434 return 0; 1435 } 1436 return -ETIMEDOUT; 1437 } 1438 1439 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1440 static bool uvd_v7_0_check_soft_reset(void *handle) 1441 { 1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1443 u32 srbm_soft_reset = 0; 1444 u32 tmp = RREG32(mmSRBM_STATUS); 1445 1446 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1447 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1448 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & 1449 AMDGPU_UVD_STATUS_BUSY_MASK)) 1450 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1451 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1452 1453 if (srbm_soft_reset) { 1454 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; 1455 return true; 1456 } else { 1457 adev->uvd.inst[ring->me].srbm_soft_reset = 0; 1458 return false; 1459 } 1460 } 1461 1462 static int uvd_v7_0_pre_soft_reset(void *handle) 1463 { 1464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1465 1466 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1467 return 0; 1468 1469 uvd_v7_0_stop(adev); 1470 return 0; 1471 } 1472 1473 static int uvd_v7_0_soft_reset(void *handle) 1474 { 1475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1476 u32 srbm_soft_reset; 1477 1478 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1479 return 0; 1480 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; 1481 1482 if (srbm_soft_reset) { 1483 u32 tmp; 1484 1485 tmp = RREG32(mmSRBM_SOFT_RESET); 1486 tmp |= srbm_soft_reset; 1487 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1488 WREG32(mmSRBM_SOFT_RESET, tmp); 1489 tmp = RREG32(mmSRBM_SOFT_RESET); 1490 1491 udelay(50); 1492 1493 tmp &= ~srbm_soft_reset; 1494 WREG32(mmSRBM_SOFT_RESET, tmp); 1495 tmp = RREG32(mmSRBM_SOFT_RESET); 1496 1497 /* Wait a little for things to settle down */ 1498 udelay(50); 1499 } 1500 1501 return 0; 1502 } 1503 1504 static int uvd_v7_0_post_soft_reset(void *handle) 1505 { 1506 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1507 1508 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1509 return 0; 1510 1511 mdelay(5); 1512 1513 return uvd_v7_0_start(adev); 1514 } 1515 #endif 1516 1517 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1518 struct amdgpu_irq_src *source, 1519 unsigned type, 1520 enum amdgpu_interrupt_state state) 1521 { 1522 // TODO 1523 return 0; 1524 } 1525 1526 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1527 struct amdgpu_irq_src *source, 1528 struct amdgpu_iv_entry *entry) 1529 { 1530 uint32_t ip_instance; 1531 1532 switch (entry->client_id) { 1533 case SOC15_IH_CLIENTID_UVD: 1534 ip_instance = 0; 1535 break; 1536 case SOC15_IH_CLIENTID_UVD1: 1537 ip_instance = 1; 1538 break; 1539 default: 1540 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1541 return 0; 1542 } 1543 1544 DRM_DEBUG("IH: UVD TRAP\n"); 1545 1546 switch (entry->src_id) { 1547 case 124: 1548 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1549 break; 1550 case 119: 1551 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1552 break; 1553 case 120: 1554 if (!amdgpu_sriov_vf(adev)) 1555 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1556 break; 1557 default: 1558 DRM_ERROR("Unhandled interrupt: %d %d\n", 1559 entry->src_id, entry->src_data[0]); 1560 break; 1561 } 1562 1563 return 0; 1564 } 1565 1566 #if 0 1567 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) 1568 { 1569 uint32_t data, data1, data2, suvd_flags; 1570 1571 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1572 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1573 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1574 1575 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1576 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1577 1578 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1579 UVD_SUVD_CGC_GATE__SIT_MASK | 1580 UVD_SUVD_CGC_GATE__SMP_MASK | 1581 UVD_SUVD_CGC_GATE__SCM_MASK | 1582 UVD_SUVD_CGC_GATE__SDB_MASK; 1583 1584 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1585 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1586 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1587 1588 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1589 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1590 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1591 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1592 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1593 UVD_CGC_CTRL__SYS_MODE_MASK | 1594 UVD_CGC_CTRL__UDEC_MODE_MASK | 1595 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1596 UVD_CGC_CTRL__REGS_MODE_MASK | 1597 UVD_CGC_CTRL__RBC_MODE_MASK | 1598 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1599 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1600 UVD_CGC_CTRL__IDCT_MODE_MASK | 1601 UVD_CGC_CTRL__MPRD_MODE_MASK | 1602 UVD_CGC_CTRL__MPC_MODE_MASK | 1603 UVD_CGC_CTRL__LBSI_MODE_MASK | 1604 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1605 UVD_CGC_CTRL__WCB_MODE_MASK | 1606 UVD_CGC_CTRL__VCPU_MODE_MASK | 1607 UVD_CGC_CTRL__JPEG_MODE_MASK | 1608 UVD_CGC_CTRL__JPEG2_MODE_MASK | 1609 UVD_CGC_CTRL__SCPU_MODE_MASK); 1610 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1611 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1612 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1613 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1614 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1615 data1 |= suvd_flags; 1616 1617 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); 1618 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); 1619 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1620 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); 1621 } 1622 1623 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) 1624 { 1625 uint32_t data, data1, cgc_flags, suvd_flags; 1626 1627 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); 1628 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1629 1630 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1631 UVD_CGC_GATE__UDEC_MASK | 1632 UVD_CGC_GATE__MPEG2_MASK | 1633 UVD_CGC_GATE__RBC_MASK | 1634 UVD_CGC_GATE__LMI_MC_MASK | 1635 UVD_CGC_GATE__IDCT_MASK | 1636 UVD_CGC_GATE__MPRD_MASK | 1637 UVD_CGC_GATE__MPC_MASK | 1638 UVD_CGC_GATE__LBSI_MASK | 1639 UVD_CGC_GATE__LRBBM_MASK | 1640 UVD_CGC_GATE__UDEC_RE_MASK | 1641 UVD_CGC_GATE__UDEC_CM_MASK | 1642 UVD_CGC_GATE__UDEC_IT_MASK | 1643 UVD_CGC_GATE__UDEC_DB_MASK | 1644 UVD_CGC_GATE__UDEC_MP_MASK | 1645 UVD_CGC_GATE__WCB_MASK | 1646 UVD_CGC_GATE__VCPU_MASK | 1647 UVD_CGC_GATE__SCPU_MASK | 1648 UVD_CGC_GATE__JPEG_MASK | 1649 UVD_CGC_GATE__JPEG2_MASK; 1650 1651 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1652 UVD_SUVD_CGC_GATE__SIT_MASK | 1653 UVD_SUVD_CGC_GATE__SMP_MASK | 1654 UVD_SUVD_CGC_GATE__SCM_MASK | 1655 UVD_SUVD_CGC_GATE__SDB_MASK; 1656 1657 data |= cgc_flags; 1658 data1 |= suvd_flags; 1659 1660 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); 1661 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1662 } 1663 1664 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 1665 { 1666 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1667 1668 if (enable) 1669 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1670 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1671 else 1672 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1673 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1674 1675 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 1676 } 1677 1678 1679 static int uvd_v7_0_set_clockgating_state(void *handle, 1680 enum amd_clockgating_state state) 1681 { 1682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1683 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1684 1685 uvd_v7_0_set_bypass_mode(adev, enable); 1686 1687 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 1688 return 0; 1689 1690 if (enable) { 1691 /* disable HW gating and enable Sw gating */ 1692 uvd_v7_0_set_sw_clock_gating(adev); 1693 } else { 1694 /* wait for STATUS to clear */ 1695 if (uvd_v7_0_wait_for_idle(handle)) 1696 return -EBUSY; 1697 1698 /* enable HW gates because UVD is idle */ 1699 /* uvd_v7_0_set_hw_clock_gating(adev); */ 1700 } 1701 1702 return 0; 1703 } 1704 1705 static int uvd_v7_0_set_powergating_state(void *handle, 1706 enum amd_powergating_state state) 1707 { 1708 /* This doesn't actually powergate the UVD block. 1709 * That's done in the dpm code via the SMC. This 1710 * just re-inits the block as necessary. The actual 1711 * gating still happens in the dpm code. We should 1712 * revisit this when there is a cleaner line between 1713 * the smc and the hw blocks 1714 */ 1715 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1716 1717 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1718 return 0; 1719 1720 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1721 1722 if (state == AMD_PG_STATE_GATE) { 1723 uvd_v7_0_stop(adev); 1724 return 0; 1725 } else { 1726 return uvd_v7_0_start(adev); 1727 } 1728 } 1729 #endif 1730 1731 static int uvd_v7_0_set_clockgating_state(void *handle, 1732 enum amd_clockgating_state state) 1733 { 1734 /* needed for driver unload*/ 1735 return 0; 1736 } 1737 1738 const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1739 .name = "uvd_v7_0", 1740 .early_init = uvd_v7_0_early_init, 1741 .late_init = NULL, 1742 .sw_init = uvd_v7_0_sw_init, 1743 .sw_fini = uvd_v7_0_sw_fini, 1744 .hw_init = uvd_v7_0_hw_init, 1745 .hw_fini = uvd_v7_0_hw_fini, 1746 .suspend = uvd_v7_0_suspend, 1747 .resume = uvd_v7_0_resume, 1748 .is_idle = NULL /* uvd_v7_0_is_idle */, 1749 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, 1750 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, 1751 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, 1752 .soft_reset = NULL /* uvd_v7_0_soft_reset */, 1753 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, 1754 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1755 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1756 }; 1757 1758 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1759 .type = AMDGPU_RING_TYPE_UVD, 1760 .align_mask = 0xf, 1761 .support_64bit_ptrs = false, 1762 .vmhub = AMDGPU_MMHUB, 1763 .get_rptr = uvd_v7_0_ring_get_rptr, 1764 .get_wptr = uvd_v7_0_ring_get_wptr, 1765 .set_wptr = uvd_v7_0_ring_set_wptr, 1766 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1767 .emit_frame_size = 1768 6 + /* hdp invalidate */ 1769 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1770 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1771 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1772 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1773 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1774 .emit_ib = uvd_v7_0_ring_emit_ib, 1775 .emit_fence = uvd_v7_0_ring_emit_fence, 1776 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1777 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1778 .test_ring = uvd_v7_0_ring_test_ring, 1779 .test_ib = amdgpu_uvd_ring_test_ib, 1780 .insert_nop = uvd_v7_0_ring_insert_nop, 1781 .pad_ib = amdgpu_ring_generic_pad_ib, 1782 .begin_use = amdgpu_uvd_ring_begin_use, 1783 .end_use = amdgpu_uvd_ring_end_use, 1784 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1785 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1786 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1787 }; 1788 1789 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1790 .type = AMDGPU_RING_TYPE_UVD_ENC, 1791 .align_mask = 0x3f, 1792 .nop = HEVC_ENC_CMD_NO_OP, 1793 .support_64bit_ptrs = false, 1794 .vmhub = AMDGPU_MMHUB, 1795 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1796 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1797 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1798 .emit_frame_size = 1799 3 + 3 + /* hdp flush / invalidate */ 1800 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1801 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1802 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1803 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1804 1, /* uvd_v7_0_enc_ring_insert_end */ 1805 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1806 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1807 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1808 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1809 .test_ring = uvd_v7_0_enc_ring_test_ring, 1810 .test_ib = uvd_v7_0_enc_ring_test_ib, 1811 .insert_nop = amdgpu_ring_insert_nop, 1812 .insert_end = uvd_v7_0_enc_ring_insert_end, 1813 .pad_ib = amdgpu_ring_generic_pad_ib, 1814 .begin_use = amdgpu_uvd_ring_begin_use, 1815 .end_use = amdgpu_uvd_ring_end_use, 1816 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1817 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1818 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1819 }; 1820 1821 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1822 { 1823 int i; 1824 1825 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1826 if (adev->uvd.harvest_config & (1 << i)) 1827 continue; 1828 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1829 adev->uvd.inst[i].ring.me = i; 1830 DRM_INFO("UVD(%d) is enabled in VM mode\n", i); 1831 } 1832 } 1833 1834 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1835 { 1836 int i, j; 1837 1838 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1839 if (adev->uvd.harvest_config & (1 << j)) 1840 continue; 1841 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1842 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1843 adev->uvd.inst[j].ring_enc[i].me = j; 1844 } 1845 1846 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); 1847 } 1848 } 1849 1850 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1851 .set = uvd_v7_0_set_interrupt_state, 1852 .process = uvd_v7_0_process_interrupt, 1853 }; 1854 1855 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1856 { 1857 int i; 1858 1859 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1860 if (adev->uvd.harvest_config & (1 << i)) 1861 continue; 1862 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1863 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1864 } 1865 } 1866 1867 const struct amdgpu_ip_block_version uvd_v7_0_ip_block = 1868 { 1869 .type = AMD_IP_BLOCK_TYPE_UVD, 1870 .major = 7, 1871 .minor = 0, 1872 .rev = 0, 1873 .funcs = &uvd_v7_0_ip_funcs, 1874 }; 1875