1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_6_0_d.h" 31 #include "uvd/uvd_6_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 #include "smu/smu_7_1_3_d.h" 35 #include "smu/smu_7_1_3_sh_mask.h" 36 #include "bif/bif_5_1_d.h" 37 #include "gmc/gmc_8_1_d.h" 38 #include "vi.h" 39 #include "ivsrcid/ivsrcid_vislands30.h" 40 41 /* Polaris10/11/12 firmware version */ 42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8)) 43 44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); 45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev); 46 47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); 48 static int uvd_v6_0_start(struct amdgpu_device *adev); 49 static void uvd_v6_0_stop(struct amdgpu_device *adev); 50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); 51 static int uvd_v6_0_set_clockgating_state(void *handle, 52 enum amd_clockgating_state state); 53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, 54 bool enable); 55 56 /** 57 * uvd_v6_0_enc_support - get encode support status 58 * 59 * @adev: amdgpu_device pointer 60 * 61 * Returns the current hardware encode support status 62 */ 63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev) 64 { 65 return ((adev->asic_type >= CHIP_POLARIS10) && 66 (adev->asic_type <= CHIP_VEGAM) && 67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); 68 } 69 70 /** 71 * uvd_v6_0_ring_get_rptr - get read pointer 72 * 73 * @ring: amdgpu_ring pointer 74 * 75 * Returns the current hardware read pointer 76 */ 77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 78 { 79 struct amdgpu_device *adev = ring->adev; 80 81 return RREG32(mmUVD_RBC_RB_RPTR); 82 } 83 84 /** 85 * uvd_v6_0_enc_ring_get_rptr - get enc read pointer 86 * 87 * @ring: amdgpu_ring pointer 88 * 89 * Returns the current hardware enc read pointer 90 */ 91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 92 { 93 struct amdgpu_device *adev = ring->adev; 94 95 if (ring == &adev->uvd.inst->ring_enc[0]) 96 return RREG32(mmUVD_RB_RPTR); 97 else 98 return RREG32(mmUVD_RB_RPTR2); 99 } 100 /** 101 * uvd_v6_0_ring_get_wptr - get write pointer 102 * 103 * @ring: amdgpu_ring pointer 104 * 105 * Returns the current hardware write pointer 106 */ 107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 108 { 109 struct amdgpu_device *adev = ring->adev; 110 111 return RREG32(mmUVD_RBC_RB_WPTR); 112 } 113 114 /** 115 * uvd_v6_0_enc_ring_get_wptr - get enc write pointer 116 * 117 * @ring: amdgpu_ring pointer 118 * 119 * Returns the current hardware enc write pointer 120 */ 121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 122 { 123 struct amdgpu_device *adev = ring->adev; 124 125 if (ring == &adev->uvd.inst->ring_enc[0]) 126 return RREG32(mmUVD_RB_WPTR); 127 else 128 return RREG32(mmUVD_RB_WPTR2); 129 } 130 131 /** 132 * uvd_v6_0_ring_set_wptr - set write pointer 133 * 134 * @ring: amdgpu_ring pointer 135 * 136 * Commits the write pointer to the hardware 137 */ 138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 139 { 140 struct amdgpu_device *adev = ring->adev; 141 142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 143 } 144 145 /** 146 * uvd_v6_0_enc_ring_set_wptr - set enc write pointer 147 * 148 * @ring: amdgpu_ring pointer 149 * 150 * Commits the enc write pointer to the hardware 151 */ 152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 153 { 154 struct amdgpu_device *adev = ring->adev; 155 156 if (ring == &adev->uvd.inst->ring_enc[0]) 157 WREG32(mmUVD_RB_WPTR, 158 lower_32_bits(ring->wptr)); 159 else 160 WREG32(mmUVD_RB_WPTR2, 161 lower_32_bits(ring->wptr)); 162 } 163 164 /** 165 * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working 166 * 167 * @ring: the engine to test on 168 * 169 */ 170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) 171 { 172 struct amdgpu_device *adev = ring->adev; 173 uint32_t rptr = amdgpu_ring_get_rptr(ring); 174 unsigned i; 175 int r; 176 177 r = amdgpu_ring_alloc(ring, 16); 178 if (r) { 179 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n", 180 ring->idx, r); 181 return r; 182 } 183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 184 amdgpu_ring_commit(ring); 185 186 for (i = 0; i < adev->usec_timeout; i++) { 187 if (amdgpu_ring_get_rptr(ring) != rptr) 188 break; 189 DRM_UDELAY(1); 190 } 191 192 if (i < adev->usec_timeout) { 193 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 194 ring->idx, i); 195 } else { 196 DRM_ERROR("amdgpu: ring %d test failed\n", 197 ring->idx); 198 r = -ETIMEDOUT; 199 } 200 201 return r; 202 } 203 204 /** 205 * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg 206 * 207 * @adev: amdgpu_device pointer 208 * @ring: ring we should submit the msg to 209 * @handle: session handle to use 210 * @fence: optional fence to return 211 * 212 * Open up a stream for HW test 213 */ 214 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 215 struct dma_fence **fence) 216 { 217 const unsigned ib_size_dw = 16; 218 struct amdgpu_job *job; 219 struct amdgpu_ib *ib; 220 struct dma_fence *f = NULL; 221 uint64_t dummy; 222 int i, r; 223 224 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 225 if (r) 226 return r; 227 228 ib = &job->ibs[0]; 229 dummy = ib->gpu_addr + 1024; 230 231 ib->length_dw = 0; 232 ib->ptr[ib->length_dw++] = 0x00000018; 233 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 234 ib->ptr[ib->length_dw++] = handle; 235 ib->ptr[ib->length_dw++] = 0x00010000; 236 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 237 ib->ptr[ib->length_dw++] = dummy; 238 239 ib->ptr[ib->length_dw++] = 0x00000014; 240 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 241 ib->ptr[ib->length_dw++] = 0x0000001c; 242 ib->ptr[ib->length_dw++] = 0x00000001; 243 ib->ptr[ib->length_dw++] = 0x00000000; 244 245 ib->ptr[ib->length_dw++] = 0x00000008; 246 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 247 248 for (i = ib->length_dw; i < ib_size_dw; ++i) 249 ib->ptr[i] = 0x0; 250 251 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 252 job->fence = dma_fence_get(f); 253 if (r) 254 goto err; 255 256 amdgpu_job_free(job); 257 if (fence) 258 *fence = dma_fence_get(f); 259 dma_fence_put(f); 260 return 0; 261 262 err: 263 amdgpu_job_free(job); 264 return r; 265 } 266 267 /** 268 * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 269 * 270 * @adev: amdgpu_device pointer 271 * @ring: ring we should submit the msg to 272 * @handle: session handle to use 273 * @fence: optional fence to return 274 * 275 * Close up a stream for HW test or if userspace failed to do so 276 */ 277 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, 278 uint32_t handle, 279 bool direct, struct dma_fence **fence) 280 { 281 const unsigned ib_size_dw = 16; 282 struct amdgpu_job *job; 283 struct amdgpu_ib *ib; 284 struct dma_fence *f = NULL; 285 uint64_t dummy; 286 int i, r; 287 288 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 289 if (r) 290 return r; 291 292 ib = &job->ibs[0]; 293 dummy = ib->gpu_addr + 1024; 294 295 ib->length_dw = 0; 296 ib->ptr[ib->length_dw++] = 0x00000018; 297 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 298 ib->ptr[ib->length_dw++] = handle; 299 ib->ptr[ib->length_dw++] = 0x00010000; 300 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 301 ib->ptr[ib->length_dw++] = dummy; 302 303 ib->ptr[ib->length_dw++] = 0x00000014; 304 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 305 ib->ptr[ib->length_dw++] = 0x0000001c; 306 ib->ptr[ib->length_dw++] = 0x00000001; 307 ib->ptr[ib->length_dw++] = 0x00000000; 308 309 ib->ptr[ib->length_dw++] = 0x00000008; 310 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 311 312 for (i = ib->length_dw; i < ib_size_dw; ++i) 313 ib->ptr[i] = 0x0; 314 315 if (direct) { 316 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 317 job->fence = dma_fence_get(f); 318 if (r) 319 goto err; 320 321 amdgpu_job_free(job); 322 } else { 323 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity, 324 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 325 if (r) 326 goto err; 327 } 328 329 if (fence) 330 *fence = dma_fence_get(f); 331 dma_fence_put(f); 332 return 0; 333 334 err: 335 amdgpu_job_free(job); 336 return r; 337 } 338 339 /** 340 * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working 341 * 342 * @ring: the engine to test on 343 * 344 */ 345 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 346 { 347 struct dma_fence *fence = NULL; 348 long r; 349 350 r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL); 351 if (r) { 352 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); 353 goto error; 354 } 355 356 r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence); 357 if (r) { 358 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); 359 goto error; 360 } 361 362 r = dma_fence_wait_timeout(fence, false, timeout); 363 if (r == 0) { 364 DRM_ERROR("amdgpu: IB test timed out.\n"); 365 r = -ETIMEDOUT; 366 } else if (r < 0) { 367 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 368 } else { 369 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 370 r = 0; 371 } 372 error: 373 dma_fence_put(fence); 374 return r; 375 } 376 static int uvd_v6_0_early_init(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 adev->uvd.num_uvd_inst = 1; 380 381 if (!(adev->flags & AMD_IS_APU) && 382 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) 383 return -ENOENT; 384 385 uvd_v6_0_set_ring_funcs(adev); 386 387 if (uvd_v6_0_enc_support(adev)) { 388 adev->uvd.num_enc_rings = 2; 389 uvd_v6_0_set_enc_ring_funcs(adev); 390 } 391 392 uvd_v6_0_set_irq_funcs(adev); 393 394 return 0; 395 } 396 397 static int uvd_v6_0_sw_init(void *handle) 398 { 399 struct amdgpu_ring *ring; 400 int i, r; 401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 402 403 /* UVD TRAP */ 404 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 405 if (r) 406 return r; 407 408 /* UVD ENC TRAP */ 409 if (uvd_v6_0_enc_support(adev)) { 410 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 411 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq); 412 if (r) 413 return r; 414 } 415 } 416 417 r = amdgpu_uvd_sw_init(adev); 418 if (r) 419 return r; 420 421 if (!uvd_v6_0_enc_support(adev)) { 422 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 423 adev->uvd.inst->ring_enc[i].funcs = NULL; 424 425 adev->uvd.inst->irq.num_types = 1; 426 adev->uvd.num_enc_rings = 0; 427 428 DRM_INFO("UVD ENC is disabled\n"); 429 } else { 430 struct drm_sched_rq *rq; 431 ring = &adev->uvd.inst->ring_enc[0]; 432 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 433 r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst->entity_enc, 434 rq, NULL); 435 if (r) { 436 DRM_ERROR("Failed setting up UVD ENC run queue.\n"); 437 return r; 438 } 439 } 440 441 r = amdgpu_uvd_resume(adev); 442 if (r) 443 return r; 444 445 ring = &adev->uvd.inst->ring; 446 sprintf(ring->name, "uvd"); 447 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 448 if (r) 449 return r; 450 451 if (uvd_v6_0_enc_support(adev)) { 452 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 453 ring = &adev->uvd.inst->ring_enc[i]; 454 sprintf(ring->name, "uvd_enc%d", i); 455 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 456 if (r) 457 return r; 458 } 459 } 460 461 return r; 462 } 463 464 static int uvd_v6_0_sw_fini(void *handle) 465 { 466 int i, r; 467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468 469 r = amdgpu_uvd_suspend(adev); 470 if (r) 471 return r; 472 473 if (uvd_v6_0_enc_support(adev)) { 474 drm_sched_entity_destroy(&adev->uvd.inst->ring_enc[0].sched, &adev->uvd.inst->entity_enc); 475 476 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 477 amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]); 478 } 479 480 return amdgpu_uvd_sw_fini(adev); 481 } 482 483 /** 484 * uvd_v6_0_hw_init - start and test UVD block 485 * 486 * @adev: amdgpu_device pointer 487 * 488 * Initialize the hardware, boot up the VCPU and do some testing 489 */ 490 static int uvd_v6_0_hw_init(void *handle) 491 { 492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 493 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 494 uint32_t tmp; 495 int i, r; 496 497 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 498 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 499 uvd_v6_0_enable_mgcg(adev, true); 500 501 ring->ready = true; 502 r = amdgpu_ring_test_ring(ring); 503 if (r) { 504 ring->ready = false; 505 goto done; 506 } 507 508 r = amdgpu_ring_alloc(ring, 10); 509 if (r) { 510 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 511 goto done; 512 } 513 514 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 515 amdgpu_ring_write(ring, tmp); 516 amdgpu_ring_write(ring, 0xFFFFF); 517 518 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 519 amdgpu_ring_write(ring, tmp); 520 amdgpu_ring_write(ring, 0xFFFFF); 521 522 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 523 amdgpu_ring_write(ring, tmp); 524 amdgpu_ring_write(ring, 0xFFFFF); 525 526 /* Clear timeout status bits */ 527 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 528 amdgpu_ring_write(ring, 0x8); 529 530 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 531 amdgpu_ring_write(ring, 3); 532 533 amdgpu_ring_commit(ring); 534 535 if (uvd_v6_0_enc_support(adev)) { 536 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 537 ring = &adev->uvd.inst->ring_enc[i]; 538 ring->ready = true; 539 r = amdgpu_ring_test_ring(ring); 540 if (r) { 541 ring->ready = false; 542 goto done; 543 } 544 } 545 } 546 547 done: 548 if (!r) { 549 if (uvd_v6_0_enc_support(adev)) 550 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 551 else 552 DRM_INFO("UVD initialized successfully.\n"); 553 } 554 555 return r; 556 } 557 558 /** 559 * uvd_v6_0_hw_fini - stop the hardware block 560 * 561 * @adev: amdgpu_device pointer 562 * 563 * Stop the UVD block, mark ring as not ready any more 564 */ 565 static int uvd_v6_0_hw_fini(void *handle) 566 { 567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 568 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 569 570 if (RREG32(mmUVD_STATUS) != 0) 571 uvd_v6_0_stop(adev); 572 573 ring->ready = false; 574 575 return 0; 576 } 577 578 static int uvd_v6_0_suspend(void *handle) 579 { 580 int r; 581 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 582 583 r = uvd_v6_0_hw_fini(adev); 584 if (r) 585 return r; 586 587 return amdgpu_uvd_suspend(adev); 588 } 589 590 static int uvd_v6_0_resume(void *handle) 591 { 592 int r; 593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 594 595 r = amdgpu_uvd_resume(adev); 596 if (r) 597 return r; 598 599 return uvd_v6_0_hw_init(adev); 600 } 601 602 /** 603 * uvd_v6_0_mc_resume - memory controller programming 604 * 605 * @adev: amdgpu_device pointer 606 * 607 * Let the UVD memory controller know it's offsets 608 */ 609 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 610 { 611 uint64_t offset; 612 uint32_t size; 613 614 /* programm memory controller bits 0-27 */ 615 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 616 lower_32_bits(adev->uvd.inst->gpu_addr)); 617 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 618 upper_32_bits(adev->uvd.inst->gpu_addr)); 619 620 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 621 size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 622 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 623 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 624 625 offset += size; 626 size = AMDGPU_UVD_HEAP_SIZE; 627 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 628 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 629 630 offset += size; 631 size = AMDGPU_UVD_STACK_SIZE + 632 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 633 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 634 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 635 636 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 637 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 638 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 639 640 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 641 } 642 643 #if 0 644 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 645 bool enable) 646 { 647 u32 data, data1; 648 649 data = RREG32(mmUVD_CGC_GATE); 650 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 651 if (enable) { 652 data |= UVD_CGC_GATE__SYS_MASK | 653 UVD_CGC_GATE__UDEC_MASK | 654 UVD_CGC_GATE__MPEG2_MASK | 655 UVD_CGC_GATE__RBC_MASK | 656 UVD_CGC_GATE__LMI_MC_MASK | 657 UVD_CGC_GATE__IDCT_MASK | 658 UVD_CGC_GATE__MPRD_MASK | 659 UVD_CGC_GATE__MPC_MASK | 660 UVD_CGC_GATE__LBSI_MASK | 661 UVD_CGC_GATE__LRBBM_MASK | 662 UVD_CGC_GATE__UDEC_RE_MASK | 663 UVD_CGC_GATE__UDEC_CM_MASK | 664 UVD_CGC_GATE__UDEC_IT_MASK | 665 UVD_CGC_GATE__UDEC_DB_MASK | 666 UVD_CGC_GATE__UDEC_MP_MASK | 667 UVD_CGC_GATE__WCB_MASK | 668 UVD_CGC_GATE__VCPU_MASK | 669 UVD_CGC_GATE__SCPU_MASK; 670 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 671 UVD_SUVD_CGC_GATE__SIT_MASK | 672 UVD_SUVD_CGC_GATE__SMP_MASK | 673 UVD_SUVD_CGC_GATE__SCM_MASK | 674 UVD_SUVD_CGC_GATE__SDB_MASK | 675 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 676 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 677 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 678 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 679 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 680 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 681 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 682 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 683 } else { 684 data &= ~(UVD_CGC_GATE__SYS_MASK | 685 UVD_CGC_GATE__UDEC_MASK | 686 UVD_CGC_GATE__MPEG2_MASK | 687 UVD_CGC_GATE__RBC_MASK | 688 UVD_CGC_GATE__LMI_MC_MASK | 689 UVD_CGC_GATE__LMI_UMC_MASK | 690 UVD_CGC_GATE__IDCT_MASK | 691 UVD_CGC_GATE__MPRD_MASK | 692 UVD_CGC_GATE__MPC_MASK | 693 UVD_CGC_GATE__LBSI_MASK | 694 UVD_CGC_GATE__LRBBM_MASK | 695 UVD_CGC_GATE__UDEC_RE_MASK | 696 UVD_CGC_GATE__UDEC_CM_MASK | 697 UVD_CGC_GATE__UDEC_IT_MASK | 698 UVD_CGC_GATE__UDEC_DB_MASK | 699 UVD_CGC_GATE__UDEC_MP_MASK | 700 UVD_CGC_GATE__WCB_MASK | 701 UVD_CGC_GATE__VCPU_MASK | 702 UVD_CGC_GATE__SCPU_MASK); 703 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 704 UVD_SUVD_CGC_GATE__SIT_MASK | 705 UVD_SUVD_CGC_GATE__SMP_MASK | 706 UVD_SUVD_CGC_GATE__SCM_MASK | 707 UVD_SUVD_CGC_GATE__SDB_MASK | 708 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 709 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 710 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 711 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 712 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 713 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 714 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 715 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); 716 } 717 WREG32(mmUVD_CGC_GATE, data); 718 WREG32(mmUVD_SUVD_CGC_GATE, data1); 719 } 720 #endif 721 722 /** 723 * uvd_v6_0_start - start UVD block 724 * 725 * @adev: amdgpu_device pointer 726 * 727 * Setup and start the UVD block 728 */ 729 static int uvd_v6_0_start(struct amdgpu_device *adev) 730 { 731 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 732 uint32_t rb_bufsz, tmp; 733 uint32_t lmi_swap_cntl; 734 uint32_t mp_swap_cntl; 735 int i, j, r; 736 737 /* disable DPG */ 738 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 739 740 /* disable byte swapping */ 741 lmi_swap_cntl = 0; 742 mp_swap_cntl = 0; 743 744 uvd_v6_0_mc_resume(adev); 745 746 /* disable interupt */ 747 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); 748 749 /* stall UMC and register bus before resetting VCPU */ 750 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); 751 mdelay(1); 752 753 /* put LMI, VCPU, RBC etc... into reset */ 754 WREG32(mmUVD_SOFT_RESET, 755 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 756 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 757 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 758 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 759 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 760 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 761 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 762 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 763 mdelay(5); 764 765 /* take UVD block out of reset */ 766 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); 767 mdelay(5); 768 769 /* initialize UVD memory controller */ 770 WREG32(mmUVD_LMI_CTRL, 771 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 772 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 773 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 774 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 775 UVD_LMI_CTRL__REQ_MODE_MASK | 776 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK); 777 778 #ifdef __BIG_ENDIAN 779 /* swap (8 in 32) RB and IB */ 780 lmi_swap_cntl = 0xa; 781 mp_swap_cntl = 0; 782 #endif 783 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 784 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 785 786 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 787 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 788 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 789 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 790 WREG32(mmUVD_MPC_SET_ALU, 0); 791 WREG32(mmUVD_MPC_SET_MUX, 0x88); 792 793 /* take all subblocks out of reset, except VCPU */ 794 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 795 mdelay(5); 796 797 /* enable VCPU clock */ 798 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 799 800 /* enable UMC */ 801 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); 802 803 /* boot up the VCPU */ 804 WREG32(mmUVD_SOFT_RESET, 0); 805 mdelay(10); 806 807 for (i = 0; i < 10; ++i) { 808 uint32_t status; 809 810 for (j = 0; j < 100; ++j) { 811 status = RREG32(mmUVD_STATUS); 812 if (status & 2) 813 break; 814 mdelay(10); 815 } 816 r = 0; 817 if (status & 2) 818 break; 819 820 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 821 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); 822 mdelay(10); 823 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); 824 mdelay(10); 825 r = -1; 826 } 827 828 if (r) { 829 DRM_ERROR("UVD not responding, giving up!!!\n"); 830 return r; 831 } 832 /* enable master interrupt */ 833 WREG32_P(mmUVD_MASTINT_EN, 834 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 835 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 836 837 /* clear the bit 4 of UVD_STATUS */ 838 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 839 840 /* force RBC into idle state */ 841 rb_bufsz = order_base_2(ring->ring_size); 842 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 843 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 844 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 845 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 846 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 847 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 848 WREG32(mmUVD_RBC_RB_CNTL, tmp); 849 850 /* set the write pointer delay */ 851 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 852 853 /* set the wb address */ 854 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 855 856 /* programm the RB_BASE for ring buffer */ 857 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 858 lower_32_bits(ring->gpu_addr)); 859 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 860 upper_32_bits(ring->gpu_addr)); 861 862 /* Initialize the ring buffer's read and write pointers */ 863 WREG32(mmUVD_RBC_RB_RPTR, 0); 864 865 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 866 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 867 868 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); 869 870 if (uvd_v6_0_enc_support(adev)) { 871 ring = &adev->uvd.inst->ring_enc[0]; 872 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 873 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 874 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); 875 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 876 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4); 877 878 ring = &adev->uvd.inst->ring_enc[1]; 879 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 880 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 881 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); 882 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 883 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4); 884 } 885 886 return 0; 887 } 888 889 /** 890 * uvd_v6_0_stop - stop UVD block 891 * 892 * @adev: amdgpu_device pointer 893 * 894 * stop the UVD block 895 */ 896 static void uvd_v6_0_stop(struct amdgpu_device *adev) 897 { 898 /* force RBC into idle state */ 899 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 900 901 /* Stall UMC and register bus before resetting VCPU */ 902 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 903 mdelay(1); 904 905 /* put VCPU into reset */ 906 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 907 mdelay(5); 908 909 /* disable VCPU clock */ 910 WREG32(mmUVD_VCPU_CNTL, 0x0); 911 912 /* Unstall UMC and register bus */ 913 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 914 915 WREG32(mmUVD_STATUS, 0); 916 } 917 918 /** 919 * uvd_v6_0_ring_emit_fence - emit an fence & trap command 920 * 921 * @ring: amdgpu_ring pointer 922 * @fence: fence to emit 923 * 924 * Write a fence and a trap command to the ring. 925 */ 926 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 927 unsigned flags) 928 { 929 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 930 931 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 932 amdgpu_ring_write(ring, seq); 933 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 934 amdgpu_ring_write(ring, addr & 0xffffffff); 935 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 936 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 937 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 938 amdgpu_ring_write(ring, 0); 939 940 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 941 amdgpu_ring_write(ring, 0); 942 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 943 amdgpu_ring_write(ring, 0); 944 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 945 amdgpu_ring_write(ring, 2); 946 } 947 948 /** 949 * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command 950 * 951 * @ring: amdgpu_ring pointer 952 * @fence: fence to emit 953 * 954 * Write enc a fence and a trap command to the ring. 955 */ 956 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 957 u64 seq, unsigned flags) 958 { 959 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 960 961 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 962 amdgpu_ring_write(ring, addr); 963 amdgpu_ring_write(ring, upper_32_bits(addr)); 964 amdgpu_ring_write(ring, seq); 965 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 966 } 967 968 /** 969 * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing 970 * 971 * @ring: amdgpu_ring pointer 972 */ 973 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 974 { 975 /* The firmware doesn't seem to like touching registers at this point. */ 976 } 977 978 /** 979 * uvd_v6_0_ring_test_ring - register write test 980 * 981 * @ring: amdgpu_ring pointer 982 * 983 * Test if we can successfully write to the context register 984 */ 985 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) 986 { 987 struct amdgpu_device *adev = ring->adev; 988 uint32_t tmp = 0; 989 unsigned i; 990 int r; 991 992 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 993 r = amdgpu_ring_alloc(ring, 3); 994 if (r) { 995 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 996 ring->idx, r); 997 return r; 998 } 999 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 1000 amdgpu_ring_write(ring, 0xDEADBEEF); 1001 amdgpu_ring_commit(ring); 1002 for (i = 0; i < adev->usec_timeout; i++) { 1003 tmp = RREG32(mmUVD_CONTEXT_ID); 1004 if (tmp == 0xDEADBEEF) 1005 break; 1006 DRM_UDELAY(1); 1007 } 1008 1009 if (i < adev->usec_timeout) { 1010 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 1011 ring->idx, i); 1012 } else { 1013 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 1014 ring->idx, tmp); 1015 r = -EINVAL; 1016 } 1017 return r; 1018 } 1019 1020 /** 1021 * uvd_v6_0_ring_emit_ib - execute indirect buffer 1022 * 1023 * @ring: amdgpu_ring pointer 1024 * @ib: indirect buffer to execute 1025 * 1026 * Write ring commands to execute the indirect buffer 1027 */ 1028 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1029 struct amdgpu_ib *ib, 1030 unsigned vmid, bool ctx_switch) 1031 { 1032 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); 1033 amdgpu_ring_write(ring, vmid); 1034 1035 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 1036 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1037 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 1038 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1039 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 1040 amdgpu_ring_write(ring, ib->length_dw); 1041 } 1042 1043 /** 1044 * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer 1045 * 1046 * @ring: amdgpu_ring pointer 1047 * @ib: indirect buffer to execute 1048 * 1049 * Write enc ring commands to execute the indirect buffer 1050 */ 1051 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1052 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) 1053 { 1054 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1055 amdgpu_ring_write(ring, vmid); 1056 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1057 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1058 amdgpu_ring_write(ring, ib->length_dw); 1059 } 1060 1061 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1062 uint32_t reg, uint32_t val) 1063 { 1064 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1065 amdgpu_ring_write(ring, reg << 2); 1066 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1067 amdgpu_ring_write(ring, val); 1068 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1069 amdgpu_ring_write(ring, 0x8); 1070 } 1071 1072 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1073 unsigned vmid, uint64_t pd_addr) 1074 { 1075 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1076 1077 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1078 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1079 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1080 amdgpu_ring_write(ring, 0); 1081 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1082 amdgpu_ring_write(ring, 1 << vmid); /* mask */ 1083 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1084 amdgpu_ring_write(ring, 0xC); 1085 } 1086 1087 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1088 { 1089 uint32_t seq = ring->fence_drv.sync_seq; 1090 uint64_t addr = ring->fence_drv.gpu_addr; 1091 1092 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1093 amdgpu_ring_write(ring, lower_32_bits(addr)); 1094 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1095 amdgpu_ring_write(ring, upper_32_bits(addr)); 1096 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1097 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1098 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); 1099 amdgpu_ring_write(ring, seq); 1100 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1101 amdgpu_ring_write(ring, 0xE); 1102 } 1103 1104 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1105 { 1106 int i; 1107 1108 WARN_ON(ring->wptr % 2 || count % 2); 1109 1110 for (i = 0; i < count / 2; i++) { 1111 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 1112 amdgpu_ring_write(ring, 0); 1113 } 1114 } 1115 1116 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1117 { 1118 uint32_t seq = ring->fence_drv.sync_seq; 1119 uint64_t addr = ring->fence_drv.gpu_addr; 1120 1121 amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE); 1122 amdgpu_ring_write(ring, lower_32_bits(addr)); 1123 amdgpu_ring_write(ring, upper_32_bits(addr)); 1124 amdgpu_ring_write(ring, seq); 1125 } 1126 1127 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1128 { 1129 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1130 } 1131 1132 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1133 unsigned int vmid, uint64_t pd_addr) 1134 { 1135 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB); 1136 amdgpu_ring_write(ring, vmid); 1137 amdgpu_ring_write(ring, pd_addr >> 12); 1138 1139 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB); 1140 amdgpu_ring_write(ring, vmid); 1141 } 1142 1143 static bool uvd_v6_0_is_idle(void *handle) 1144 { 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 1147 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1148 } 1149 1150 static int uvd_v6_0_wait_for_idle(void *handle) 1151 { 1152 unsigned i; 1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1154 1155 for (i = 0; i < adev->usec_timeout; i++) { 1156 if (uvd_v6_0_is_idle(handle)) 1157 return 0; 1158 } 1159 return -ETIMEDOUT; 1160 } 1161 1162 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1163 static bool uvd_v6_0_check_soft_reset(void *handle) 1164 { 1165 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1166 u32 srbm_soft_reset = 0; 1167 u32 tmp = RREG32(mmSRBM_STATUS); 1168 1169 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1170 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1171 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) 1172 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1173 1174 if (srbm_soft_reset) { 1175 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset; 1176 return true; 1177 } else { 1178 adev->uvd.inst->srbm_soft_reset = 0; 1179 return false; 1180 } 1181 } 1182 1183 static int uvd_v6_0_pre_soft_reset(void *handle) 1184 { 1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186 1187 if (!adev->uvd.inst->srbm_soft_reset) 1188 return 0; 1189 1190 uvd_v6_0_stop(adev); 1191 return 0; 1192 } 1193 1194 static int uvd_v6_0_soft_reset(void *handle) 1195 { 1196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1197 u32 srbm_soft_reset; 1198 1199 if (!adev->uvd.inst->srbm_soft_reset) 1200 return 0; 1201 srbm_soft_reset = adev->uvd.inst->srbm_soft_reset; 1202 1203 if (srbm_soft_reset) { 1204 u32 tmp; 1205 1206 tmp = RREG32(mmSRBM_SOFT_RESET); 1207 tmp |= srbm_soft_reset; 1208 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1209 WREG32(mmSRBM_SOFT_RESET, tmp); 1210 tmp = RREG32(mmSRBM_SOFT_RESET); 1211 1212 udelay(50); 1213 1214 tmp &= ~srbm_soft_reset; 1215 WREG32(mmSRBM_SOFT_RESET, tmp); 1216 tmp = RREG32(mmSRBM_SOFT_RESET); 1217 1218 /* Wait a little for things to settle down */ 1219 udelay(50); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int uvd_v6_0_post_soft_reset(void *handle) 1226 { 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1228 1229 if (!adev->uvd.inst->srbm_soft_reset) 1230 return 0; 1231 1232 mdelay(5); 1233 1234 return uvd_v6_0_start(adev); 1235 } 1236 1237 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 1238 struct amdgpu_irq_src *source, 1239 unsigned type, 1240 enum amdgpu_interrupt_state state) 1241 { 1242 // TODO 1243 return 0; 1244 } 1245 1246 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, 1247 struct amdgpu_irq_src *source, 1248 struct amdgpu_iv_entry *entry) 1249 { 1250 bool int_handled = true; 1251 DRM_DEBUG("IH: UVD TRAP\n"); 1252 1253 switch (entry->src_id) { 1254 case 124: 1255 amdgpu_fence_process(&adev->uvd.inst->ring); 1256 break; 1257 case 119: 1258 if (likely(uvd_v6_0_enc_support(adev))) 1259 amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]); 1260 else 1261 int_handled = false; 1262 break; 1263 case 120: 1264 if (likely(uvd_v6_0_enc_support(adev))) 1265 amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]); 1266 else 1267 int_handled = false; 1268 break; 1269 } 1270 1271 if (false == int_handled) 1272 DRM_ERROR("Unhandled interrupt: %d %d\n", 1273 entry->src_id, entry->src_data[0]); 1274 1275 return 0; 1276 } 1277 1278 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 1279 { 1280 uint32_t data1, data3; 1281 1282 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 1283 data3 = RREG32(mmUVD_CGC_GATE); 1284 1285 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 1286 UVD_SUVD_CGC_GATE__SIT_MASK | 1287 UVD_SUVD_CGC_GATE__SMP_MASK | 1288 UVD_SUVD_CGC_GATE__SCM_MASK | 1289 UVD_SUVD_CGC_GATE__SDB_MASK | 1290 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 1291 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 1292 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 1293 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 1294 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 1295 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 1296 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 1297 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 1298 1299 if (enable) { 1300 data3 |= (UVD_CGC_GATE__SYS_MASK | 1301 UVD_CGC_GATE__UDEC_MASK | 1302 UVD_CGC_GATE__MPEG2_MASK | 1303 UVD_CGC_GATE__RBC_MASK | 1304 UVD_CGC_GATE__LMI_MC_MASK | 1305 UVD_CGC_GATE__LMI_UMC_MASK | 1306 UVD_CGC_GATE__IDCT_MASK | 1307 UVD_CGC_GATE__MPRD_MASK | 1308 UVD_CGC_GATE__MPC_MASK | 1309 UVD_CGC_GATE__LBSI_MASK | 1310 UVD_CGC_GATE__LRBBM_MASK | 1311 UVD_CGC_GATE__UDEC_RE_MASK | 1312 UVD_CGC_GATE__UDEC_CM_MASK | 1313 UVD_CGC_GATE__UDEC_IT_MASK | 1314 UVD_CGC_GATE__UDEC_DB_MASK | 1315 UVD_CGC_GATE__UDEC_MP_MASK | 1316 UVD_CGC_GATE__WCB_MASK | 1317 UVD_CGC_GATE__JPEG_MASK | 1318 UVD_CGC_GATE__SCPU_MASK | 1319 UVD_CGC_GATE__JPEG2_MASK); 1320 /* only in pg enabled, we can gate clock to vcpu*/ 1321 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1322 data3 |= UVD_CGC_GATE__VCPU_MASK; 1323 1324 data3 &= ~UVD_CGC_GATE__REGS_MASK; 1325 } else { 1326 data3 = 0; 1327 } 1328 1329 WREG32(mmUVD_SUVD_CGC_GATE, data1); 1330 WREG32(mmUVD_CGC_GATE, data3); 1331 } 1332 1333 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) 1334 { 1335 uint32_t data, data2; 1336 1337 data = RREG32(mmUVD_CGC_CTRL); 1338 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 1339 1340 1341 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1342 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1343 1344 1345 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1346 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1347 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1348 1349 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1350 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1351 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1352 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1353 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1354 UVD_CGC_CTRL__SYS_MODE_MASK | 1355 UVD_CGC_CTRL__UDEC_MODE_MASK | 1356 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1357 UVD_CGC_CTRL__REGS_MODE_MASK | 1358 UVD_CGC_CTRL__RBC_MODE_MASK | 1359 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1360 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1361 UVD_CGC_CTRL__IDCT_MODE_MASK | 1362 UVD_CGC_CTRL__MPRD_MODE_MASK | 1363 UVD_CGC_CTRL__MPC_MODE_MASK | 1364 UVD_CGC_CTRL__LBSI_MODE_MASK | 1365 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1366 UVD_CGC_CTRL__WCB_MODE_MASK | 1367 UVD_CGC_CTRL__VCPU_MODE_MASK | 1368 UVD_CGC_CTRL__JPEG_MODE_MASK | 1369 UVD_CGC_CTRL__SCPU_MODE_MASK | 1370 UVD_CGC_CTRL__JPEG2_MODE_MASK); 1371 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1372 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1373 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1374 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1375 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1376 1377 WREG32(mmUVD_CGC_CTRL, data); 1378 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 1379 } 1380 1381 #if 0 1382 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 1383 { 1384 uint32_t data, data1, cgc_flags, suvd_flags; 1385 1386 data = RREG32(mmUVD_CGC_GATE); 1387 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 1388 1389 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1390 UVD_CGC_GATE__UDEC_MASK | 1391 UVD_CGC_GATE__MPEG2_MASK | 1392 UVD_CGC_GATE__RBC_MASK | 1393 UVD_CGC_GATE__LMI_MC_MASK | 1394 UVD_CGC_GATE__IDCT_MASK | 1395 UVD_CGC_GATE__MPRD_MASK | 1396 UVD_CGC_GATE__MPC_MASK | 1397 UVD_CGC_GATE__LBSI_MASK | 1398 UVD_CGC_GATE__LRBBM_MASK | 1399 UVD_CGC_GATE__UDEC_RE_MASK | 1400 UVD_CGC_GATE__UDEC_CM_MASK | 1401 UVD_CGC_GATE__UDEC_IT_MASK | 1402 UVD_CGC_GATE__UDEC_DB_MASK | 1403 UVD_CGC_GATE__UDEC_MP_MASK | 1404 UVD_CGC_GATE__WCB_MASK | 1405 UVD_CGC_GATE__VCPU_MASK | 1406 UVD_CGC_GATE__SCPU_MASK | 1407 UVD_CGC_GATE__JPEG_MASK | 1408 UVD_CGC_GATE__JPEG2_MASK; 1409 1410 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1411 UVD_SUVD_CGC_GATE__SIT_MASK | 1412 UVD_SUVD_CGC_GATE__SMP_MASK | 1413 UVD_SUVD_CGC_GATE__SCM_MASK | 1414 UVD_SUVD_CGC_GATE__SDB_MASK; 1415 1416 data |= cgc_flags; 1417 data1 |= suvd_flags; 1418 1419 WREG32(mmUVD_CGC_GATE, data); 1420 WREG32(mmUVD_SUVD_CGC_GATE, data1); 1421 } 1422 #endif 1423 1424 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, 1425 bool enable) 1426 { 1427 u32 orig, data; 1428 1429 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 1430 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 1431 data |= 0xfff; 1432 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 1433 1434 orig = data = RREG32(mmUVD_CGC_CTRL); 1435 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1436 if (orig != data) 1437 WREG32(mmUVD_CGC_CTRL, data); 1438 } else { 1439 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 1440 data &= ~0xfff; 1441 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 1442 1443 orig = data = RREG32(mmUVD_CGC_CTRL); 1444 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1445 if (orig != data) 1446 WREG32(mmUVD_CGC_CTRL, data); 1447 } 1448 } 1449 1450 static int uvd_v6_0_set_clockgating_state(void *handle, 1451 enum amd_clockgating_state state) 1452 { 1453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1454 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1455 1456 if (enable) { 1457 /* wait for STATUS to clear */ 1458 if (uvd_v6_0_wait_for_idle(handle)) 1459 return -EBUSY; 1460 uvd_v6_0_enable_clock_gating(adev, true); 1461 /* enable HW gates because UVD is idle */ 1462 /* uvd_v6_0_set_hw_clock_gating(adev); */ 1463 } else { 1464 /* disable HW gating and enable Sw gating */ 1465 uvd_v6_0_enable_clock_gating(adev, false); 1466 } 1467 uvd_v6_0_set_sw_clock_gating(adev); 1468 return 0; 1469 } 1470 1471 static int uvd_v6_0_set_powergating_state(void *handle, 1472 enum amd_powergating_state state) 1473 { 1474 /* This doesn't actually powergate the UVD block. 1475 * That's done in the dpm code via the SMC. This 1476 * just re-inits the block as necessary. The actual 1477 * gating still happens in the dpm code. We should 1478 * revisit this when there is a cleaner line between 1479 * the smc and the hw blocks 1480 */ 1481 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1482 int ret = 0; 1483 1484 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1485 1486 if (state == AMD_PG_STATE_GATE) { 1487 uvd_v6_0_stop(adev); 1488 } else { 1489 ret = uvd_v6_0_start(adev); 1490 if (ret) 1491 goto out; 1492 } 1493 1494 out: 1495 return ret; 1496 } 1497 1498 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags) 1499 { 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1501 int data; 1502 1503 mutex_lock(&adev->pm.mutex); 1504 1505 if (adev->flags & AMD_IS_APU) 1506 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); 1507 else 1508 data = RREG32_SMC(ixCURRENT_PG_STATUS); 1509 1510 if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 1511 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 1512 goto out; 1513 } 1514 1515 /* AMD_CG_SUPPORT_UVD_MGCG */ 1516 data = RREG32(mmUVD_CGC_CTRL); 1517 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 1518 *flags |= AMD_CG_SUPPORT_UVD_MGCG; 1519 1520 out: 1521 mutex_unlock(&adev->pm.mutex); 1522 } 1523 1524 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 1525 .name = "uvd_v6_0", 1526 .early_init = uvd_v6_0_early_init, 1527 .late_init = NULL, 1528 .sw_init = uvd_v6_0_sw_init, 1529 .sw_fini = uvd_v6_0_sw_fini, 1530 .hw_init = uvd_v6_0_hw_init, 1531 .hw_fini = uvd_v6_0_hw_fini, 1532 .suspend = uvd_v6_0_suspend, 1533 .resume = uvd_v6_0_resume, 1534 .is_idle = uvd_v6_0_is_idle, 1535 .wait_for_idle = uvd_v6_0_wait_for_idle, 1536 .check_soft_reset = uvd_v6_0_check_soft_reset, 1537 .pre_soft_reset = uvd_v6_0_pre_soft_reset, 1538 .soft_reset = uvd_v6_0_soft_reset, 1539 .post_soft_reset = uvd_v6_0_post_soft_reset, 1540 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 1541 .set_powergating_state = uvd_v6_0_set_powergating_state, 1542 .get_clockgating_state = uvd_v6_0_get_clockgating_state, 1543 }; 1544 1545 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { 1546 .type = AMDGPU_RING_TYPE_UVD, 1547 .align_mask = 0xf, 1548 .support_64bit_ptrs = false, 1549 .get_rptr = uvd_v6_0_ring_get_rptr, 1550 .get_wptr = uvd_v6_0_ring_get_wptr, 1551 .set_wptr = uvd_v6_0_ring_set_wptr, 1552 .parse_cs = amdgpu_uvd_ring_parse_cs, 1553 .emit_frame_size = 1554 6 + /* hdp invalidate */ 1555 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ 1556 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ 1557 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ 1558 .emit_ib = uvd_v6_0_ring_emit_ib, 1559 .emit_fence = uvd_v6_0_ring_emit_fence, 1560 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1561 .test_ring = uvd_v6_0_ring_test_ring, 1562 .test_ib = amdgpu_uvd_ring_test_ib, 1563 .insert_nop = uvd_v6_0_ring_insert_nop, 1564 .pad_ib = amdgpu_ring_generic_pad_ib, 1565 .begin_use = amdgpu_uvd_ring_begin_use, 1566 .end_use = amdgpu_uvd_ring_end_use, 1567 .emit_wreg = uvd_v6_0_ring_emit_wreg, 1568 }; 1569 1570 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { 1571 .type = AMDGPU_RING_TYPE_UVD, 1572 .align_mask = 0xf, 1573 .support_64bit_ptrs = false, 1574 .get_rptr = uvd_v6_0_ring_get_rptr, 1575 .get_wptr = uvd_v6_0_ring_get_wptr, 1576 .set_wptr = uvd_v6_0_ring_set_wptr, 1577 .emit_frame_size = 1578 6 + /* hdp invalidate */ 1579 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ 1580 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */ 1581 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ 1582 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ 1583 .emit_ib = uvd_v6_0_ring_emit_ib, 1584 .emit_fence = uvd_v6_0_ring_emit_fence, 1585 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, 1586 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync, 1587 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1588 .test_ring = uvd_v6_0_ring_test_ring, 1589 .test_ib = amdgpu_uvd_ring_test_ib, 1590 .insert_nop = uvd_v6_0_ring_insert_nop, 1591 .pad_ib = amdgpu_ring_generic_pad_ib, 1592 .begin_use = amdgpu_uvd_ring_begin_use, 1593 .end_use = amdgpu_uvd_ring_end_use, 1594 .emit_wreg = uvd_v6_0_ring_emit_wreg, 1595 }; 1596 1597 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { 1598 .type = AMDGPU_RING_TYPE_UVD_ENC, 1599 .align_mask = 0x3f, 1600 .nop = HEVC_ENC_CMD_NO_OP, 1601 .support_64bit_ptrs = false, 1602 .get_rptr = uvd_v6_0_enc_ring_get_rptr, 1603 .get_wptr = uvd_v6_0_enc_ring_get_wptr, 1604 .set_wptr = uvd_v6_0_enc_ring_set_wptr, 1605 .emit_frame_size = 1606 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ 1607 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */ 1608 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ 1609 1, /* uvd_v6_0_enc_ring_insert_end */ 1610 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */ 1611 .emit_ib = uvd_v6_0_enc_ring_emit_ib, 1612 .emit_fence = uvd_v6_0_enc_ring_emit_fence, 1613 .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush, 1614 .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync, 1615 .test_ring = uvd_v6_0_enc_ring_test_ring, 1616 .test_ib = uvd_v6_0_enc_ring_test_ib, 1617 .insert_nop = amdgpu_ring_insert_nop, 1618 .insert_end = uvd_v6_0_enc_ring_insert_end, 1619 .pad_ib = amdgpu_ring_generic_pad_ib, 1620 .begin_use = amdgpu_uvd_ring_begin_use, 1621 .end_use = amdgpu_uvd_ring_end_use, 1622 }; 1623 1624 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1625 { 1626 if (adev->asic_type >= CHIP_POLARIS10) { 1627 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs; 1628 DRM_INFO("UVD is enabled in VM mode\n"); 1629 } else { 1630 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs; 1631 DRM_INFO("UVD is enabled in physical mode\n"); 1632 } 1633 } 1634 1635 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1636 { 1637 int i; 1638 1639 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 1640 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs; 1641 1642 DRM_INFO("UVD ENC is enabled in VM mode\n"); 1643 } 1644 1645 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { 1646 .set = uvd_v6_0_set_interrupt_state, 1647 .process = uvd_v6_0_process_interrupt, 1648 }; 1649 1650 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1651 { 1652 if (uvd_v6_0_enc_support(adev)) 1653 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; 1654 else 1655 adev->uvd.inst->irq.num_types = 1; 1656 1657 adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs; 1658 } 1659 1660 const struct amdgpu_ip_block_version uvd_v6_0_ip_block = 1661 { 1662 .type = AMD_IP_BLOCK_TYPE_UVD, 1663 .major = 6, 1664 .minor = 0, 1665 .rev = 0, 1666 .funcs = &uvd_v6_0_ip_funcs, 1667 }; 1668 1669 const struct amdgpu_ip_block_version uvd_v6_2_ip_block = 1670 { 1671 .type = AMD_IP_BLOCK_TYPE_UVD, 1672 .major = 6, 1673 .minor = 2, 1674 .rev = 0, 1675 .funcs = &uvd_v6_0_ip_funcs, 1676 }; 1677 1678 const struct amdgpu_ip_block_version uvd_v6_3_ip_block = 1679 { 1680 .type = AMD_IP_BLOCK_TYPE_UVD, 1681 .major = 6, 1682 .minor = 3, 1683 .rev = 0, 1684 .funcs = &uvd_v6_0_ip_funcs, 1685 }; 1686