1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_6_0_d.h" 31 #include "uvd/uvd_6_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 #include "smu/smu_7_1_3_d.h" 35 #include "smu/smu_7_1_3_sh_mask.h" 36 #include "bif/bif_5_1_d.h" 37 #include "gmc/gmc_8_1_d.h" 38 #include "vi.h" 39 40 /* Polaris10/11/12 firmware version */ 41 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8)) 42 43 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); 44 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev); 45 46 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); 47 static int uvd_v6_0_start(struct amdgpu_device *adev); 48 static void uvd_v6_0_stop(struct amdgpu_device *adev); 49 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); 50 static int uvd_v6_0_set_clockgating_state(void *handle, 51 enum amd_clockgating_state state); 52 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, 53 bool enable); 54 55 /** 56 * uvd_v6_0_enc_support - get encode support status 57 * 58 * @adev: amdgpu_device pointer 59 * 60 * Returns the current hardware encode support status 61 */ 62 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev) 63 { 64 return ((adev->asic_type >= CHIP_POLARIS10) && 65 (adev->asic_type <= CHIP_VEGAM) && 66 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); 67 } 68 69 /** 70 * uvd_v6_0_ring_get_rptr - get read pointer 71 * 72 * @ring: amdgpu_ring pointer 73 * 74 * Returns the current hardware read pointer 75 */ 76 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 77 { 78 struct amdgpu_device *adev = ring->adev; 79 80 return RREG32(mmUVD_RBC_RB_RPTR); 81 } 82 83 /** 84 * uvd_v6_0_enc_ring_get_rptr - get enc read pointer 85 * 86 * @ring: amdgpu_ring pointer 87 * 88 * Returns the current hardware enc read pointer 89 */ 90 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 91 { 92 struct amdgpu_device *adev = ring->adev; 93 94 if (ring == &adev->uvd.inst->ring_enc[0]) 95 return RREG32(mmUVD_RB_RPTR); 96 else 97 return RREG32(mmUVD_RB_RPTR2); 98 } 99 /** 100 * uvd_v6_0_ring_get_wptr - get write pointer 101 * 102 * @ring: amdgpu_ring pointer 103 * 104 * Returns the current hardware write pointer 105 */ 106 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 107 { 108 struct amdgpu_device *adev = ring->adev; 109 110 return RREG32(mmUVD_RBC_RB_WPTR); 111 } 112 113 /** 114 * uvd_v6_0_enc_ring_get_wptr - get enc write pointer 115 * 116 * @ring: amdgpu_ring pointer 117 * 118 * Returns the current hardware enc write pointer 119 */ 120 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 121 { 122 struct amdgpu_device *adev = ring->adev; 123 124 if (ring == &adev->uvd.inst->ring_enc[0]) 125 return RREG32(mmUVD_RB_WPTR); 126 else 127 return RREG32(mmUVD_RB_WPTR2); 128 } 129 130 /** 131 * uvd_v6_0_ring_set_wptr - set write pointer 132 * 133 * @ring: amdgpu_ring pointer 134 * 135 * Commits the write pointer to the hardware 136 */ 137 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 138 { 139 struct amdgpu_device *adev = ring->adev; 140 141 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 142 } 143 144 /** 145 * uvd_v6_0_enc_ring_set_wptr - set enc write pointer 146 * 147 * @ring: amdgpu_ring pointer 148 * 149 * Commits the enc write pointer to the hardware 150 */ 151 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 152 { 153 struct amdgpu_device *adev = ring->adev; 154 155 if (ring == &adev->uvd.inst->ring_enc[0]) 156 WREG32(mmUVD_RB_WPTR, 157 lower_32_bits(ring->wptr)); 158 else 159 WREG32(mmUVD_RB_WPTR2, 160 lower_32_bits(ring->wptr)); 161 } 162 163 /** 164 * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working 165 * 166 * @ring: the engine to test on 167 * 168 */ 169 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) 170 { 171 struct amdgpu_device *adev = ring->adev; 172 uint32_t rptr = amdgpu_ring_get_rptr(ring); 173 unsigned i; 174 int r; 175 176 r = amdgpu_ring_alloc(ring, 16); 177 if (r) { 178 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n", 179 ring->idx, r); 180 return r; 181 } 182 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 183 amdgpu_ring_commit(ring); 184 185 for (i = 0; i < adev->usec_timeout; i++) { 186 if (amdgpu_ring_get_rptr(ring) != rptr) 187 break; 188 DRM_UDELAY(1); 189 } 190 191 if (i < adev->usec_timeout) { 192 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 193 ring->idx, i); 194 } else { 195 DRM_ERROR("amdgpu: ring %d test failed\n", 196 ring->idx); 197 r = -ETIMEDOUT; 198 } 199 200 return r; 201 } 202 203 /** 204 * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg 205 * 206 * @adev: amdgpu_device pointer 207 * @ring: ring we should submit the msg to 208 * @handle: session handle to use 209 * @fence: optional fence to return 210 * 211 * Open up a stream for HW test 212 */ 213 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 214 struct dma_fence **fence) 215 { 216 const unsigned ib_size_dw = 16; 217 struct amdgpu_job *job; 218 struct amdgpu_ib *ib; 219 struct dma_fence *f = NULL; 220 uint64_t dummy; 221 int i, r; 222 223 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 224 if (r) 225 return r; 226 227 ib = &job->ibs[0]; 228 dummy = ib->gpu_addr + 1024; 229 230 ib->length_dw = 0; 231 ib->ptr[ib->length_dw++] = 0x00000018; 232 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 233 ib->ptr[ib->length_dw++] = handle; 234 ib->ptr[ib->length_dw++] = 0x00010000; 235 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 236 ib->ptr[ib->length_dw++] = dummy; 237 238 ib->ptr[ib->length_dw++] = 0x00000014; 239 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 240 ib->ptr[ib->length_dw++] = 0x0000001c; 241 ib->ptr[ib->length_dw++] = 0x00000001; 242 ib->ptr[ib->length_dw++] = 0x00000000; 243 244 ib->ptr[ib->length_dw++] = 0x00000008; 245 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 246 247 for (i = ib->length_dw; i < ib_size_dw; ++i) 248 ib->ptr[i] = 0x0; 249 250 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 251 job->fence = dma_fence_get(f); 252 if (r) 253 goto err; 254 255 amdgpu_job_free(job); 256 if (fence) 257 *fence = dma_fence_get(f); 258 dma_fence_put(f); 259 return 0; 260 261 err: 262 amdgpu_job_free(job); 263 return r; 264 } 265 266 /** 267 * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 268 * 269 * @adev: amdgpu_device pointer 270 * @ring: ring we should submit the msg to 271 * @handle: session handle to use 272 * @fence: optional fence to return 273 * 274 * Close up a stream for HW test or if userspace failed to do so 275 */ 276 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, 277 uint32_t handle, 278 bool direct, struct dma_fence **fence) 279 { 280 const unsigned ib_size_dw = 16; 281 struct amdgpu_job *job; 282 struct amdgpu_ib *ib; 283 struct dma_fence *f = NULL; 284 uint64_t dummy; 285 int i, r; 286 287 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 288 if (r) 289 return r; 290 291 ib = &job->ibs[0]; 292 dummy = ib->gpu_addr + 1024; 293 294 ib->length_dw = 0; 295 ib->ptr[ib->length_dw++] = 0x00000018; 296 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 297 ib->ptr[ib->length_dw++] = handle; 298 ib->ptr[ib->length_dw++] = 0x00010000; 299 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 300 ib->ptr[ib->length_dw++] = dummy; 301 302 ib->ptr[ib->length_dw++] = 0x00000014; 303 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 304 ib->ptr[ib->length_dw++] = 0x0000001c; 305 ib->ptr[ib->length_dw++] = 0x00000001; 306 ib->ptr[ib->length_dw++] = 0x00000000; 307 308 ib->ptr[ib->length_dw++] = 0x00000008; 309 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 310 311 for (i = ib->length_dw; i < ib_size_dw; ++i) 312 ib->ptr[i] = 0x0; 313 314 if (direct) { 315 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 316 job->fence = dma_fence_get(f); 317 if (r) 318 goto err; 319 320 amdgpu_job_free(job); 321 } else { 322 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity, 323 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 324 if (r) 325 goto err; 326 } 327 328 if (fence) 329 *fence = dma_fence_get(f); 330 dma_fence_put(f); 331 return 0; 332 333 err: 334 amdgpu_job_free(job); 335 return r; 336 } 337 338 /** 339 * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working 340 * 341 * @ring: the engine to test on 342 * 343 */ 344 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 345 { 346 struct dma_fence *fence = NULL; 347 long r; 348 349 r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL); 350 if (r) { 351 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); 352 goto error; 353 } 354 355 r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence); 356 if (r) { 357 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); 358 goto error; 359 } 360 361 r = dma_fence_wait_timeout(fence, false, timeout); 362 if (r == 0) { 363 DRM_ERROR("amdgpu: IB test timed out.\n"); 364 r = -ETIMEDOUT; 365 } else if (r < 0) { 366 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 367 } else { 368 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 369 r = 0; 370 } 371 error: 372 dma_fence_put(fence); 373 return r; 374 } 375 static int uvd_v6_0_early_init(void *handle) 376 { 377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 378 adev->uvd.num_uvd_inst = 1; 379 380 if (!(adev->flags & AMD_IS_APU) && 381 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) 382 return -ENOENT; 383 384 uvd_v6_0_set_ring_funcs(adev); 385 386 if (uvd_v6_0_enc_support(adev)) { 387 adev->uvd.num_enc_rings = 2; 388 uvd_v6_0_set_enc_ring_funcs(adev); 389 } 390 391 uvd_v6_0_set_irq_funcs(adev); 392 393 return 0; 394 } 395 396 static int uvd_v6_0_sw_init(void *handle) 397 { 398 struct amdgpu_ring *ring; 399 int i, r; 400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 401 402 /* UVD TRAP */ 403 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 404 if (r) 405 return r; 406 407 /* UVD ENC TRAP */ 408 if (uvd_v6_0_enc_support(adev)) { 409 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 410 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.inst->irq); 411 if (r) 412 return r; 413 } 414 } 415 416 r = amdgpu_uvd_sw_init(adev); 417 if (r) 418 return r; 419 420 if (!uvd_v6_0_enc_support(adev)) { 421 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 422 adev->uvd.inst->ring_enc[i].funcs = NULL; 423 424 adev->uvd.inst->irq.num_types = 1; 425 adev->uvd.num_enc_rings = 0; 426 427 DRM_INFO("UVD ENC is disabled\n"); 428 } else { 429 struct drm_sched_rq *rq; 430 ring = &adev->uvd.inst->ring_enc[0]; 431 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 432 r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst->entity_enc, 433 rq, NULL); 434 if (r) { 435 DRM_ERROR("Failed setting up UVD ENC run queue.\n"); 436 return r; 437 } 438 } 439 440 r = amdgpu_uvd_resume(adev); 441 if (r) 442 return r; 443 444 ring = &adev->uvd.inst->ring; 445 sprintf(ring->name, "uvd"); 446 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 447 if (r) 448 return r; 449 450 if (uvd_v6_0_enc_support(adev)) { 451 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 452 ring = &adev->uvd.inst->ring_enc[i]; 453 sprintf(ring->name, "uvd_enc%d", i); 454 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 455 if (r) 456 return r; 457 } 458 } 459 460 return r; 461 } 462 463 static int uvd_v6_0_sw_fini(void *handle) 464 { 465 int i, r; 466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 467 468 r = amdgpu_uvd_suspend(adev); 469 if (r) 470 return r; 471 472 if (uvd_v6_0_enc_support(adev)) { 473 drm_sched_entity_fini(&adev->uvd.inst->ring_enc[0].sched, &adev->uvd.inst->entity_enc); 474 475 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 476 amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]); 477 } 478 479 return amdgpu_uvd_sw_fini(adev); 480 } 481 482 /** 483 * uvd_v6_0_hw_init - start and test UVD block 484 * 485 * @adev: amdgpu_device pointer 486 * 487 * Initialize the hardware, boot up the VCPU and do some testing 488 */ 489 static int uvd_v6_0_hw_init(void *handle) 490 { 491 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 492 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 493 uint32_t tmp; 494 int i, r; 495 496 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 497 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 498 uvd_v6_0_enable_mgcg(adev, true); 499 500 ring->ready = true; 501 r = amdgpu_ring_test_ring(ring); 502 if (r) { 503 ring->ready = false; 504 goto done; 505 } 506 507 r = amdgpu_ring_alloc(ring, 10); 508 if (r) { 509 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 510 goto done; 511 } 512 513 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 514 amdgpu_ring_write(ring, tmp); 515 amdgpu_ring_write(ring, 0xFFFFF); 516 517 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 518 amdgpu_ring_write(ring, tmp); 519 amdgpu_ring_write(ring, 0xFFFFF); 520 521 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 522 amdgpu_ring_write(ring, tmp); 523 amdgpu_ring_write(ring, 0xFFFFF); 524 525 /* Clear timeout status bits */ 526 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 527 amdgpu_ring_write(ring, 0x8); 528 529 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 530 amdgpu_ring_write(ring, 3); 531 532 amdgpu_ring_commit(ring); 533 534 if (uvd_v6_0_enc_support(adev)) { 535 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 536 ring = &adev->uvd.inst->ring_enc[i]; 537 ring->ready = true; 538 r = amdgpu_ring_test_ring(ring); 539 if (r) { 540 ring->ready = false; 541 goto done; 542 } 543 } 544 } 545 546 done: 547 if (!r) { 548 if (uvd_v6_0_enc_support(adev)) 549 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 550 else 551 DRM_INFO("UVD initialized successfully.\n"); 552 } 553 554 return r; 555 } 556 557 /** 558 * uvd_v6_0_hw_fini - stop the hardware block 559 * 560 * @adev: amdgpu_device pointer 561 * 562 * Stop the UVD block, mark ring as not ready any more 563 */ 564 static int uvd_v6_0_hw_fini(void *handle) 565 { 566 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 567 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 568 569 if (RREG32(mmUVD_STATUS) != 0) 570 uvd_v6_0_stop(adev); 571 572 ring->ready = false; 573 574 return 0; 575 } 576 577 static int uvd_v6_0_suspend(void *handle) 578 { 579 int r; 580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 581 582 r = uvd_v6_0_hw_fini(adev); 583 if (r) 584 return r; 585 586 return amdgpu_uvd_suspend(adev); 587 } 588 589 static int uvd_v6_0_resume(void *handle) 590 { 591 int r; 592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 593 594 r = amdgpu_uvd_resume(adev); 595 if (r) 596 return r; 597 598 return uvd_v6_0_hw_init(adev); 599 } 600 601 /** 602 * uvd_v6_0_mc_resume - memory controller programming 603 * 604 * @adev: amdgpu_device pointer 605 * 606 * Let the UVD memory controller know it's offsets 607 */ 608 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 609 { 610 uint64_t offset; 611 uint32_t size; 612 613 /* programm memory controller bits 0-27 */ 614 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 615 lower_32_bits(adev->uvd.inst->gpu_addr)); 616 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 617 upper_32_bits(adev->uvd.inst->gpu_addr)); 618 619 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 620 size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 621 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 622 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 623 624 offset += size; 625 size = AMDGPU_UVD_HEAP_SIZE; 626 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 627 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 628 629 offset += size; 630 size = AMDGPU_UVD_STACK_SIZE + 631 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 632 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 633 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 634 635 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 636 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 637 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 638 639 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 640 } 641 642 #if 0 643 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 644 bool enable) 645 { 646 u32 data, data1; 647 648 data = RREG32(mmUVD_CGC_GATE); 649 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 650 if (enable) { 651 data |= UVD_CGC_GATE__SYS_MASK | 652 UVD_CGC_GATE__UDEC_MASK | 653 UVD_CGC_GATE__MPEG2_MASK | 654 UVD_CGC_GATE__RBC_MASK | 655 UVD_CGC_GATE__LMI_MC_MASK | 656 UVD_CGC_GATE__IDCT_MASK | 657 UVD_CGC_GATE__MPRD_MASK | 658 UVD_CGC_GATE__MPC_MASK | 659 UVD_CGC_GATE__LBSI_MASK | 660 UVD_CGC_GATE__LRBBM_MASK | 661 UVD_CGC_GATE__UDEC_RE_MASK | 662 UVD_CGC_GATE__UDEC_CM_MASK | 663 UVD_CGC_GATE__UDEC_IT_MASK | 664 UVD_CGC_GATE__UDEC_DB_MASK | 665 UVD_CGC_GATE__UDEC_MP_MASK | 666 UVD_CGC_GATE__WCB_MASK | 667 UVD_CGC_GATE__VCPU_MASK | 668 UVD_CGC_GATE__SCPU_MASK; 669 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 670 UVD_SUVD_CGC_GATE__SIT_MASK | 671 UVD_SUVD_CGC_GATE__SMP_MASK | 672 UVD_SUVD_CGC_GATE__SCM_MASK | 673 UVD_SUVD_CGC_GATE__SDB_MASK | 674 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 675 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 676 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 677 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 678 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 679 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 680 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 681 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 682 } else { 683 data &= ~(UVD_CGC_GATE__SYS_MASK | 684 UVD_CGC_GATE__UDEC_MASK | 685 UVD_CGC_GATE__MPEG2_MASK | 686 UVD_CGC_GATE__RBC_MASK | 687 UVD_CGC_GATE__LMI_MC_MASK | 688 UVD_CGC_GATE__LMI_UMC_MASK | 689 UVD_CGC_GATE__IDCT_MASK | 690 UVD_CGC_GATE__MPRD_MASK | 691 UVD_CGC_GATE__MPC_MASK | 692 UVD_CGC_GATE__LBSI_MASK | 693 UVD_CGC_GATE__LRBBM_MASK | 694 UVD_CGC_GATE__UDEC_RE_MASK | 695 UVD_CGC_GATE__UDEC_CM_MASK | 696 UVD_CGC_GATE__UDEC_IT_MASK | 697 UVD_CGC_GATE__UDEC_DB_MASK | 698 UVD_CGC_GATE__UDEC_MP_MASK | 699 UVD_CGC_GATE__WCB_MASK | 700 UVD_CGC_GATE__VCPU_MASK | 701 UVD_CGC_GATE__SCPU_MASK); 702 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 703 UVD_SUVD_CGC_GATE__SIT_MASK | 704 UVD_SUVD_CGC_GATE__SMP_MASK | 705 UVD_SUVD_CGC_GATE__SCM_MASK | 706 UVD_SUVD_CGC_GATE__SDB_MASK | 707 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 708 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 709 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 710 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 711 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 712 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 713 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 714 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); 715 } 716 WREG32(mmUVD_CGC_GATE, data); 717 WREG32(mmUVD_SUVD_CGC_GATE, data1); 718 } 719 #endif 720 721 /** 722 * uvd_v6_0_start - start UVD block 723 * 724 * @adev: amdgpu_device pointer 725 * 726 * Setup and start the UVD block 727 */ 728 static int uvd_v6_0_start(struct amdgpu_device *adev) 729 { 730 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 731 uint32_t rb_bufsz, tmp; 732 uint32_t lmi_swap_cntl; 733 uint32_t mp_swap_cntl; 734 int i, j, r; 735 736 /* disable DPG */ 737 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 738 739 /* disable byte swapping */ 740 lmi_swap_cntl = 0; 741 mp_swap_cntl = 0; 742 743 uvd_v6_0_mc_resume(adev); 744 745 /* disable interupt */ 746 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); 747 748 /* stall UMC and register bus before resetting VCPU */ 749 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); 750 mdelay(1); 751 752 /* put LMI, VCPU, RBC etc... into reset */ 753 WREG32(mmUVD_SOFT_RESET, 754 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 755 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 756 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 757 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 758 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 759 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 760 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 761 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 762 mdelay(5); 763 764 /* take UVD block out of reset */ 765 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); 766 mdelay(5); 767 768 /* initialize UVD memory controller */ 769 WREG32(mmUVD_LMI_CTRL, 770 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 771 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 772 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 773 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 774 UVD_LMI_CTRL__REQ_MODE_MASK | 775 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK); 776 777 #ifdef __BIG_ENDIAN 778 /* swap (8 in 32) RB and IB */ 779 lmi_swap_cntl = 0xa; 780 mp_swap_cntl = 0; 781 #endif 782 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 783 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 784 785 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 786 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 787 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 788 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 789 WREG32(mmUVD_MPC_SET_ALU, 0); 790 WREG32(mmUVD_MPC_SET_MUX, 0x88); 791 792 /* take all subblocks out of reset, except VCPU */ 793 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 794 mdelay(5); 795 796 /* enable VCPU clock */ 797 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 798 799 /* enable UMC */ 800 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); 801 802 /* boot up the VCPU */ 803 WREG32(mmUVD_SOFT_RESET, 0); 804 mdelay(10); 805 806 for (i = 0; i < 10; ++i) { 807 uint32_t status; 808 809 for (j = 0; j < 100; ++j) { 810 status = RREG32(mmUVD_STATUS); 811 if (status & 2) 812 break; 813 mdelay(10); 814 } 815 r = 0; 816 if (status & 2) 817 break; 818 819 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 820 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); 821 mdelay(10); 822 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); 823 mdelay(10); 824 r = -1; 825 } 826 827 if (r) { 828 DRM_ERROR("UVD not responding, giving up!!!\n"); 829 return r; 830 } 831 /* enable master interrupt */ 832 WREG32_P(mmUVD_MASTINT_EN, 833 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 834 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 835 836 /* clear the bit 4 of UVD_STATUS */ 837 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 838 839 /* force RBC into idle state */ 840 rb_bufsz = order_base_2(ring->ring_size); 841 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 842 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 843 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 844 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 845 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 846 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 847 WREG32(mmUVD_RBC_RB_CNTL, tmp); 848 849 /* set the write pointer delay */ 850 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 851 852 /* set the wb address */ 853 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 854 855 /* programm the RB_BASE for ring buffer */ 856 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 857 lower_32_bits(ring->gpu_addr)); 858 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 859 upper_32_bits(ring->gpu_addr)); 860 861 /* Initialize the ring buffer's read and write pointers */ 862 WREG32(mmUVD_RBC_RB_RPTR, 0); 863 864 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 865 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 866 867 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); 868 869 if (uvd_v6_0_enc_support(adev)) { 870 ring = &adev->uvd.inst->ring_enc[0]; 871 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 872 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 873 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); 874 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 875 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4); 876 877 ring = &adev->uvd.inst->ring_enc[1]; 878 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 879 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 880 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); 881 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 882 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4); 883 } 884 885 return 0; 886 } 887 888 /** 889 * uvd_v6_0_stop - stop UVD block 890 * 891 * @adev: amdgpu_device pointer 892 * 893 * stop the UVD block 894 */ 895 static void uvd_v6_0_stop(struct amdgpu_device *adev) 896 { 897 /* force RBC into idle state */ 898 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 899 900 /* Stall UMC and register bus before resetting VCPU */ 901 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 902 mdelay(1); 903 904 /* put VCPU into reset */ 905 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 906 mdelay(5); 907 908 /* disable VCPU clock */ 909 WREG32(mmUVD_VCPU_CNTL, 0x0); 910 911 /* Unstall UMC and register bus */ 912 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 913 914 WREG32(mmUVD_STATUS, 0); 915 } 916 917 /** 918 * uvd_v6_0_ring_emit_fence - emit an fence & trap command 919 * 920 * @ring: amdgpu_ring pointer 921 * @fence: fence to emit 922 * 923 * Write a fence and a trap command to the ring. 924 */ 925 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 926 unsigned flags) 927 { 928 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 929 930 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 931 amdgpu_ring_write(ring, seq); 932 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 933 amdgpu_ring_write(ring, addr & 0xffffffff); 934 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 935 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 936 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 937 amdgpu_ring_write(ring, 0); 938 939 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 940 amdgpu_ring_write(ring, 0); 941 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 942 amdgpu_ring_write(ring, 0); 943 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 944 amdgpu_ring_write(ring, 2); 945 } 946 947 /** 948 * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command 949 * 950 * @ring: amdgpu_ring pointer 951 * @fence: fence to emit 952 * 953 * Write enc a fence and a trap command to the ring. 954 */ 955 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 956 u64 seq, unsigned flags) 957 { 958 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 959 960 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 961 amdgpu_ring_write(ring, addr); 962 amdgpu_ring_write(ring, upper_32_bits(addr)); 963 amdgpu_ring_write(ring, seq); 964 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 965 } 966 967 /** 968 * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing 969 * 970 * @ring: amdgpu_ring pointer 971 */ 972 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 973 { 974 /* The firmware doesn't seem to like touching registers at this point. */ 975 } 976 977 /** 978 * uvd_v6_0_ring_test_ring - register write test 979 * 980 * @ring: amdgpu_ring pointer 981 * 982 * Test if we can successfully write to the context register 983 */ 984 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) 985 { 986 struct amdgpu_device *adev = ring->adev; 987 uint32_t tmp = 0; 988 unsigned i; 989 int r; 990 991 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 992 r = amdgpu_ring_alloc(ring, 3); 993 if (r) { 994 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 995 ring->idx, r); 996 return r; 997 } 998 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 999 amdgpu_ring_write(ring, 0xDEADBEEF); 1000 amdgpu_ring_commit(ring); 1001 for (i = 0; i < adev->usec_timeout; i++) { 1002 tmp = RREG32(mmUVD_CONTEXT_ID); 1003 if (tmp == 0xDEADBEEF) 1004 break; 1005 DRM_UDELAY(1); 1006 } 1007 1008 if (i < adev->usec_timeout) { 1009 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 1010 ring->idx, i); 1011 } else { 1012 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 1013 ring->idx, tmp); 1014 r = -EINVAL; 1015 } 1016 return r; 1017 } 1018 1019 /** 1020 * uvd_v6_0_ring_emit_ib - execute indirect buffer 1021 * 1022 * @ring: amdgpu_ring pointer 1023 * @ib: indirect buffer to execute 1024 * 1025 * Write ring commands to execute the indirect buffer 1026 */ 1027 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1028 struct amdgpu_ib *ib, 1029 unsigned vmid, bool ctx_switch) 1030 { 1031 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); 1032 amdgpu_ring_write(ring, vmid); 1033 1034 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 1035 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1036 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 1037 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1038 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 1039 amdgpu_ring_write(ring, ib->length_dw); 1040 } 1041 1042 /** 1043 * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer 1044 * 1045 * @ring: amdgpu_ring pointer 1046 * @ib: indirect buffer to execute 1047 * 1048 * Write enc ring commands to execute the indirect buffer 1049 */ 1050 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1051 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) 1052 { 1053 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1054 amdgpu_ring_write(ring, vmid); 1055 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1056 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1057 amdgpu_ring_write(ring, ib->length_dw); 1058 } 1059 1060 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1061 uint32_t reg, uint32_t val) 1062 { 1063 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1064 amdgpu_ring_write(ring, reg << 2); 1065 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1066 amdgpu_ring_write(ring, val); 1067 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1068 amdgpu_ring_write(ring, 0x8); 1069 } 1070 1071 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1072 unsigned vmid, uint64_t pd_addr) 1073 { 1074 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1075 1076 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1077 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1078 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1079 amdgpu_ring_write(ring, 0); 1080 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1081 amdgpu_ring_write(ring, 1 << vmid); /* mask */ 1082 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1083 amdgpu_ring_write(ring, 0xC); 1084 } 1085 1086 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1087 { 1088 uint32_t seq = ring->fence_drv.sync_seq; 1089 uint64_t addr = ring->fence_drv.gpu_addr; 1090 1091 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1092 amdgpu_ring_write(ring, lower_32_bits(addr)); 1093 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1094 amdgpu_ring_write(ring, upper_32_bits(addr)); 1095 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1096 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1097 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); 1098 amdgpu_ring_write(ring, seq); 1099 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1100 amdgpu_ring_write(ring, 0xE); 1101 } 1102 1103 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1104 { 1105 int i; 1106 1107 WARN_ON(ring->wptr % 2 || count % 2); 1108 1109 for (i = 0; i < count / 2; i++) { 1110 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 1111 amdgpu_ring_write(ring, 0); 1112 } 1113 } 1114 1115 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1116 { 1117 uint32_t seq = ring->fence_drv.sync_seq; 1118 uint64_t addr = ring->fence_drv.gpu_addr; 1119 1120 amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE); 1121 amdgpu_ring_write(ring, lower_32_bits(addr)); 1122 amdgpu_ring_write(ring, upper_32_bits(addr)); 1123 amdgpu_ring_write(ring, seq); 1124 } 1125 1126 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1127 { 1128 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1129 } 1130 1131 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1132 unsigned int vmid, uint64_t pd_addr) 1133 { 1134 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB); 1135 amdgpu_ring_write(ring, vmid); 1136 amdgpu_ring_write(ring, pd_addr >> 12); 1137 1138 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB); 1139 amdgpu_ring_write(ring, vmid); 1140 } 1141 1142 static bool uvd_v6_0_is_idle(void *handle) 1143 { 1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1145 1146 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1147 } 1148 1149 static int uvd_v6_0_wait_for_idle(void *handle) 1150 { 1151 unsigned i; 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 1154 for (i = 0; i < adev->usec_timeout; i++) { 1155 if (uvd_v6_0_is_idle(handle)) 1156 return 0; 1157 } 1158 return -ETIMEDOUT; 1159 } 1160 1161 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1162 static bool uvd_v6_0_check_soft_reset(void *handle) 1163 { 1164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1165 u32 srbm_soft_reset = 0; 1166 u32 tmp = RREG32(mmSRBM_STATUS); 1167 1168 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1169 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1170 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) 1171 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1172 1173 if (srbm_soft_reset) { 1174 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset; 1175 return true; 1176 } else { 1177 adev->uvd.inst->srbm_soft_reset = 0; 1178 return false; 1179 } 1180 } 1181 1182 static int uvd_v6_0_pre_soft_reset(void *handle) 1183 { 1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1185 1186 if (!adev->uvd.inst->srbm_soft_reset) 1187 return 0; 1188 1189 uvd_v6_0_stop(adev); 1190 return 0; 1191 } 1192 1193 static int uvd_v6_0_soft_reset(void *handle) 1194 { 1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1196 u32 srbm_soft_reset; 1197 1198 if (!adev->uvd.inst->srbm_soft_reset) 1199 return 0; 1200 srbm_soft_reset = adev->uvd.inst->srbm_soft_reset; 1201 1202 if (srbm_soft_reset) { 1203 u32 tmp; 1204 1205 tmp = RREG32(mmSRBM_SOFT_RESET); 1206 tmp |= srbm_soft_reset; 1207 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1208 WREG32(mmSRBM_SOFT_RESET, tmp); 1209 tmp = RREG32(mmSRBM_SOFT_RESET); 1210 1211 udelay(50); 1212 1213 tmp &= ~srbm_soft_reset; 1214 WREG32(mmSRBM_SOFT_RESET, tmp); 1215 tmp = RREG32(mmSRBM_SOFT_RESET); 1216 1217 /* Wait a little for things to settle down */ 1218 udelay(50); 1219 } 1220 1221 return 0; 1222 } 1223 1224 static int uvd_v6_0_post_soft_reset(void *handle) 1225 { 1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1227 1228 if (!adev->uvd.inst->srbm_soft_reset) 1229 return 0; 1230 1231 mdelay(5); 1232 1233 return uvd_v6_0_start(adev); 1234 } 1235 1236 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 1237 struct amdgpu_irq_src *source, 1238 unsigned type, 1239 enum amdgpu_interrupt_state state) 1240 { 1241 // TODO 1242 return 0; 1243 } 1244 1245 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, 1246 struct amdgpu_irq_src *source, 1247 struct amdgpu_iv_entry *entry) 1248 { 1249 bool int_handled = true; 1250 DRM_DEBUG("IH: UVD TRAP\n"); 1251 1252 switch (entry->src_id) { 1253 case 124: 1254 amdgpu_fence_process(&adev->uvd.inst->ring); 1255 break; 1256 case 119: 1257 if (likely(uvd_v6_0_enc_support(adev))) 1258 amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]); 1259 else 1260 int_handled = false; 1261 break; 1262 case 120: 1263 if (likely(uvd_v6_0_enc_support(adev))) 1264 amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]); 1265 else 1266 int_handled = false; 1267 break; 1268 } 1269 1270 if (false == int_handled) 1271 DRM_ERROR("Unhandled interrupt: %d %d\n", 1272 entry->src_id, entry->src_data[0]); 1273 1274 return 0; 1275 } 1276 1277 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 1278 { 1279 uint32_t data1, data3; 1280 1281 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 1282 data3 = RREG32(mmUVD_CGC_GATE); 1283 1284 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 1285 UVD_SUVD_CGC_GATE__SIT_MASK | 1286 UVD_SUVD_CGC_GATE__SMP_MASK | 1287 UVD_SUVD_CGC_GATE__SCM_MASK | 1288 UVD_SUVD_CGC_GATE__SDB_MASK | 1289 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 1290 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 1291 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 1292 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 1293 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 1294 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 1295 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 1296 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 1297 1298 if (enable) { 1299 data3 |= (UVD_CGC_GATE__SYS_MASK | 1300 UVD_CGC_GATE__UDEC_MASK | 1301 UVD_CGC_GATE__MPEG2_MASK | 1302 UVD_CGC_GATE__RBC_MASK | 1303 UVD_CGC_GATE__LMI_MC_MASK | 1304 UVD_CGC_GATE__LMI_UMC_MASK | 1305 UVD_CGC_GATE__IDCT_MASK | 1306 UVD_CGC_GATE__MPRD_MASK | 1307 UVD_CGC_GATE__MPC_MASK | 1308 UVD_CGC_GATE__LBSI_MASK | 1309 UVD_CGC_GATE__LRBBM_MASK | 1310 UVD_CGC_GATE__UDEC_RE_MASK | 1311 UVD_CGC_GATE__UDEC_CM_MASK | 1312 UVD_CGC_GATE__UDEC_IT_MASK | 1313 UVD_CGC_GATE__UDEC_DB_MASK | 1314 UVD_CGC_GATE__UDEC_MP_MASK | 1315 UVD_CGC_GATE__WCB_MASK | 1316 UVD_CGC_GATE__JPEG_MASK | 1317 UVD_CGC_GATE__SCPU_MASK | 1318 UVD_CGC_GATE__JPEG2_MASK); 1319 /* only in pg enabled, we can gate clock to vcpu*/ 1320 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1321 data3 |= UVD_CGC_GATE__VCPU_MASK; 1322 1323 data3 &= ~UVD_CGC_GATE__REGS_MASK; 1324 } else { 1325 data3 = 0; 1326 } 1327 1328 WREG32(mmUVD_SUVD_CGC_GATE, data1); 1329 WREG32(mmUVD_CGC_GATE, data3); 1330 } 1331 1332 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) 1333 { 1334 uint32_t data, data2; 1335 1336 data = RREG32(mmUVD_CGC_CTRL); 1337 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 1338 1339 1340 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1341 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1342 1343 1344 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1345 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1346 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1347 1348 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1349 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1350 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1351 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1352 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1353 UVD_CGC_CTRL__SYS_MODE_MASK | 1354 UVD_CGC_CTRL__UDEC_MODE_MASK | 1355 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1356 UVD_CGC_CTRL__REGS_MODE_MASK | 1357 UVD_CGC_CTRL__RBC_MODE_MASK | 1358 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1359 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1360 UVD_CGC_CTRL__IDCT_MODE_MASK | 1361 UVD_CGC_CTRL__MPRD_MODE_MASK | 1362 UVD_CGC_CTRL__MPC_MODE_MASK | 1363 UVD_CGC_CTRL__LBSI_MODE_MASK | 1364 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1365 UVD_CGC_CTRL__WCB_MODE_MASK | 1366 UVD_CGC_CTRL__VCPU_MODE_MASK | 1367 UVD_CGC_CTRL__JPEG_MODE_MASK | 1368 UVD_CGC_CTRL__SCPU_MODE_MASK | 1369 UVD_CGC_CTRL__JPEG2_MODE_MASK); 1370 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1371 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1372 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1373 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1374 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1375 1376 WREG32(mmUVD_CGC_CTRL, data); 1377 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 1378 } 1379 1380 #if 0 1381 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 1382 { 1383 uint32_t data, data1, cgc_flags, suvd_flags; 1384 1385 data = RREG32(mmUVD_CGC_GATE); 1386 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 1387 1388 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1389 UVD_CGC_GATE__UDEC_MASK | 1390 UVD_CGC_GATE__MPEG2_MASK | 1391 UVD_CGC_GATE__RBC_MASK | 1392 UVD_CGC_GATE__LMI_MC_MASK | 1393 UVD_CGC_GATE__IDCT_MASK | 1394 UVD_CGC_GATE__MPRD_MASK | 1395 UVD_CGC_GATE__MPC_MASK | 1396 UVD_CGC_GATE__LBSI_MASK | 1397 UVD_CGC_GATE__LRBBM_MASK | 1398 UVD_CGC_GATE__UDEC_RE_MASK | 1399 UVD_CGC_GATE__UDEC_CM_MASK | 1400 UVD_CGC_GATE__UDEC_IT_MASK | 1401 UVD_CGC_GATE__UDEC_DB_MASK | 1402 UVD_CGC_GATE__UDEC_MP_MASK | 1403 UVD_CGC_GATE__WCB_MASK | 1404 UVD_CGC_GATE__VCPU_MASK | 1405 UVD_CGC_GATE__SCPU_MASK | 1406 UVD_CGC_GATE__JPEG_MASK | 1407 UVD_CGC_GATE__JPEG2_MASK; 1408 1409 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1410 UVD_SUVD_CGC_GATE__SIT_MASK | 1411 UVD_SUVD_CGC_GATE__SMP_MASK | 1412 UVD_SUVD_CGC_GATE__SCM_MASK | 1413 UVD_SUVD_CGC_GATE__SDB_MASK; 1414 1415 data |= cgc_flags; 1416 data1 |= suvd_flags; 1417 1418 WREG32(mmUVD_CGC_GATE, data); 1419 WREG32(mmUVD_SUVD_CGC_GATE, data1); 1420 } 1421 #endif 1422 1423 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, 1424 bool enable) 1425 { 1426 u32 orig, data; 1427 1428 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 1429 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 1430 data |= 0xfff; 1431 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 1432 1433 orig = data = RREG32(mmUVD_CGC_CTRL); 1434 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1435 if (orig != data) 1436 WREG32(mmUVD_CGC_CTRL, data); 1437 } else { 1438 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 1439 data &= ~0xfff; 1440 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 1441 1442 orig = data = RREG32(mmUVD_CGC_CTRL); 1443 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1444 if (orig != data) 1445 WREG32(mmUVD_CGC_CTRL, data); 1446 } 1447 } 1448 1449 static int uvd_v6_0_set_clockgating_state(void *handle, 1450 enum amd_clockgating_state state) 1451 { 1452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1453 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1454 1455 if (enable) { 1456 /* wait for STATUS to clear */ 1457 if (uvd_v6_0_wait_for_idle(handle)) 1458 return -EBUSY; 1459 uvd_v6_0_enable_clock_gating(adev, true); 1460 /* enable HW gates because UVD is idle */ 1461 /* uvd_v6_0_set_hw_clock_gating(adev); */ 1462 } else { 1463 /* disable HW gating and enable Sw gating */ 1464 uvd_v6_0_enable_clock_gating(adev, false); 1465 } 1466 uvd_v6_0_set_sw_clock_gating(adev); 1467 return 0; 1468 } 1469 1470 static int uvd_v6_0_set_powergating_state(void *handle, 1471 enum amd_powergating_state state) 1472 { 1473 /* This doesn't actually powergate the UVD block. 1474 * That's done in the dpm code via the SMC. This 1475 * just re-inits the block as necessary. The actual 1476 * gating still happens in the dpm code. We should 1477 * revisit this when there is a cleaner line between 1478 * the smc and the hw blocks 1479 */ 1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1481 int ret = 0; 1482 1483 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1484 1485 if (state == AMD_PG_STATE_GATE) { 1486 uvd_v6_0_stop(adev); 1487 } else { 1488 ret = uvd_v6_0_start(adev); 1489 if (ret) 1490 goto out; 1491 } 1492 1493 out: 1494 return ret; 1495 } 1496 1497 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags) 1498 { 1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1500 int data; 1501 1502 mutex_lock(&adev->pm.mutex); 1503 1504 if (adev->flags & AMD_IS_APU) 1505 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); 1506 else 1507 data = RREG32_SMC(ixCURRENT_PG_STATUS); 1508 1509 if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 1510 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 1511 goto out; 1512 } 1513 1514 /* AMD_CG_SUPPORT_UVD_MGCG */ 1515 data = RREG32(mmUVD_CGC_CTRL); 1516 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 1517 *flags |= AMD_CG_SUPPORT_UVD_MGCG; 1518 1519 out: 1520 mutex_unlock(&adev->pm.mutex); 1521 } 1522 1523 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 1524 .name = "uvd_v6_0", 1525 .early_init = uvd_v6_0_early_init, 1526 .late_init = NULL, 1527 .sw_init = uvd_v6_0_sw_init, 1528 .sw_fini = uvd_v6_0_sw_fini, 1529 .hw_init = uvd_v6_0_hw_init, 1530 .hw_fini = uvd_v6_0_hw_fini, 1531 .suspend = uvd_v6_0_suspend, 1532 .resume = uvd_v6_0_resume, 1533 .is_idle = uvd_v6_0_is_idle, 1534 .wait_for_idle = uvd_v6_0_wait_for_idle, 1535 .check_soft_reset = uvd_v6_0_check_soft_reset, 1536 .pre_soft_reset = uvd_v6_0_pre_soft_reset, 1537 .soft_reset = uvd_v6_0_soft_reset, 1538 .post_soft_reset = uvd_v6_0_post_soft_reset, 1539 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 1540 .set_powergating_state = uvd_v6_0_set_powergating_state, 1541 .get_clockgating_state = uvd_v6_0_get_clockgating_state, 1542 }; 1543 1544 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { 1545 .type = AMDGPU_RING_TYPE_UVD, 1546 .align_mask = 0xf, 1547 .support_64bit_ptrs = false, 1548 .get_rptr = uvd_v6_0_ring_get_rptr, 1549 .get_wptr = uvd_v6_0_ring_get_wptr, 1550 .set_wptr = uvd_v6_0_ring_set_wptr, 1551 .parse_cs = amdgpu_uvd_ring_parse_cs, 1552 .emit_frame_size = 1553 6 + /* hdp invalidate */ 1554 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ 1555 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ 1556 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ 1557 .emit_ib = uvd_v6_0_ring_emit_ib, 1558 .emit_fence = uvd_v6_0_ring_emit_fence, 1559 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1560 .test_ring = uvd_v6_0_ring_test_ring, 1561 .test_ib = amdgpu_uvd_ring_test_ib, 1562 .insert_nop = uvd_v6_0_ring_insert_nop, 1563 .pad_ib = amdgpu_ring_generic_pad_ib, 1564 .begin_use = amdgpu_uvd_ring_begin_use, 1565 .end_use = amdgpu_uvd_ring_end_use, 1566 .emit_wreg = uvd_v6_0_ring_emit_wreg, 1567 }; 1568 1569 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { 1570 .type = AMDGPU_RING_TYPE_UVD, 1571 .align_mask = 0xf, 1572 .nop = PACKET0(mmUVD_NO_OP, 0), 1573 .support_64bit_ptrs = false, 1574 .get_rptr = uvd_v6_0_ring_get_rptr, 1575 .get_wptr = uvd_v6_0_ring_get_wptr, 1576 .set_wptr = uvd_v6_0_ring_set_wptr, 1577 .emit_frame_size = 1578 6 + /* hdp invalidate */ 1579 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ 1580 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */ 1581 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ 1582 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ 1583 .emit_ib = uvd_v6_0_ring_emit_ib, 1584 .emit_fence = uvd_v6_0_ring_emit_fence, 1585 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, 1586 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync, 1587 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1588 .test_ring = uvd_v6_0_ring_test_ring, 1589 .test_ib = amdgpu_uvd_ring_test_ib, 1590 .insert_nop = amdgpu_ring_insert_nop, 1591 .pad_ib = amdgpu_ring_generic_pad_ib, 1592 .begin_use = amdgpu_uvd_ring_begin_use, 1593 .end_use = amdgpu_uvd_ring_end_use, 1594 .emit_wreg = uvd_v6_0_ring_emit_wreg, 1595 }; 1596 1597 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { 1598 .type = AMDGPU_RING_TYPE_UVD_ENC, 1599 .align_mask = 0x3f, 1600 .nop = HEVC_ENC_CMD_NO_OP, 1601 .support_64bit_ptrs = false, 1602 .get_rptr = uvd_v6_0_enc_ring_get_rptr, 1603 .get_wptr = uvd_v6_0_enc_ring_get_wptr, 1604 .set_wptr = uvd_v6_0_enc_ring_set_wptr, 1605 .emit_frame_size = 1606 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ 1607 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */ 1608 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ 1609 1, /* uvd_v6_0_enc_ring_insert_end */ 1610 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */ 1611 .emit_ib = uvd_v6_0_enc_ring_emit_ib, 1612 .emit_fence = uvd_v6_0_enc_ring_emit_fence, 1613 .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush, 1614 .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync, 1615 .test_ring = uvd_v6_0_enc_ring_test_ring, 1616 .test_ib = uvd_v6_0_enc_ring_test_ib, 1617 .insert_nop = amdgpu_ring_insert_nop, 1618 .insert_end = uvd_v6_0_enc_ring_insert_end, 1619 .pad_ib = amdgpu_ring_generic_pad_ib, 1620 .begin_use = amdgpu_uvd_ring_begin_use, 1621 .end_use = amdgpu_uvd_ring_end_use, 1622 }; 1623 1624 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1625 { 1626 if (adev->asic_type >= CHIP_POLARIS10) { 1627 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs; 1628 DRM_INFO("UVD is enabled in VM mode\n"); 1629 } else { 1630 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs; 1631 DRM_INFO("UVD is enabled in physical mode\n"); 1632 } 1633 } 1634 1635 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1636 { 1637 int i; 1638 1639 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 1640 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs; 1641 1642 DRM_INFO("UVD ENC is enabled in VM mode\n"); 1643 } 1644 1645 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { 1646 .set = uvd_v6_0_set_interrupt_state, 1647 .process = uvd_v6_0_process_interrupt, 1648 }; 1649 1650 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1651 { 1652 if (uvd_v6_0_enc_support(adev)) 1653 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; 1654 else 1655 adev->uvd.inst->irq.num_types = 1; 1656 1657 adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs; 1658 } 1659 1660 const struct amdgpu_ip_block_version uvd_v6_0_ip_block = 1661 { 1662 .type = AMD_IP_BLOCK_TYPE_UVD, 1663 .major = 6, 1664 .minor = 0, 1665 .rev = 0, 1666 .funcs = &uvd_v6_0_ip_funcs, 1667 }; 1668 1669 const struct amdgpu_ip_block_version uvd_v6_2_ip_block = 1670 { 1671 .type = AMD_IP_BLOCK_TYPE_UVD, 1672 .major = 6, 1673 .minor = 2, 1674 .rev = 0, 1675 .funcs = &uvd_v6_0_ip_funcs, 1676 }; 1677 1678 const struct amdgpu_ip_block_version uvd_v6_3_ip_block = 1679 { 1680 .type = AMD_IP_BLOCK_TYPE_UVD, 1681 .major = 6, 1682 .minor = 3, 1683 .rev = 0, 1684 .funcs = &uvd_v6_0_ip_funcs, 1685 }; 1686