1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_6_0_d.h" 31 #include "uvd/uvd_6_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 35 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); 36 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); 37 static int uvd_v6_0_start(struct amdgpu_device *adev); 38 static void uvd_v6_0_stop(struct amdgpu_device *adev); 39 40 /** 41 * uvd_v6_0_ring_get_rptr - get read pointer 42 * 43 * @ring: amdgpu_ring pointer 44 * 45 * Returns the current hardware read pointer 46 */ 47 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 48 { 49 struct amdgpu_device *adev = ring->adev; 50 51 return RREG32(mmUVD_RBC_RB_RPTR); 52 } 53 54 /** 55 * uvd_v6_0_ring_get_wptr - get write pointer 56 * 57 * @ring: amdgpu_ring pointer 58 * 59 * Returns the current hardware write pointer 60 */ 61 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 62 { 63 struct amdgpu_device *adev = ring->adev; 64 65 return RREG32(mmUVD_RBC_RB_WPTR); 66 } 67 68 /** 69 * uvd_v6_0_ring_set_wptr - set write pointer 70 * 71 * @ring: amdgpu_ring pointer 72 * 73 * Commits the write pointer to the hardware 74 */ 75 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 76 { 77 struct amdgpu_device *adev = ring->adev; 78 79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 80 } 81 82 static int uvd_v6_0_early_init(void *handle) 83 { 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 86 uvd_v6_0_set_ring_funcs(adev); 87 uvd_v6_0_set_irq_funcs(adev); 88 89 return 0; 90 } 91 92 static int uvd_v6_0_sw_init(void *handle) 93 { 94 struct amdgpu_ring *ring; 95 int r; 96 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 97 98 /* UVD TRAP */ 99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 100 if (r) 101 return r; 102 103 r = amdgpu_uvd_sw_init(adev); 104 if (r) 105 return r; 106 107 r = amdgpu_uvd_resume(adev); 108 if (r) 109 return r; 110 111 ring = &adev->uvd.ring; 112 sprintf(ring->name, "uvd"); 113 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 114 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 115 116 return r; 117 } 118 119 static int uvd_v6_0_sw_fini(void *handle) 120 { 121 int r; 122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 123 124 r = amdgpu_uvd_suspend(adev); 125 if (r) 126 return r; 127 128 r = amdgpu_uvd_sw_fini(adev); 129 if (r) 130 return r; 131 132 return r; 133 } 134 135 /** 136 * uvd_v6_0_hw_init - start and test UVD block 137 * 138 * @adev: amdgpu_device pointer 139 * 140 * Initialize the hardware, boot up the VCPU and do some testing 141 */ 142 static int uvd_v6_0_hw_init(void *handle) 143 { 144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 145 struct amdgpu_ring *ring = &adev->uvd.ring; 146 uint32_t tmp; 147 int r; 148 149 r = uvd_v6_0_start(adev); 150 if (r) 151 goto done; 152 153 ring->ready = true; 154 r = amdgpu_ring_test_ring(ring); 155 if (r) { 156 ring->ready = false; 157 goto done; 158 } 159 160 r = amdgpu_ring_alloc(ring, 10); 161 if (r) { 162 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 163 goto done; 164 } 165 166 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 167 amdgpu_ring_write(ring, tmp); 168 amdgpu_ring_write(ring, 0xFFFFF); 169 170 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 171 amdgpu_ring_write(ring, tmp); 172 amdgpu_ring_write(ring, 0xFFFFF); 173 174 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 175 amdgpu_ring_write(ring, tmp); 176 amdgpu_ring_write(ring, 0xFFFFF); 177 178 /* Clear timeout status bits */ 179 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 180 amdgpu_ring_write(ring, 0x8); 181 182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 183 amdgpu_ring_write(ring, 3); 184 185 amdgpu_ring_commit(ring); 186 187 done: 188 if (!r) 189 DRM_INFO("UVD initialized successfully.\n"); 190 191 return r; 192 } 193 194 /** 195 * uvd_v6_0_hw_fini - stop the hardware block 196 * 197 * @adev: amdgpu_device pointer 198 * 199 * Stop the UVD block, mark ring as not ready any more 200 */ 201 static int uvd_v6_0_hw_fini(void *handle) 202 { 203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 204 struct amdgpu_ring *ring = &adev->uvd.ring; 205 206 uvd_v6_0_stop(adev); 207 ring->ready = false; 208 209 return 0; 210 } 211 212 static int uvd_v6_0_suspend(void *handle) 213 { 214 int r; 215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 216 217 /* Skip this for APU for now */ 218 if (!(adev->flags & AMD_IS_APU)) { 219 r = amdgpu_uvd_suspend(adev); 220 if (r) 221 return r; 222 } 223 r = uvd_v6_0_hw_fini(adev); 224 if (r) 225 return r; 226 227 return r; 228 } 229 230 static int uvd_v6_0_resume(void *handle) 231 { 232 int r; 233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 234 235 /* Skip this for APU for now */ 236 if (!(adev->flags & AMD_IS_APU)) { 237 r = amdgpu_uvd_resume(adev); 238 if (r) 239 return r; 240 } 241 r = uvd_v6_0_hw_init(adev); 242 if (r) 243 return r; 244 245 return r; 246 } 247 248 /** 249 * uvd_v6_0_mc_resume - memory controller programming 250 * 251 * @adev: amdgpu_device pointer 252 * 253 * Let the UVD memory controller know it's offsets 254 */ 255 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 256 { 257 uint64_t offset; 258 uint32_t size; 259 260 /* programm memory controller bits 0-27 */ 261 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 262 lower_32_bits(adev->uvd.gpu_addr)); 263 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 264 upper_32_bits(adev->uvd.gpu_addr)); 265 266 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 267 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 268 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 269 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 270 271 offset += size; 272 size = AMDGPU_UVD_STACK_SIZE; 273 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 274 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 275 276 offset += size; 277 size = AMDGPU_UVD_HEAP_SIZE; 278 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 279 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 280 281 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 282 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 283 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 284 } 285 286 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 287 bool enable) 288 { 289 u32 data, data1; 290 291 data = RREG32(mmUVD_CGC_GATE); 292 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 293 if (enable) { 294 data |= UVD_CGC_GATE__SYS_MASK | 295 UVD_CGC_GATE__UDEC_MASK | 296 UVD_CGC_GATE__MPEG2_MASK | 297 UVD_CGC_GATE__RBC_MASK | 298 UVD_CGC_GATE__LMI_MC_MASK | 299 UVD_CGC_GATE__IDCT_MASK | 300 UVD_CGC_GATE__MPRD_MASK | 301 UVD_CGC_GATE__MPC_MASK | 302 UVD_CGC_GATE__LBSI_MASK | 303 UVD_CGC_GATE__LRBBM_MASK | 304 UVD_CGC_GATE__UDEC_RE_MASK | 305 UVD_CGC_GATE__UDEC_CM_MASK | 306 UVD_CGC_GATE__UDEC_IT_MASK | 307 UVD_CGC_GATE__UDEC_DB_MASK | 308 UVD_CGC_GATE__UDEC_MP_MASK | 309 UVD_CGC_GATE__WCB_MASK | 310 UVD_CGC_GATE__VCPU_MASK | 311 UVD_CGC_GATE__SCPU_MASK; 312 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 313 UVD_SUVD_CGC_GATE__SIT_MASK | 314 UVD_SUVD_CGC_GATE__SMP_MASK | 315 UVD_SUVD_CGC_GATE__SCM_MASK | 316 UVD_SUVD_CGC_GATE__SDB_MASK | 317 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 318 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 319 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 320 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 321 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 322 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 323 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 324 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 325 } else { 326 data &= ~(UVD_CGC_GATE__SYS_MASK | 327 UVD_CGC_GATE__UDEC_MASK | 328 UVD_CGC_GATE__MPEG2_MASK | 329 UVD_CGC_GATE__RBC_MASK | 330 UVD_CGC_GATE__LMI_MC_MASK | 331 UVD_CGC_GATE__LMI_UMC_MASK | 332 UVD_CGC_GATE__IDCT_MASK | 333 UVD_CGC_GATE__MPRD_MASK | 334 UVD_CGC_GATE__MPC_MASK | 335 UVD_CGC_GATE__LBSI_MASK | 336 UVD_CGC_GATE__LRBBM_MASK | 337 UVD_CGC_GATE__UDEC_RE_MASK | 338 UVD_CGC_GATE__UDEC_CM_MASK | 339 UVD_CGC_GATE__UDEC_IT_MASK | 340 UVD_CGC_GATE__UDEC_DB_MASK | 341 UVD_CGC_GATE__UDEC_MP_MASK | 342 UVD_CGC_GATE__WCB_MASK | 343 UVD_CGC_GATE__VCPU_MASK | 344 UVD_CGC_GATE__SCPU_MASK); 345 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 346 UVD_SUVD_CGC_GATE__SIT_MASK | 347 UVD_SUVD_CGC_GATE__SMP_MASK | 348 UVD_SUVD_CGC_GATE__SCM_MASK | 349 UVD_SUVD_CGC_GATE__SDB_MASK | 350 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 351 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 352 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 353 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 354 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 355 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 356 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 357 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); 358 } 359 WREG32(mmUVD_CGC_GATE, data); 360 WREG32(mmUVD_SUVD_CGC_GATE, data1); 361 } 362 363 static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 364 bool enable) 365 { 366 u32 data, data1; 367 368 data = RREG32(mmUVD_CGC_GATE); 369 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 370 if (enable) { 371 data |= UVD_CGC_GATE__SYS_MASK | 372 UVD_CGC_GATE__UDEC_MASK | 373 UVD_CGC_GATE__MPEG2_MASK | 374 UVD_CGC_GATE__RBC_MASK | 375 UVD_CGC_GATE__LMI_MC_MASK | 376 UVD_CGC_GATE__IDCT_MASK | 377 UVD_CGC_GATE__MPRD_MASK | 378 UVD_CGC_GATE__MPC_MASK | 379 UVD_CGC_GATE__LBSI_MASK | 380 UVD_CGC_GATE__LRBBM_MASK | 381 UVD_CGC_GATE__UDEC_RE_MASK | 382 UVD_CGC_GATE__UDEC_CM_MASK | 383 UVD_CGC_GATE__UDEC_IT_MASK | 384 UVD_CGC_GATE__UDEC_DB_MASK | 385 UVD_CGC_GATE__UDEC_MP_MASK | 386 UVD_CGC_GATE__WCB_MASK | 387 UVD_CGC_GATE__VCPU_MASK | 388 UVD_CGC_GATE__SCPU_MASK; 389 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 390 UVD_SUVD_CGC_GATE__SIT_MASK | 391 UVD_SUVD_CGC_GATE__SMP_MASK | 392 UVD_SUVD_CGC_GATE__SCM_MASK | 393 UVD_SUVD_CGC_GATE__SDB_MASK; 394 } else { 395 data &= ~(UVD_CGC_GATE__SYS_MASK | 396 UVD_CGC_GATE__UDEC_MASK | 397 UVD_CGC_GATE__MPEG2_MASK | 398 UVD_CGC_GATE__RBC_MASK | 399 UVD_CGC_GATE__LMI_MC_MASK | 400 UVD_CGC_GATE__LMI_UMC_MASK | 401 UVD_CGC_GATE__IDCT_MASK | 402 UVD_CGC_GATE__MPRD_MASK | 403 UVD_CGC_GATE__MPC_MASK | 404 UVD_CGC_GATE__LBSI_MASK | 405 UVD_CGC_GATE__LRBBM_MASK | 406 UVD_CGC_GATE__UDEC_RE_MASK | 407 UVD_CGC_GATE__UDEC_CM_MASK | 408 UVD_CGC_GATE__UDEC_IT_MASK | 409 UVD_CGC_GATE__UDEC_DB_MASK | 410 UVD_CGC_GATE__UDEC_MP_MASK | 411 UVD_CGC_GATE__WCB_MASK | 412 UVD_CGC_GATE__VCPU_MASK | 413 UVD_CGC_GATE__SCPU_MASK); 414 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 415 UVD_SUVD_CGC_GATE__SIT_MASK | 416 UVD_SUVD_CGC_GATE__SMP_MASK | 417 UVD_SUVD_CGC_GATE__SCM_MASK | 418 UVD_SUVD_CGC_GATE__SDB_MASK); 419 } 420 WREG32(mmUVD_CGC_GATE, data); 421 WREG32(mmUVD_SUVD_CGC_GATE, data1); 422 } 423 424 static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev, 425 bool swmode) 426 { 427 u32 data, data1 = 0, data2; 428 429 /* Always un-gate UVD REGS bit */ 430 data = RREG32(mmUVD_CGC_GATE); 431 data &= ~(UVD_CGC_GATE__REGS_MASK); 432 WREG32(mmUVD_CGC_GATE, data); 433 434 data = RREG32(mmUVD_CGC_CTRL); 435 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 436 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 437 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 438 1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) | 439 4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY); 440 441 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 442 if (swmode) { 443 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 444 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 445 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 446 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 447 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 448 UVD_CGC_CTRL__SYS_MODE_MASK | 449 UVD_CGC_CTRL__UDEC_MODE_MASK | 450 UVD_CGC_CTRL__MPEG2_MODE_MASK | 451 UVD_CGC_CTRL__REGS_MODE_MASK | 452 UVD_CGC_CTRL__RBC_MODE_MASK | 453 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 454 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 455 UVD_CGC_CTRL__IDCT_MODE_MASK | 456 UVD_CGC_CTRL__MPRD_MODE_MASK | 457 UVD_CGC_CTRL__MPC_MODE_MASK | 458 UVD_CGC_CTRL__LBSI_MODE_MASK | 459 UVD_CGC_CTRL__LRBBM_MODE_MASK | 460 UVD_CGC_CTRL__WCB_MODE_MASK | 461 UVD_CGC_CTRL__VCPU_MODE_MASK | 462 UVD_CGC_CTRL__JPEG_MODE_MASK | 463 UVD_CGC_CTRL__SCPU_MODE_MASK); 464 data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 465 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK; 466 data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK; 467 data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID); 468 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 469 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 470 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 471 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 472 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 473 } else { 474 data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 475 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 476 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 477 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 478 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 479 UVD_CGC_CTRL__SYS_MODE_MASK | 480 UVD_CGC_CTRL__UDEC_MODE_MASK | 481 UVD_CGC_CTRL__MPEG2_MODE_MASK | 482 UVD_CGC_CTRL__REGS_MODE_MASK | 483 UVD_CGC_CTRL__RBC_MODE_MASK | 484 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 485 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 486 UVD_CGC_CTRL__IDCT_MODE_MASK | 487 UVD_CGC_CTRL__MPRD_MODE_MASK | 488 UVD_CGC_CTRL__MPC_MODE_MASK | 489 UVD_CGC_CTRL__LBSI_MODE_MASK | 490 UVD_CGC_CTRL__LRBBM_MODE_MASK | 491 UVD_CGC_CTRL__WCB_MODE_MASK | 492 UVD_CGC_CTRL__VCPU_MODE_MASK | 493 UVD_CGC_CTRL__SCPU_MODE_MASK; 494 data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 495 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 496 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 497 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 498 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK; 499 } 500 WREG32(mmUVD_CGC_CTRL, data); 501 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 502 503 data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2); 504 data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) | 505 REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) | 506 REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID)); 507 data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) | 508 REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) | 509 REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID)); 510 data |= data1; 511 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data); 512 } 513 514 /** 515 * uvd_v6_0_start - start UVD block 516 * 517 * @adev: amdgpu_device pointer 518 * 519 * Setup and start the UVD block 520 */ 521 static int uvd_v6_0_start(struct amdgpu_device *adev) 522 { 523 struct amdgpu_ring *ring = &adev->uvd.ring; 524 uint32_t rb_bufsz, tmp; 525 uint32_t lmi_swap_cntl; 526 uint32_t mp_swap_cntl; 527 int i, j, r; 528 529 /*disable DPG */ 530 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 531 532 /* disable byte swapping */ 533 lmi_swap_cntl = 0; 534 mp_swap_cntl = 0; 535 536 uvd_v6_0_mc_resume(adev); 537 538 /* Set dynamic clock gating in S/W control mode */ 539 if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) { 540 if (adev->flags & AMD_IS_APU) 541 cz_set_uvd_clock_gating_branches(adev, false); 542 else 543 tonga_set_uvd_clock_gating_branches(adev, false); 544 uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true); 545 } else { 546 /* disable clock gating */ 547 uint32_t data = RREG32(mmUVD_CGC_CTRL); 548 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 549 WREG32(mmUVD_CGC_CTRL, data); 550 } 551 552 /* disable interupt */ 553 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 554 555 /* stall UMC and register bus before resetting VCPU */ 556 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 557 mdelay(1); 558 559 /* put LMI, VCPU, RBC etc... into reset */ 560 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 561 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 562 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 563 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 564 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 565 mdelay(5); 566 567 /* take UVD block out of reset */ 568 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 569 mdelay(5); 570 571 /* initialize UVD memory controller */ 572 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 573 (1 << 21) | (1 << 9) | (1 << 20)); 574 575 #ifdef __BIG_ENDIAN 576 /* swap (8 in 32) RB and IB */ 577 lmi_swap_cntl = 0xa; 578 mp_swap_cntl = 0; 579 #endif 580 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 581 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 582 583 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 584 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 585 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 586 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 587 WREG32(mmUVD_MPC_SET_ALU, 0); 588 WREG32(mmUVD_MPC_SET_MUX, 0x88); 589 590 /* take all subblocks out of reset, except VCPU */ 591 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 592 mdelay(5); 593 594 /* enable VCPU clock */ 595 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 596 597 /* enable UMC */ 598 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 599 600 /* boot up the VCPU */ 601 WREG32(mmUVD_SOFT_RESET, 0); 602 mdelay(10); 603 604 for (i = 0; i < 10; ++i) { 605 uint32_t status; 606 607 for (j = 0; j < 100; ++j) { 608 status = RREG32(mmUVD_STATUS); 609 if (status & 2) 610 break; 611 mdelay(10); 612 } 613 r = 0; 614 if (status & 2) 615 break; 616 617 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 618 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 619 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 620 mdelay(10); 621 WREG32_P(mmUVD_SOFT_RESET, 0, 622 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 623 mdelay(10); 624 r = -1; 625 } 626 627 if (r) { 628 DRM_ERROR("UVD not responding, giving up!!!\n"); 629 return r; 630 } 631 /* enable master interrupt */ 632 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 633 634 /* clear the bit 4 of UVD_STATUS */ 635 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 636 637 rb_bufsz = order_base_2(ring->ring_size); 638 tmp = 0; 639 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 640 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 641 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 642 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 643 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 644 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 645 /* force RBC into idle state */ 646 WREG32(mmUVD_RBC_RB_CNTL, tmp); 647 648 /* set the write pointer delay */ 649 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 650 651 /* set the wb address */ 652 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 653 654 /* programm the RB_BASE for ring buffer */ 655 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 656 lower_32_bits(ring->gpu_addr)); 657 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 658 upper_32_bits(ring->gpu_addr)); 659 660 /* Initialize the ring buffer's read and write pointers */ 661 WREG32(mmUVD_RBC_RB_RPTR, 0); 662 663 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 664 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 665 666 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 667 668 return 0; 669 } 670 671 /** 672 * uvd_v6_0_stop - stop UVD block 673 * 674 * @adev: amdgpu_device pointer 675 * 676 * stop the UVD block 677 */ 678 static void uvd_v6_0_stop(struct amdgpu_device *adev) 679 { 680 /* force RBC into idle state */ 681 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 682 683 /* Stall UMC and register bus before resetting VCPU */ 684 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 685 mdelay(1); 686 687 /* put VCPU into reset */ 688 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 689 mdelay(5); 690 691 /* disable VCPU clock */ 692 WREG32(mmUVD_VCPU_CNTL, 0x0); 693 694 /* Unstall UMC and register bus */ 695 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 696 } 697 698 /** 699 * uvd_v6_0_ring_emit_fence - emit an fence & trap command 700 * 701 * @ring: amdgpu_ring pointer 702 * @fence: fence to emit 703 * 704 * Write a fence and a trap command to the ring. 705 */ 706 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 707 unsigned flags) 708 { 709 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 710 711 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 712 amdgpu_ring_write(ring, seq); 713 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 714 amdgpu_ring_write(ring, addr & 0xffffffff); 715 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 716 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 717 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 718 amdgpu_ring_write(ring, 0); 719 720 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 721 amdgpu_ring_write(ring, 0); 722 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 723 amdgpu_ring_write(ring, 0); 724 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 725 amdgpu_ring_write(ring, 2); 726 } 727 728 /** 729 * uvd_v6_0_ring_test_ring - register write test 730 * 731 * @ring: amdgpu_ring pointer 732 * 733 * Test if we can successfully write to the context register 734 */ 735 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) 736 { 737 struct amdgpu_device *adev = ring->adev; 738 uint32_t tmp = 0; 739 unsigned i; 740 int r; 741 742 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 743 r = amdgpu_ring_alloc(ring, 3); 744 if (r) { 745 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 746 ring->idx, r); 747 return r; 748 } 749 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 750 amdgpu_ring_write(ring, 0xDEADBEEF); 751 amdgpu_ring_commit(ring); 752 for (i = 0; i < adev->usec_timeout; i++) { 753 tmp = RREG32(mmUVD_CONTEXT_ID); 754 if (tmp == 0xDEADBEEF) 755 break; 756 DRM_UDELAY(1); 757 } 758 759 if (i < adev->usec_timeout) { 760 DRM_INFO("ring test on %d succeeded in %d usecs\n", 761 ring->idx, i); 762 } else { 763 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 764 ring->idx, tmp); 765 r = -EINVAL; 766 } 767 return r; 768 } 769 770 /** 771 * uvd_v6_0_ring_emit_ib - execute indirect buffer 772 * 773 * @ring: amdgpu_ring pointer 774 * @ib: indirect buffer to execute 775 * 776 * Write ring commands to execute the indirect buffer 777 */ 778 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 779 struct amdgpu_ib *ib) 780 { 781 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 782 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 783 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 784 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 785 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 786 amdgpu_ring_write(ring, ib->length_dw); 787 } 788 789 /** 790 * uvd_v6_0_ring_test_ib - test ib execution 791 * 792 * @ring: amdgpu_ring pointer 793 * 794 * Test if we can successfully execute an IB 795 */ 796 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring) 797 { 798 struct fence *fence = NULL; 799 int r; 800 801 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 802 if (r) { 803 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 804 goto error; 805 } 806 807 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 808 if (r) { 809 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 810 goto error; 811 } 812 813 r = fence_wait(fence, false); 814 if (r) { 815 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 816 goto error; 817 } 818 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 819 error: 820 fence_put(fence); 821 return r; 822 } 823 824 static bool uvd_v6_0_is_idle(void *handle) 825 { 826 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 827 828 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 829 } 830 831 static int uvd_v6_0_wait_for_idle(void *handle) 832 { 833 unsigned i; 834 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 835 836 for (i = 0; i < adev->usec_timeout; i++) { 837 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 838 return 0; 839 } 840 return -ETIMEDOUT; 841 } 842 843 static int uvd_v6_0_soft_reset(void *handle) 844 { 845 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 846 847 uvd_v6_0_stop(adev); 848 849 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 850 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 851 mdelay(5); 852 853 return uvd_v6_0_start(adev); 854 } 855 856 static void uvd_v6_0_print_status(void *handle) 857 { 858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 859 dev_info(adev->dev, "UVD 6.0 registers\n"); 860 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 861 RREG32(mmUVD_SEMA_ADDR_LOW)); 862 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 863 RREG32(mmUVD_SEMA_ADDR_HIGH)); 864 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 865 RREG32(mmUVD_SEMA_CMD)); 866 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 867 RREG32(mmUVD_GPCOM_VCPU_CMD)); 868 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 869 RREG32(mmUVD_GPCOM_VCPU_DATA0)); 870 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 871 RREG32(mmUVD_GPCOM_VCPU_DATA1)); 872 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 873 RREG32(mmUVD_ENGINE_CNTL)); 874 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 875 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 876 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 877 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 878 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 879 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 880 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 881 RREG32(mmUVD_SEMA_CNTL)); 882 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 883 RREG32(mmUVD_LMI_EXT40_ADDR)); 884 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 885 RREG32(mmUVD_CTX_INDEX)); 886 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 887 RREG32(mmUVD_CTX_DATA)); 888 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 889 RREG32(mmUVD_CGC_GATE)); 890 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 891 RREG32(mmUVD_CGC_CTRL)); 892 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 893 RREG32(mmUVD_LMI_CTRL2)); 894 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 895 RREG32(mmUVD_MASTINT_EN)); 896 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 897 RREG32(mmUVD_LMI_ADDR_EXT)); 898 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 899 RREG32(mmUVD_LMI_CTRL)); 900 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 901 RREG32(mmUVD_LMI_SWAP_CNTL)); 902 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 903 RREG32(mmUVD_MP_SWAP_CNTL)); 904 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 905 RREG32(mmUVD_MPC_SET_MUXA0)); 906 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 907 RREG32(mmUVD_MPC_SET_MUXA1)); 908 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 909 RREG32(mmUVD_MPC_SET_MUXB0)); 910 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 911 RREG32(mmUVD_MPC_SET_MUXB1)); 912 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 913 RREG32(mmUVD_MPC_SET_MUX)); 914 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 915 RREG32(mmUVD_MPC_SET_ALU)); 916 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 917 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 918 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 919 RREG32(mmUVD_VCPU_CACHE_SIZE0)); 920 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 921 RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 922 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 923 RREG32(mmUVD_VCPU_CACHE_SIZE1)); 924 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 925 RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 926 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 927 RREG32(mmUVD_VCPU_CACHE_SIZE2)); 928 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 929 RREG32(mmUVD_VCPU_CNTL)); 930 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 931 RREG32(mmUVD_SOFT_RESET)); 932 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 933 RREG32(mmUVD_RBC_IB_SIZE)); 934 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 935 RREG32(mmUVD_RBC_RB_RPTR)); 936 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 937 RREG32(mmUVD_RBC_RB_WPTR)); 938 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 939 RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 940 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 941 RREG32(mmUVD_RBC_RB_CNTL)); 942 dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 943 RREG32(mmUVD_STATUS)); 944 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 945 RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 946 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 947 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 948 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 949 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 950 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 951 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 952 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 953 RREG32(mmUVD_CONTEXT_ID)); 954 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 955 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 956 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 957 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 958 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 959 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 960 } 961 962 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 963 struct amdgpu_irq_src *source, 964 unsigned type, 965 enum amdgpu_interrupt_state state) 966 { 967 // TODO 968 return 0; 969 } 970 971 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, 972 struct amdgpu_irq_src *source, 973 struct amdgpu_iv_entry *entry) 974 { 975 DRM_DEBUG("IH: UVD TRAP\n"); 976 amdgpu_fence_process(&adev->uvd.ring); 977 return 0; 978 } 979 980 static int uvd_v6_0_set_clockgating_state(void *handle, 981 enum amd_clockgating_state state) 982 { 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 984 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 985 986 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 987 return 0; 988 989 if (enable) { 990 if (adev->flags & AMD_IS_APU) 991 cz_set_uvd_clock_gating_branches(adev, enable); 992 else 993 tonga_set_uvd_clock_gating_branches(adev, enable); 994 uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true); 995 } else { 996 uint32_t data = RREG32(mmUVD_CGC_CTRL); 997 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 998 WREG32(mmUVD_CGC_CTRL, data); 999 } 1000 1001 return 0; 1002 } 1003 1004 static int uvd_v6_0_set_powergating_state(void *handle, 1005 enum amd_powergating_state state) 1006 { 1007 /* This doesn't actually powergate the UVD block. 1008 * That's done in the dpm code via the SMC. This 1009 * just re-inits the block as necessary. The actual 1010 * gating still happens in the dpm code. We should 1011 * revisit this when there is a cleaner line between 1012 * the smc and the hw blocks 1013 */ 1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1015 1016 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1017 return 0; 1018 1019 if (state == AMD_PG_STATE_GATE) { 1020 uvd_v6_0_stop(adev); 1021 return 0; 1022 } else { 1023 return uvd_v6_0_start(adev); 1024 } 1025 } 1026 1027 const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 1028 .early_init = uvd_v6_0_early_init, 1029 .late_init = NULL, 1030 .sw_init = uvd_v6_0_sw_init, 1031 .sw_fini = uvd_v6_0_sw_fini, 1032 .hw_init = uvd_v6_0_hw_init, 1033 .hw_fini = uvd_v6_0_hw_fini, 1034 .suspend = uvd_v6_0_suspend, 1035 .resume = uvd_v6_0_resume, 1036 .is_idle = uvd_v6_0_is_idle, 1037 .wait_for_idle = uvd_v6_0_wait_for_idle, 1038 .soft_reset = uvd_v6_0_soft_reset, 1039 .print_status = uvd_v6_0_print_status, 1040 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 1041 .set_powergating_state = uvd_v6_0_set_powergating_state, 1042 }; 1043 1044 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { 1045 .get_rptr = uvd_v6_0_ring_get_rptr, 1046 .get_wptr = uvd_v6_0_ring_get_wptr, 1047 .set_wptr = uvd_v6_0_ring_set_wptr, 1048 .parse_cs = amdgpu_uvd_ring_parse_cs, 1049 .emit_ib = uvd_v6_0_ring_emit_ib, 1050 .emit_fence = uvd_v6_0_ring_emit_fence, 1051 .test_ring = uvd_v6_0_ring_test_ring, 1052 .test_ib = uvd_v6_0_ring_test_ib, 1053 .insert_nop = amdgpu_ring_insert_nop, 1054 .pad_ib = amdgpu_ring_generic_pad_ib, 1055 }; 1056 1057 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1058 { 1059 adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs; 1060 } 1061 1062 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { 1063 .set = uvd_v6_0_set_interrupt_state, 1064 .process = uvd_v6_0_process_interrupt, 1065 }; 1066 1067 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1068 { 1069 adev->uvd.irq.num_types = 1; 1070 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; 1071 } 1072