1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_6_0_d.h" 31 #include "uvd/uvd_6_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 #include "smu/smu_7_1_3_d.h" 35 #include "smu/smu_7_1_3_sh_mask.h" 36 #include "vi.h" 37 38 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); 39 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); 40 static int uvd_v6_0_start(struct amdgpu_device *adev); 41 static void uvd_v6_0_stop(struct amdgpu_device *adev); 42 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); 43 44 /** 45 * uvd_v6_0_ring_get_rptr - get read pointer 46 * 47 * @ring: amdgpu_ring pointer 48 * 49 * Returns the current hardware read pointer 50 */ 51 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 52 { 53 struct amdgpu_device *adev = ring->adev; 54 55 return RREG32(mmUVD_RBC_RB_RPTR); 56 } 57 58 /** 59 * uvd_v6_0_ring_get_wptr - get write pointer 60 * 61 * @ring: amdgpu_ring pointer 62 * 63 * Returns the current hardware write pointer 64 */ 65 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 66 { 67 struct amdgpu_device *adev = ring->adev; 68 69 return RREG32(mmUVD_RBC_RB_WPTR); 70 } 71 72 /** 73 * uvd_v6_0_ring_set_wptr - set write pointer 74 * 75 * @ring: amdgpu_ring pointer 76 * 77 * Commits the write pointer to the hardware 78 */ 79 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 80 { 81 struct amdgpu_device *adev = ring->adev; 82 83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 84 } 85 86 static int uvd_v6_0_early_init(void *handle) 87 { 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 90 uvd_v6_0_set_ring_funcs(adev); 91 uvd_v6_0_set_irq_funcs(adev); 92 93 return 0; 94 } 95 96 static int uvd_v6_0_sw_init(void *handle) 97 { 98 struct amdgpu_ring *ring; 99 int r; 100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 101 102 /* UVD TRAP */ 103 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 104 if (r) 105 return r; 106 107 r = amdgpu_uvd_sw_init(adev); 108 if (r) 109 return r; 110 111 r = amdgpu_uvd_resume(adev); 112 if (r) 113 return r; 114 115 ring = &adev->uvd.ring; 116 sprintf(ring->name, "uvd"); 117 r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, 118 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 119 120 return r; 121 } 122 123 static int uvd_v6_0_sw_fini(void *handle) 124 { 125 int r; 126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 127 128 r = amdgpu_uvd_suspend(adev); 129 if (r) 130 return r; 131 132 r = amdgpu_uvd_sw_fini(adev); 133 if (r) 134 return r; 135 136 return r; 137 } 138 139 /** 140 * uvd_v6_0_hw_init - start and test UVD block 141 * 142 * @adev: amdgpu_device pointer 143 * 144 * Initialize the hardware, boot up the VCPU and do some testing 145 */ 146 static int uvd_v6_0_hw_init(void *handle) 147 { 148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 149 struct amdgpu_ring *ring = &adev->uvd.ring; 150 uint32_t tmp; 151 int r; 152 153 r = uvd_v6_0_start(adev); 154 if (r) 155 goto done; 156 157 ring->ready = true; 158 r = amdgpu_ring_test_ring(ring); 159 if (r) { 160 ring->ready = false; 161 goto done; 162 } 163 164 r = amdgpu_ring_alloc(ring, 10); 165 if (r) { 166 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 167 goto done; 168 } 169 170 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 171 amdgpu_ring_write(ring, tmp); 172 amdgpu_ring_write(ring, 0xFFFFF); 173 174 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 175 amdgpu_ring_write(ring, tmp); 176 amdgpu_ring_write(ring, 0xFFFFF); 177 178 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 179 amdgpu_ring_write(ring, tmp); 180 amdgpu_ring_write(ring, 0xFFFFF); 181 182 /* Clear timeout status bits */ 183 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 184 amdgpu_ring_write(ring, 0x8); 185 186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 187 amdgpu_ring_write(ring, 3); 188 189 amdgpu_ring_commit(ring); 190 191 done: 192 if (!r) 193 DRM_INFO("UVD initialized successfully.\n"); 194 195 return r; 196 } 197 198 /** 199 * uvd_v6_0_hw_fini - stop the hardware block 200 * 201 * @adev: amdgpu_device pointer 202 * 203 * Stop the UVD block, mark ring as not ready any more 204 */ 205 static int uvd_v6_0_hw_fini(void *handle) 206 { 207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 208 struct amdgpu_ring *ring = &adev->uvd.ring; 209 210 uvd_v6_0_stop(adev); 211 ring->ready = false; 212 213 return 0; 214 } 215 216 static int uvd_v6_0_suspend(void *handle) 217 { 218 int r; 219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 220 221 r = uvd_v6_0_hw_fini(adev); 222 if (r) 223 return r; 224 225 /* Skip this for APU for now */ 226 if (!(adev->flags & AMD_IS_APU)) { 227 r = amdgpu_uvd_suspend(adev); 228 if (r) 229 return r; 230 } 231 232 return r; 233 } 234 235 static int uvd_v6_0_resume(void *handle) 236 { 237 int r; 238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 239 240 /* Skip this for APU for now */ 241 if (!(adev->flags & AMD_IS_APU)) { 242 r = amdgpu_uvd_resume(adev); 243 if (r) 244 return r; 245 } 246 r = uvd_v6_0_hw_init(adev); 247 if (r) 248 return r; 249 250 return r; 251 } 252 253 /** 254 * uvd_v6_0_mc_resume - memory controller programming 255 * 256 * @adev: amdgpu_device pointer 257 * 258 * Let the UVD memory controller know it's offsets 259 */ 260 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 261 { 262 uint64_t offset; 263 uint32_t size; 264 265 /* programm memory controller bits 0-27 */ 266 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 267 lower_32_bits(adev->uvd.gpu_addr)); 268 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 269 upper_32_bits(adev->uvd.gpu_addr)); 270 271 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 272 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 273 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 274 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 275 276 offset += size; 277 size = AMDGPU_UVD_HEAP_SIZE; 278 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 279 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 280 281 offset += size; 282 size = AMDGPU_UVD_STACK_SIZE + 283 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 284 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 285 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 286 287 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 288 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 289 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 290 291 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 292 } 293 294 #if 0 295 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 296 bool enable) 297 { 298 u32 data, data1; 299 300 data = RREG32(mmUVD_CGC_GATE); 301 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 302 if (enable) { 303 data |= UVD_CGC_GATE__SYS_MASK | 304 UVD_CGC_GATE__UDEC_MASK | 305 UVD_CGC_GATE__MPEG2_MASK | 306 UVD_CGC_GATE__RBC_MASK | 307 UVD_CGC_GATE__LMI_MC_MASK | 308 UVD_CGC_GATE__IDCT_MASK | 309 UVD_CGC_GATE__MPRD_MASK | 310 UVD_CGC_GATE__MPC_MASK | 311 UVD_CGC_GATE__LBSI_MASK | 312 UVD_CGC_GATE__LRBBM_MASK | 313 UVD_CGC_GATE__UDEC_RE_MASK | 314 UVD_CGC_GATE__UDEC_CM_MASK | 315 UVD_CGC_GATE__UDEC_IT_MASK | 316 UVD_CGC_GATE__UDEC_DB_MASK | 317 UVD_CGC_GATE__UDEC_MP_MASK | 318 UVD_CGC_GATE__WCB_MASK | 319 UVD_CGC_GATE__VCPU_MASK | 320 UVD_CGC_GATE__SCPU_MASK; 321 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 322 UVD_SUVD_CGC_GATE__SIT_MASK | 323 UVD_SUVD_CGC_GATE__SMP_MASK | 324 UVD_SUVD_CGC_GATE__SCM_MASK | 325 UVD_SUVD_CGC_GATE__SDB_MASK | 326 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 327 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 328 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 329 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 330 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 331 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 332 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 333 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 334 } else { 335 data &= ~(UVD_CGC_GATE__SYS_MASK | 336 UVD_CGC_GATE__UDEC_MASK | 337 UVD_CGC_GATE__MPEG2_MASK | 338 UVD_CGC_GATE__RBC_MASK | 339 UVD_CGC_GATE__LMI_MC_MASK | 340 UVD_CGC_GATE__LMI_UMC_MASK | 341 UVD_CGC_GATE__IDCT_MASK | 342 UVD_CGC_GATE__MPRD_MASK | 343 UVD_CGC_GATE__MPC_MASK | 344 UVD_CGC_GATE__LBSI_MASK | 345 UVD_CGC_GATE__LRBBM_MASK | 346 UVD_CGC_GATE__UDEC_RE_MASK | 347 UVD_CGC_GATE__UDEC_CM_MASK | 348 UVD_CGC_GATE__UDEC_IT_MASK | 349 UVD_CGC_GATE__UDEC_DB_MASK | 350 UVD_CGC_GATE__UDEC_MP_MASK | 351 UVD_CGC_GATE__WCB_MASK | 352 UVD_CGC_GATE__VCPU_MASK | 353 UVD_CGC_GATE__SCPU_MASK); 354 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 355 UVD_SUVD_CGC_GATE__SIT_MASK | 356 UVD_SUVD_CGC_GATE__SMP_MASK | 357 UVD_SUVD_CGC_GATE__SCM_MASK | 358 UVD_SUVD_CGC_GATE__SDB_MASK | 359 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 360 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 361 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 362 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 363 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 364 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 365 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 366 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); 367 } 368 WREG32(mmUVD_CGC_GATE, data); 369 WREG32(mmUVD_SUVD_CGC_GATE, data1); 370 } 371 #endif 372 373 /** 374 * uvd_v6_0_start - start UVD block 375 * 376 * @adev: amdgpu_device pointer 377 * 378 * Setup and start the UVD block 379 */ 380 static int uvd_v6_0_start(struct amdgpu_device *adev) 381 { 382 struct amdgpu_ring *ring = &adev->uvd.ring; 383 uint32_t rb_bufsz, tmp; 384 uint32_t lmi_swap_cntl; 385 uint32_t mp_swap_cntl; 386 int i, j, r; 387 388 /*disable DPG */ 389 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 390 391 /* disable byte swapping */ 392 lmi_swap_cntl = 0; 393 mp_swap_cntl = 0; 394 395 uvd_v6_0_mc_resume(adev); 396 397 /* Set dynamic clock gating in S/W control mode */ 398 if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) { 399 uvd_v6_0_set_sw_clock_gating(adev); 400 } else { 401 /* disable clock gating */ 402 uint32_t data = RREG32(mmUVD_CGC_CTRL); 403 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 404 WREG32(mmUVD_CGC_CTRL, data); 405 } 406 407 /* disable interupt */ 408 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 409 410 /* stall UMC and register bus before resetting VCPU */ 411 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 412 mdelay(1); 413 414 /* put LMI, VCPU, RBC etc... into reset */ 415 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 416 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 417 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 418 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 419 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 420 mdelay(5); 421 422 /* take UVD block out of reset */ 423 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 424 mdelay(5); 425 426 /* initialize UVD memory controller */ 427 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 428 (1 << 21) | (1 << 9) | (1 << 20)); 429 430 #ifdef __BIG_ENDIAN 431 /* swap (8 in 32) RB and IB */ 432 lmi_swap_cntl = 0xa; 433 mp_swap_cntl = 0; 434 #endif 435 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 436 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 437 438 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 439 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 440 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 441 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 442 WREG32(mmUVD_MPC_SET_ALU, 0); 443 WREG32(mmUVD_MPC_SET_MUX, 0x88); 444 445 /* take all subblocks out of reset, except VCPU */ 446 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 447 mdelay(5); 448 449 /* enable VCPU clock */ 450 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 451 452 /* enable UMC */ 453 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 454 455 /* boot up the VCPU */ 456 WREG32(mmUVD_SOFT_RESET, 0); 457 mdelay(10); 458 459 for (i = 0; i < 10; ++i) { 460 uint32_t status; 461 462 for (j = 0; j < 100; ++j) { 463 status = RREG32(mmUVD_STATUS); 464 if (status & 2) 465 break; 466 mdelay(10); 467 } 468 r = 0; 469 if (status & 2) 470 break; 471 472 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 473 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 474 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 475 mdelay(10); 476 WREG32_P(mmUVD_SOFT_RESET, 0, 477 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 478 mdelay(10); 479 r = -1; 480 } 481 482 if (r) { 483 DRM_ERROR("UVD not responding, giving up!!!\n"); 484 return r; 485 } 486 /* enable master interrupt */ 487 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 488 489 /* clear the bit 4 of UVD_STATUS */ 490 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 491 492 rb_bufsz = order_base_2(ring->ring_size); 493 tmp = 0; 494 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 495 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 496 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 497 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 498 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 499 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 500 /* force RBC into idle state */ 501 WREG32(mmUVD_RBC_RB_CNTL, tmp); 502 503 /* set the write pointer delay */ 504 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 505 506 /* set the wb address */ 507 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 508 509 /* programm the RB_BASE for ring buffer */ 510 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 511 lower_32_bits(ring->gpu_addr)); 512 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 513 upper_32_bits(ring->gpu_addr)); 514 515 /* Initialize the ring buffer's read and write pointers */ 516 WREG32(mmUVD_RBC_RB_RPTR, 0); 517 518 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 519 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 520 521 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 522 523 return 0; 524 } 525 526 /** 527 * uvd_v6_0_stop - stop UVD block 528 * 529 * @adev: amdgpu_device pointer 530 * 531 * stop the UVD block 532 */ 533 static void uvd_v6_0_stop(struct amdgpu_device *adev) 534 { 535 /* force RBC into idle state */ 536 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 537 538 /* Stall UMC and register bus before resetting VCPU */ 539 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 540 mdelay(1); 541 542 /* put VCPU into reset */ 543 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 544 mdelay(5); 545 546 /* disable VCPU clock */ 547 WREG32(mmUVD_VCPU_CNTL, 0x0); 548 549 /* Unstall UMC and register bus */ 550 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 551 } 552 553 /** 554 * uvd_v6_0_ring_emit_fence - emit an fence & trap command 555 * 556 * @ring: amdgpu_ring pointer 557 * @fence: fence to emit 558 * 559 * Write a fence and a trap command to the ring. 560 */ 561 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 562 unsigned flags) 563 { 564 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 565 566 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 567 amdgpu_ring_write(ring, seq); 568 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 569 amdgpu_ring_write(ring, addr & 0xffffffff); 570 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 571 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 572 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 573 amdgpu_ring_write(ring, 0); 574 575 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 576 amdgpu_ring_write(ring, 0); 577 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 578 amdgpu_ring_write(ring, 0); 579 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 580 amdgpu_ring_write(ring, 2); 581 } 582 583 /** 584 * uvd_v6_0_ring_test_ring - register write test 585 * 586 * @ring: amdgpu_ring pointer 587 * 588 * Test if we can successfully write to the context register 589 */ 590 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) 591 { 592 struct amdgpu_device *adev = ring->adev; 593 uint32_t tmp = 0; 594 unsigned i; 595 int r; 596 597 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 598 r = amdgpu_ring_alloc(ring, 3); 599 if (r) { 600 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 601 ring->idx, r); 602 return r; 603 } 604 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 605 amdgpu_ring_write(ring, 0xDEADBEEF); 606 amdgpu_ring_commit(ring); 607 for (i = 0; i < adev->usec_timeout; i++) { 608 tmp = RREG32(mmUVD_CONTEXT_ID); 609 if (tmp == 0xDEADBEEF) 610 break; 611 DRM_UDELAY(1); 612 } 613 614 if (i < adev->usec_timeout) { 615 DRM_INFO("ring test on %d succeeded in %d usecs\n", 616 ring->idx, i); 617 } else { 618 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 619 ring->idx, tmp); 620 r = -EINVAL; 621 } 622 return r; 623 } 624 625 /** 626 * uvd_v6_0_ring_emit_ib - execute indirect buffer 627 * 628 * @ring: amdgpu_ring pointer 629 * @ib: indirect buffer to execute 630 * 631 * Write ring commands to execute the indirect buffer 632 */ 633 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 634 struct amdgpu_ib *ib, 635 unsigned vm_id, bool ctx_switch) 636 { 637 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 638 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 639 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 640 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 641 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 642 amdgpu_ring_write(ring, ib->length_dw); 643 } 644 645 /** 646 * uvd_v6_0_ring_test_ib - test ib execution 647 * 648 * @ring: amdgpu_ring pointer 649 * 650 * Test if we can successfully execute an IB 651 */ 652 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring) 653 { 654 struct fence *fence = NULL; 655 int r; 656 657 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 658 if (r) { 659 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 660 goto error; 661 } 662 663 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 664 if (r) { 665 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 666 goto error; 667 } 668 669 r = fence_wait(fence, false); 670 if (r) { 671 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 672 goto error; 673 } 674 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 675 error: 676 fence_put(fence); 677 return r; 678 } 679 680 static bool uvd_v6_0_is_idle(void *handle) 681 { 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 684 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 685 } 686 687 static int uvd_v6_0_wait_for_idle(void *handle) 688 { 689 unsigned i; 690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 691 692 for (i = 0; i < adev->usec_timeout; i++) { 693 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 694 return 0; 695 } 696 return -ETIMEDOUT; 697 } 698 699 static int uvd_v6_0_soft_reset(void *handle) 700 { 701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 702 703 uvd_v6_0_stop(adev); 704 705 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 706 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 707 mdelay(5); 708 709 return uvd_v6_0_start(adev); 710 } 711 712 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 713 struct amdgpu_irq_src *source, 714 unsigned type, 715 enum amdgpu_interrupt_state state) 716 { 717 // TODO 718 return 0; 719 } 720 721 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, 722 struct amdgpu_irq_src *source, 723 struct amdgpu_iv_entry *entry) 724 { 725 DRM_DEBUG("IH: UVD TRAP\n"); 726 amdgpu_fence_process(&adev->uvd.ring); 727 return 0; 728 } 729 730 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) 731 { 732 uint32_t data, data1, data2, suvd_flags; 733 734 data = RREG32(mmUVD_CGC_CTRL); 735 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 736 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 737 738 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 739 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 740 741 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 742 UVD_SUVD_CGC_GATE__SIT_MASK | 743 UVD_SUVD_CGC_GATE__SMP_MASK | 744 UVD_SUVD_CGC_GATE__SCM_MASK | 745 UVD_SUVD_CGC_GATE__SDB_MASK; 746 747 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 748 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 749 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 750 751 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 752 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 753 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 754 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 755 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 756 UVD_CGC_CTRL__SYS_MODE_MASK | 757 UVD_CGC_CTRL__UDEC_MODE_MASK | 758 UVD_CGC_CTRL__MPEG2_MODE_MASK | 759 UVD_CGC_CTRL__REGS_MODE_MASK | 760 UVD_CGC_CTRL__RBC_MODE_MASK | 761 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 762 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 763 UVD_CGC_CTRL__IDCT_MODE_MASK | 764 UVD_CGC_CTRL__MPRD_MODE_MASK | 765 UVD_CGC_CTRL__MPC_MODE_MASK | 766 UVD_CGC_CTRL__LBSI_MODE_MASK | 767 UVD_CGC_CTRL__LRBBM_MODE_MASK | 768 UVD_CGC_CTRL__WCB_MODE_MASK | 769 UVD_CGC_CTRL__VCPU_MODE_MASK | 770 UVD_CGC_CTRL__JPEG_MODE_MASK | 771 UVD_CGC_CTRL__SCPU_MODE_MASK | 772 UVD_CGC_CTRL__JPEG2_MODE_MASK); 773 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 774 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 775 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 776 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 777 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 778 data1 |= suvd_flags; 779 780 WREG32(mmUVD_CGC_CTRL, data); 781 WREG32(mmUVD_CGC_GATE, 0); 782 WREG32(mmUVD_SUVD_CGC_GATE, data1); 783 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 784 } 785 786 #if 0 787 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 788 { 789 uint32_t data, data1, cgc_flags, suvd_flags; 790 791 data = RREG32(mmUVD_CGC_GATE); 792 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 793 794 cgc_flags = UVD_CGC_GATE__SYS_MASK | 795 UVD_CGC_GATE__UDEC_MASK | 796 UVD_CGC_GATE__MPEG2_MASK | 797 UVD_CGC_GATE__RBC_MASK | 798 UVD_CGC_GATE__LMI_MC_MASK | 799 UVD_CGC_GATE__IDCT_MASK | 800 UVD_CGC_GATE__MPRD_MASK | 801 UVD_CGC_GATE__MPC_MASK | 802 UVD_CGC_GATE__LBSI_MASK | 803 UVD_CGC_GATE__LRBBM_MASK | 804 UVD_CGC_GATE__UDEC_RE_MASK | 805 UVD_CGC_GATE__UDEC_CM_MASK | 806 UVD_CGC_GATE__UDEC_IT_MASK | 807 UVD_CGC_GATE__UDEC_DB_MASK | 808 UVD_CGC_GATE__UDEC_MP_MASK | 809 UVD_CGC_GATE__WCB_MASK | 810 UVD_CGC_GATE__VCPU_MASK | 811 UVD_CGC_GATE__SCPU_MASK | 812 UVD_CGC_GATE__JPEG_MASK | 813 UVD_CGC_GATE__JPEG2_MASK; 814 815 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 816 UVD_SUVD_CGC_GATE__SIT_MASK | 817 UVD_SUVD_CGC_GATE__SMP_MASK | 818 UVD_SUVD_CGC_GATE__SCM_MASK | 819 UVD_SUVD_CGC_GATE__SDB_MASK; 820 821 data |= cgc_flags; 822 data1 |= suvd_flags; 823 824 WREG32(mmUVD_CGC_GATE, data); 825 WREG32(mmUVD_SUVD_CGC_GATE, data1); 826 } 827 #endif 828 829 static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable) 830 { 831 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 832 833 if (enable) 834 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 835 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 836 else 837 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 838 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 839 840 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 841 } 842 843 static int uvd_v6_0_set_clockgating_state(void *handle, 844 enum amd_clockgating_state state) 845 { 846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 847 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 848 static int curstate = -1; 849 850 if (adev->asic_type == CHIP_FIJI) 851 uvd_v6_set_bypass_mode(adev, enable); 852 853 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 854 return 0; 855 856 if (curstate == state) 857 return 0; 858 859 curstate = state; 860 if (enable) { 861 /* disable HW gating and enable Sw gating */ 862 uvd_v6_0_set_sw_clock_gating(adev); 863 } else { 864 /* wait for STATUS to clear */ 865 if (uvd_v6_0_wait_for_idle(handle)) 866 return -EBUSY; 867 868 /* enable HW gates because UVD is idle */ 869 /* uvd_v6_0_set_hw_clock_gating(adev); */ 870 } 871 872 return 0; 873 } 874 875 static int uvd_v6_0_set_powergating_state(void *handle, 876 enum amd_powergating_state state) 877 { 878 /* This doesn't actually powergate the UVD block. 879 * That's done in the dpm code via the SMC. This 880 * just re-inits the block as necessary. The actual 881 * gating still happens in the dpm code. We should 882 * revisit this when there is a cleaner line between 883 * the smc and the hw blocks 884 */ 885 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 886 887 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 888 return 0; 889 890 if (state == AMD_PG_STATE_GATE) { 891 uvd_v6_0_stop(adev); 892 return 0; 893 } else { 894 return uvd_v6_0_start(adev); 895 } 896 } 897 898 const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 899 .name = "uvd_v6_0", 900 .early_init = uvd_v6_0_early_init, 901 .late_init = NULL, 902 .sw_init = uvd_v6_0_sw_init, 903 .sw_fini = uvd_v6_0_sw_fini, 904 .hw_init = uvd_v6_0_hw_init, 905 .hw_fini = uvd_v6_0_hw_fini, 906 .suspend = uvd_v6_0_suspend, 907 .resume = uvd_v6_0_resume, 908 .is_idle = uvd_v6_0_is_idle, 909 .wait_for_idle = uvd_v6_0_wait_for_idle, 910 .soft_reset = uvd_v6_0_soft_reset, 911 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 912 .set_powergating_state = uvd_v6_0_set_powergating_state, 913 }; 914 915 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { 916 .get_rptr = uvd_v6_0_ring_get_rptr, 917 .get_wptr = uvd_v6_0_ring_get_wptr, 918 .set_wptr = uvd_v6_0_ring_set_wptr, 919 .parse_cs = amdgpu_uvd_ring_parse_cs, 920 .emit_ib = uvd_v6_0_ring_emit_ib, 921 .emit_fence = uvd_v6_0_ring_emit_fence, 922 .test_ring = uvd_v6_0_ring_test_ring, 923 .test_ib = uvd_v6_0_ring_test_ib, 924 .insert_nop = amdgpu_ring_insert_nop, 925 .pad_ib = amdgpu_ring_generic_pad_ib, 926 }; 927 928 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 929 { 930 adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs; 931 } 932 933 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { 934 .set = uvd_v6_0_set_interrupt_state, 935 .process = uvd_v6_0_process_interrupt, 936 }; 937 938 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) 939 { 940 adev->uvd.irq.num_types = 1; 941 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; 942 } 943