1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_uvd.h" 30 #include "vid.h" 31 #include "uvd/uvd_5_0_d.h" 32 #include "uvd/uvd_5_0_sh_mask.h" 33 #include "oss/oss_2_0_d.h" 34 #include "oss/oss_2_0_sh_mask.h" 35 #include "bif/bif_5_0_d.h" 36 #include "vi.h" 37 #include "smu/smu_7_1_2_d.h" 38 #include "smu/smu_7_1_2_sh_mask.h" 39 #include "ivsrcid/ivsrcid_vislands30.h" 40 41 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 42 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 43 static int uvd_v5_0_start(struct amdgpu_device *adev); 44 static void uvd_v5_0_stop(struct amdgpu_device *adev); 45 static int uvd_v5_0_set_clockgating_state(void *handle, 46 enum amd_clockgating_state state); 47 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 48 bool enable); 49 /** 50 * uvd_v5_0_ring_get_rptr - get read pointer 51 * 52 * @ring: amdgpu_ring pointer 53 * 54 * Returns the current hardware read pointer 55 */ 56 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 57 { 58 struct amdgpu_device *adev = ring->adev; 59 60 return RREG32(mmUVD_RBC_RB_RPTR); 61 } 62 63 /** 64 * uvd_v5_0_ring_get_wptr - get write pointer 65 * 66 * @ring: amdgpu_ring pointer 67 * 68 * Returns the current hardware write pointer 69 */ 70 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 71 { 72 struct amdgpu_device *adev = ring->adev; 73 74 return RREG32(mmUVD_RBC_RB_WPTR); 75 } 76 77 /** 78 * uvd_v5_0_ring_set_wptr - set write pointer 79 * 80 * @ring: amdgpu_ring pointer 81 * 82 * Commits the write pointer to the hardware 83 */ 84 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 85 { 86 struct amdgpu_device *adev = ring->adev; 87 88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 89 } 90 91 static int uvd_v5_0_early_init(void *handle) 92 { 93 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 94 adev->uvd.num_uvd_inst = 1; 95 96 uvd_v5_0_set_ring_funcs(adev); 97 uvd_v5_0_set_irq_funcs(adev); 98 99 return 0; 100 } 101 102 static int uvd_v5_0_sw_init(void *handle) 103 { 104 struct amdgpu_ring *ring; 105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 106 int r; 107 108 /* UVD TRAP */ 109 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 110 if (r) 111 return r; 112 113 r = amdgpu_uvd_sw_init(adev); 114 if (r) 115 return r; 116 117 ring = &adev->uvd.inst->ring; 118 sprintf(ring->name, "uvd"); 119 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 120 AMDGPU_RING_PRIO_DEFAULT, NULL); 121 if (r) 122 return r; 123 124 r = amdgpu_uvd_resume(adev); 125 if (r) 126 return r; 127 128 r = amdgpu_uvd_entity_init(adev); 129 130 return r; 131 } 132 133 static int uvd_v5_0_sw_fini(void *handle) 134 { 135 int r; 136 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137 138 r = amdgpu_uvd_suspend(adev); 139 if (r) 140 return r; 141 142 return amdgpu_uvd_sw_fini(adev); 143 } 144 145 /** 146 * uvd_v5_0_hw_init - start and test UVD block 147 * 148 * @handle: handle used to pass amdgpu_device pointer 149 * 150 * Initialize the hardware, boot up the VCPU and do some testing 151 */ 152 static int uvd_v5_0_hw_init(void *handle) 153 { 154 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 155 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 156 uint32_t tmp; 157 int r; 158 159 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 161 uvd_v5_0_enable_mgcg(adev, true); 162 163 r = amdgpu_ring_test_helper(ring); 164 if (r) 165 goto done; 166 167 r = amdgpu_ring_alloc(ring, 10); 168 if (r) { 169 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170 goto done; 171 } 172 173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174 amdgpu_ring_write(ring, tmp); 175 amdgpu_ring_write(ring, 0xFFFFF); 176 177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178 amdgpu_ring_write(ring, tmp); 179 amdgpu_ring_write(ring, 0xFFFFF); 180 181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182 amdgpu_ring_write(ring, tmp); 183 amdgpu_ring_write(ring, 0xFFFFF); 184 185 /* Clear timeout status bits */ 186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187 amdgpu_ring_write(ring, 0x8); 188 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190 amdgpu_ring_write(ring, 3); 191 192 amdgpu_ring_commit(ring); 193 194 done: 195 if (!r) 196 DRM_INFO("UVD initialized successfully.\n"); 197 198 return r; 199 200 } 201 202 /** 203 * uvd_v5_0_hw_fini - stop the hardware block 204 * 205 * @handle: handle used to pass amdgpu_device pointer 206 * 207 * Stop the UVD block, mark ring as not ready any more 208 */ 209 static int uvd_v5_0_hw_fini(void *handle) 210 { 211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212 213 /* 214 * Proper cleanups before halting the HW engine: 215 * - cancel the delayed idle work 216 * - enable powergating 217 * - enable clockgating 218 * - disable dpm 219 * 220 * TODO: to align with the VCN implementation, move the 221 * jobs for clockgating/powergating/dpm setting to 222 * ->set_powergating_state(). 223 */ 224 cancel_delayed_work_sync(&adev->uvd.idle_work); 225 226 if (adev->pm.dpm_enabled) { 227 amdgpu_dpm_enable_uvd(adev, false); 228 } else { 229 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 230 /* shutdown the UVD block */ 231 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 232 AMD_PG_STATE_GATE); 233 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 234 AMD_CG_STATE_GATE); 235 } 236 237 if (RREG32(mmUVD_STATUS) != 0) 238 uvd_v5_0_stop(adev); 239 240 return 0; 241 } 242 243 static int uvd_v5_0_suspend(void *handle) 244 { 245 int r; 246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 247 248 r = uvd_v5_0_hw_fini(adev); 249 if (r) 250 return r; 251 252 return amdgpu_uvd_suspend(adev); 253 } 254 255 static int uvd_v5_0_resume(void *handle) 256 { 257 int r; 258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 259 260 r = amdgpu_uvd_resume(adev); 261 if (r) 262 return r; 263 264 return uvd_v5_0_hw_init(adev); 265 } 266 267 /** 268 * uvd_v5_0_mc_resume - memory controller programming 269 * 270 * @adev: amdgpu_device pointer 271 * 272 * Let the UVD memory controller know it's offsets 273 */ 274 static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 275 { 276 uint64_t offset; 277 uint32_t size; 278 279 /* program memory controller bits 0-27 */ 280 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 281 lower_32_bits(adev->uvd.inst->gpu_addr)); 282 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 283 upper_32_bits(adev->uvd.inst->gpu_addr)); 284 285 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 286 size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 287 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 288 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 289 290 offset += size; 291 size = AMDGPU_UVD_HEAP_SIZE; 292 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 293 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 294 295 offset += size; 296 size = AMDGPU_UVD_STACK_SIZE + 297 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 298 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 299 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 300 301 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 302 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 303 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 304 } 305 306 /** 307 * uvd_v5_0_start - start UVD block 308 * 309 * @adev: amdgpu_device pointer 310 * 311 * Setup and start the UVD block 312 */ 313 static int uvd_v5_0_start(struct amdgpu_device *adev) 314 { 315 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 316 uint32_t rb_bufsz, tmp; 317 uint32_t lmi_swap_cntl; 318 uint32_t mp_swap_cntl; 319 int i, j, r; 320 321 /*disable DPG */ 322 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 323 324 /* disable byte swapping */ 325 lmi_swap_cntl = 0; 326 mp_swap_cntl = 0; 327 328 uvd_v5_0_mc_resume(adev); 329 330 /* disable interupt */ 331 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 332 333 /* stall UMC and register bus before resetting VCPU */ 334 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 335 mdelay(1); 336 337 /* put LMI, VCPU, RBC etc... into reset */ 338 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 339 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 340 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 341 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 342 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 343 mdelay(5); 344 345 /* take UVD block out of reset */ 346 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 347 mdelay(5); 348 349 /* initialize UVD memory controller */ 350 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 351 (1 << 21) | (1 << 9) | (1 << 20)); 352 353 #ifdef __BIG_ENDIAN 354 /* swap (8 in 32) RB and IB */ 355 lmi_swap_cntl = 0xa; 356 mp_swap_cntl = 0; 357 #endif 358 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 359 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 360 361 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 362 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 363 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 364 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 365 WREG32(mmUVD_MPC_SET_ALU, 0); 366 WREG32(mmUVD_MPC_SET_MUX, 0x88); 367 368 /* take all subblocks out of reset, except VCPU */ 369 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 370 mdelay(5); 371 372 /* enable VCPU clock */ 373 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 374 375 /* enable UMC */ 376 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 377 378 /* boot up the VCPU */ 379 WREG32(mmUVD_SOFT_RESET, 0); 380 mdelay(10); 381 382 for (i = 0; i < 10; ++i) { 383 uint32_t status; 384 for (j = 0; j < 100; ++j) { 385 status = RREG32(mmUVD_STATUS); 386 if (status & 2) 387 break; 388 mdelay(10); 389 } 390 r = 0; 391 if (status & 2) 392 break; 393 394 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 396 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 397 mdelay(10); 398 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 399 mdelay(10); 400 r = -1; 401 } 402 403 if (r) { 404 DRM_ERROR("UVD not responding, giving up!!!\n"); 405 return r; 406 } 407 /* enable master interrupt */ 408 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 409 410 /* clear the bit 4 of UVD_STATUS */ 411 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 412 413 rb_bufsz = order_base_2(ring->ring_size); 414 tmp = 0; 415 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 416 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 417 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 418 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 419 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 420 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 421 /* force RBC into idle state */ 422 WREG32(mmUVD_RBC_RB_CNTL, tmp); 423 424 /* set the write pointer delay */ 425 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 426 427 /* set the wb address */ 428 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 429 430 /* program the RB_BASE for ring buffer */ 431 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 432 lower_32_bits(ring->gpu_addr)); 433 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 434 upper_32_bits(ring->gpu_addr)); 435 436 /* Initialize the ring buffer's read and write pointers */ 437 WREG32(mmUVD_RBC_RB_RPTR, 0); 438 439 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 440 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 441 442 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 443 444 return 0; 445 } 446 447 /** 448 * uvd_v5_0_stop - stop UVD block 449 * 450 * @adev: amdgpu_device pointer 451 * 452 * stop the UVD block 453 */ 454 static void uvd_v5_0_stop(struct amdgpu_device *adev) 455 { 456 /* force RBC into idle state */ 457 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 458 459 /* Stall UMC and register bus before resetting VCPU */ 460 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 461 mdelay(1); 462 463 /* put VCPU into reset */ 464 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 465 mdelay(5); 466 467 /* disable VCPU clock */ 468 WREG32(mmUVD_VCPU_CNTL, 0x0); 469 470 /* Unstall UMC and register bus */ 471 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 472 473 WREG32(mmUVD_STATUS, 0); 474 } 475 476 /** 477 * uvd_v5_0_ring_emit_fence - emit an fence & trap command 478 * 479 * @ring: amdgpu_ring pointer 480 * @addr: address 481 * @seq: sequence number 482 * @flags: fence related flags 483 * 484 * Write a fence and a trap command to the ring. 485 */ 486 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 487 unsigned flags) 488 { 489 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 490 491 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 492 amdgpu_ring_write(ring, seq); 493 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 494 amdgpu_ring_write(ring, addr & 0xffffffff); 495 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 496 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 497 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 498 amdgpu_ring_write(ring, 0); 499 500 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 501 amdgpu_ring_write(ring, 0); 502 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 503 amdgpu_ring_write(ring, 0); 504 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 505 amdgpu_ring_write(ring, 2); 506 } 507 508 /** 509 * uvd_v5_0_ring_test_ring - register write test 510 * 511 * @ring: amdgpu_ring pointer 512 * 513 * Test if we can successfully write to the context register 514 */ 515 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 516 { 517 struct amdgpu_device *adev = ring->adev; 518 uint32_t tmp = 0; 519 unsigned i; 520 int r; 521 522 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 523 r = amdgpu_ring_alloc(ring, 3); 524 if (r) 525 return r; 526 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 527 amdgpu_ring_write(ring, 0xDEADBEEF); 528 amdgpu_ring_commit(ring); 529 for (i = 0; i < adev->usec_timeout; i++) { 530 tmp = RREG32(mmUVD_CONTEXT_ID); 531 if (tmp == 0xDEADBEEF) 532 break; 533 udelay(1); 534 } 535 536 if (i >= adev->usec_timeout) 537 r = -ETIMEDOUT; 538 539 return r; 540 } 541 542 /** 543 * uvd_v5_0_ring_emit_ib - execute indirect buffer 544 * 545 * @ring: amdgpu_ring pointer 546 * @job: job to retrieve vmid from 547 * @ib: indirect buffer to execute 548 * @flags: unused 549 * 550 * Write ring commands to execute the indirect buffer 551 */ 552 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 553 struct amdgpu_job *job, 554 struct amdgpu_ib *ib, 555 uint32_t flags) 556 { 557 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 558 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 559 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 560 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 561 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 562 amdgpu_ring_write(ring, ib->length_dw); 563 } 564 565 static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 566 { 567 int i; 568 569 WARN_ON(ring->wptr % 2 || count % 2); 570 571 for (i = 0; i < count / 2; i++) { 572 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 573 amdgpu_ring_write(ring, 0); 574 } 575 } 576 577 static bool uvd_v5_0_is_idle(void *handle) 578 { 579 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 580 581 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 582 } 583 584 static int uvd_v5_0_wait_for_idle(void *handle) 585 { 586 unsigned i; 587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 588 589 for (i = 0; i < adev->usec_timeout; i++) { 590 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 591 return 0; 592 } 593 return -ETIMEDOUT; 594 } 595 596 static int uvd_v5_0_soft_reset(void *handle) 597 { 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 600 uvd_v5_0_stop(adev); 601 602 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 603 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 604 mdelay(5); 605 606 return uvd_v5_0_start(adev); 607 } 608 609 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 610 struct amdgpu_irq_src *source, 611 unsigned type, 612 enum amdgpu_interrupt_state state) 613 { 614 // TODO 615 return 0; 616 } 617 618 static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 619 struct amdgpu_irq_src *source, 620 struct amdgpu_iv_entry *entry) 621 { 622 DRM_DEBUG("IH: UVD TRAP\n"); 623 amdgpu_fence_process(&adev->uvd.inst->ring); 624 return 0; 625 } 626 627 static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 628 { 629 uint32_t data1, data3, suvd_flags; 630 631 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 632 data3 = RREG32(mmUVD_CGC_GATE); 633 634 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 635 UVD_SUVD_CGC_GATE__SIT_MASK | 636 UVD_SUVD_CGC_GATE__SMP_MASK | 637 UVD_SUVD_CGC_GATE__SCM_MASK | 638 UVD_SUVD_CGC_GATE__SDB_MASK; 639 640 if (enable) { 641 data3 |= (UVD_CGC_GATE__SYS_MASK | 642 UVD_CGC_GATE__UDEC_MASK | 643 UVD_CGC_GATE__MPEG2_MASK | 644 UVD_CGC_GATE__RBC_MASK | 645 UVD_CGC_GATE__LMI_MC_MASK | 646 UVD_CGC_GATE__IDCT_MASK | 647 UVD_CGC_GATE__MPRD_MASK | 648 UVD_CGC_GATE__MPC_MASK | 649 UVD_CGC_GATE__LBSI_MASK | 650 UVD_CGC_GATE__LRBBM_MASK | 651 UVD_CGC_GATE__UDEC_RE_MASK | 652 UVD_CGC_GATE__UDEC_CM_MASK | 653 UVD_CGC_GATE__UDEC_IT_MASK | 654 UVD_CGC_GATE__UDEC_DB_MASK | 655 UVD_CGC_GATE__UDEC_MP_MASK | 656 UVD_CGC_GATE__WCB_MASK | 657 UVD_CGC_GATE__JPEG_MASK | 658 UVD_CGC_GATE__SCPU_MASK); 659 /* only in pg enabled, we can gate clock to vcpu*/ 660 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 661 data3 |= UVD_CGC_GATE__VCPU_MASK; 662 data3 &= ~UVD_CGC_GATE__REGS_MASK; 663 data1 |= suvd_flags; 664 } else { 665 data3 = 0; 666 data1 = 0; 667 } 668 669 WREG32(mmUVD_SUVD_CGC_GATE, data1); 670 WREG32(mmUVD_CGC_GATE, data3); 671 } 672 673 static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 674 { 675 uint32_t data, data2; 676 677 data = RREG32(mmUVD_CGC_CTRL); 678 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 679 680 681 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 682 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 683 684 685 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 686 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 687 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 688 689 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 690 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 691 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 692 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 693 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 694 UVD_CGC_CTRL__SYS_MODE_MASK | 695 UVD_CGC_CTRL__UDEC_MODE_MASK | 696 UVD_CGC_CTRL__MPEG2_MODE_MASK | 697 UVD_CGC_CTRL__REGS_MODE_MASK | 698 UVD_CGC_CTRL__RBC_MODE_MASK | 699 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 700 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 701 UVD_CGC_CTRL__IDCT_MODE_MASK | 702 UVD_CGC_CTRL__MPRD_MODE_MASK | 703 UVD_CGC_CTRL__MPC_MODE_MASK | 704 UVD_CGC_CTRL__LBSI_MODE_MASK | 705 UVD_CGC_CTRL__LRBBM_MODE_MASK | 706 UVD_CGC_CTRL__WCB_MODE_MASK | 707 UVD_CGC_CTRL__VCPU_MODE_MASK | 708 UVD_CGC_CTRL__JPEG_MODE_MASK | 709 UVD_CGC_CTRL__SCPU_MODE_MASK); 710 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 711 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 712 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 713 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 714 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 715 716 WREG32(mmUVD_CGC_CTRL, data); 717 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 718 } 719 720 #if 0 721 static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 722 { 723 uint32_t data, data1, cgc_flags, suvd_flags; 724 725 data = RREG32(mmUVD_CGC_GATE); 726 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 727 728 cgc_flags = UVD_CGC_GATE__SYS_MASK | 729 UVD_CGC_GATE__UDEC_MASK | 730 UVD_CGC_GATE__MPEG2_MASK | 731 UVD_CGC_GATE__RBC_MASK | 732 UVD_CGC_GATE__LMI_MC_MASK | 733 UVD_CGC_GATE__IDCT_MASK | 734 UVD_CGC_GATE__MPRD_MASK | 735 UVD_CGC_GATE__MPC_MASK | 736 UVD_CGC_GATE__LBSI_MASK | 737 UVD_CGC_GATE__LRBBM_MASK | 738 UVD_CGC_GATE__UDEC_RE_MASK | 739 UVD_CGC_GATE__UDEC_CM_MASK | 740 UVD_CGC_GATE__UDEC_IT_MASK | 741 UVD_CGC_GATE__UDEC_DB_MASK | 742 UVD_CGC_GATE__UDEC_MP_MASK | 743 UVD_CGC_GATE__WCB_MASK | 744 UVD_CGC_GATE__VCPU_MASK | 745 UVD_CGC_GATE__SCPU_MASK; 746 747 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 748 UVD_SUVD_CGC_GATE__SIT_MASK | 749 UVD_SUVD_CGC_GATE__SMP_MASK | 750 UVD_SUVD_CGC_GATE__SCM_MASK | 751 UVD_SUVD_CGC_GATE__SDB_MASK; 752 753 data |= cgc_flags; 754 data1 |= suvd_flags; 755 756 WREG32(mmUVD_CGC_GATE, data); 757 WREG32(mmUVD_SUVD_CGC_GATE, data1); 758 } 759 #endif 760 761 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 762 bool enable) 763 { 764 u32 orig, data; 765 766 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 767 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 768 data |= 0xfff; 769 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 770 771 orig = data = RREG32(mmUVD_CGC_CTRL); 772 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 773 if (orig != data) 774 WREG32(mmUVD_CGC_CTRL, data); 775 } else { 776 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 777 data &= ~0xfff; 778 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 779 780 orig = data = RREG32(mmUVD_CGC_CTRL); 781 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 782 if (orig != data) 783 WREG32(mmUVD_CGC_CTRL, data); 784 } 785 } 786 787 static int uvd_v5_0_set_clockgating_state(void *handle, 788 enum amd_clockgating_state state) 789 { 790 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 791 bool enable = (state == AMD_CG_STATE_GATE); 792 793 if (enable) { 794 /* wait for STATUS to clear */ 795 if (uvd_v5_0_wait_for_idle(handle)) 796 return -EBUSY; 797 uvd_v5_0_enable_clock_gating(adev, true); 798 799 /* enable HW gates because UVD is idle */ 800 /* uvd_v5_0_set_hw_clock_gating(adev); */ 801 } else { 802 uvd_v5_0_enable_clock_gating(adev, false); 803 } 804 805 uvd_v5_0_set_sw_clock_gating(adev); 806 return 0; 807 } 808 809 static int uvd_v5_0_set_powergating_state(void *handle, 810 enum amd_powergating_state state) 811 { 812 /* This doesn't actually powergate the UVD block. 813 * That's done in the dpm code via the SMC. This 814 * just re-inits the block as necessary. The actual 815 * gating still happens in the dpm code. We should 816 * revisit this when there is a cleaner line between 817 * the smc and the hw blocks 818 */ 819 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 820 int ret = 0; 821 822 if (state == AMD_PG_STATE_GATE) { 823 uvd_v5_0_stop(adev); 824 } else { 825 ret = uvd_v5_0_start(adev); 826 if (ret) 827 goto out; 828 } 829 830 out: 831 return ret; 832 } 833 834 static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 835 { 836 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 837 int data; 838 839 mutex_lock(&adev->pm.mutex); 840 841 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 842 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 843 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 844 goto out; 845 } 846 847 /* AMD_CG_SUPPORT_UVD_MGCG */ 848 data = RREG32(mmUVD_CGC_CTRL); 849 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 850 *flags |= AMD_CG_SUPPORT_UVD_MGCG; 851 852 out: 853 mutex_unlock(&adev->pm.mutex); 854 } 855 856 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 857 .name = "uvd_v5_0", 858 .early_init = uvd_v5_0_early_init, 859 .late_init = NULL, 860 .sw_init = uvd_v5_0_sw_init, 861 .sw_fini = uvd_v5_0_sw_fini, 862 .hw_init = uvd_v5_0_hw_init, 863 .hw_fini = uvd_v5_0_hw_fini, 864 .suspend = uvd_v5_0_suspend, 865 .resume = uvd_v5_0_resume, 866 .is_idle = uvd_v5_0_is_idle, 867 .wait_for_idle = uvd_v5_0_wait_for_idle, 868 .soft_reset = uvd_v5_0_soft_reset, 869 .set_clockgating_state = uvd_v5_0_set_clockgating_state, 870 .set_powergating_state = uvd_v5_0_set_powergating_state, 871 .get_clockgating_state = uvd_v5_0_get_clockgating_state, 872 }; 873 874 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 875 .type = AMDGPU_RING_TYPE_UVD, 876 .align_mask = 0xf, 877 .support_64bit_ptrs = false, 878 .no_user_fence = true, 879 .get_rptr = uvd_v5_0_ring_get_rptr, 880 .get_wptr = uvd_v5_0_ring_get_wptr, 881 .set_wptr = uvd_v5_0_ring_set_wptr, 882 .parse_cs = amdgpu_uvd_ring_parse_cs, 883 .emit_frame_size = 884 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 885 .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 886 .emit_ib = uvd_v5_0_ring_emit_ib, 887 .emit_fence = uvd_v5_0_ring_emit_fence, 888 .test_ring = uvd_v5_0_ring_test_ring, 889 .test_ib = amdgpu_uvd_ring_test_ib, 890 .insert_nop = uvd_v5_0_ring_insert_nop, 891 .pad_ib = amdgpu_ring_generic_pad_ib, 892 .begin_use = amdgpu_uvd_ring_begin_use, 893 .end_use = amdgpu_uvd_ring_end_use, 894 }; 895 896 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 897 { 898 adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 899 } 900 901 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 902 .set = uvd_v5_0_set_interrupt_state, 903 .process = uvd_v5_0_process_interrupt, 904 }; 905 906 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 907 { 908 adev->uvd.inst->irq.num_types = 1; 909 adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 910 } 911 912 const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 913 { 914 .type = AMD_IP_BLOCK_TYPE_UVD, 915 .major = 5, 916 .minor = 0, 917 .rev = 0, 918 .funcs = &uvd_v5_0_ip_funcs, 919 }; 920