1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_5_0_d.h" 31 #include "uvd/uvd_5_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 #include "bif/bif_5_0_d.h" 35 #include "vi.h" 36 #include "smu/smu_7_1_2_d.h" 37 #include "smu/smu_7_1_2_sh_mask.h" 38 #include "ivsrcid/ivsrcid_vislands30.h" 39 40 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 41 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 42 static int uvd_v5_0_start(struct amdgpu_device *adev); 43 static void uvd_v5_0_stop(struct amdgpu_device *adev); 44 static int uvd_v5_0_set_clockgating_state(void *handle, 45 enum amd_clockgating_state state); 46 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 47 bool enable); 48 /** 49 * uvd_v5_0_ring_get_rptr - get read pointer 50 * 51 * @ring: amdgpu_ring pointer 52 * 53 * Returns the current hardware read pointer 54 */ 55 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 56 { 57 struct amdgpu_device *adev = ring->adev; 58 59 return RREG32(mmUVD_RBC_RB_RPTR); 60 } 61 62 /** 63 * uvd_v5_0_ring_get_wptr - get write pointer 64 * 65 * @ring: amdgpu_ring pointer 66 * 67 * Returns the current hardware write pointer 68 */ 69 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 70 { 71 struct amdgpu_device *adev = ring->adev; 72 73 return RREG32(mmUVD_RBC_RB_WPTR); 74 } 75 76 /** 77 * uvd_v5_0_ring_set_wptr - set write pointer 78 * 79 * @ring: amdgpu_ring pointer 80 * 81 * Commits the write pointer to the hardware 82 */ 83 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 84 { 85 struct amdgpu_device *adev = ring->adev; 86 87 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 88 } 89 90 static int uvd_v5_0_early_init(void *handle) 91 { 92 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 93 adev->uvd.num_uvd_inst = 1; 94 95 uvd_v5_0_set_ring_funcs(adev); 96 uvd_v5_0_set_irq_funcs(adev); 97 98 return 0; 99 } 100 101 static int uvd_v5_0_sw_init(void *handle) 102 { 103 struct amdgpu_ring *ring; 104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 105 int r; 106 107 /* UVD TRAP */ 108 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 109 if (r) 110 return r; 111 112 r = amdgpu_uvd_sw_init(adev); 113 if (r) 114 return r; 115 116 r = amdgpu_uvd_resume(adev); 117 if (r) 118 return r; 119 120 ring = &adev->uvd.inst->ring; 121 sprintf(ring->name, "uvd"); 122 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 123 124 return r; 125 } 126 127 static int uvd_v5_0_sw_fini(void *handle) 128 { 129 int r; 130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 131 132 r = amdgpu_uvd_suspend(adev); 133 if (r) 134 return r; 135 136 return amdgpu_uvd_sw_fini(adev); 137 } 138 139 /** 140 * uvd_v5_0_hw_init - start and test UVD block 141 * 142 * @adev: amdgpu_device pointer 143 * 144 * Initialize the hardware, boot up the VCPU and do some testing 145 */ 146 static int uvd_v5_0_hw_init(void *handle) 147 { 148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 149 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 150 uint32_t tmp; 151 int r; 152 153 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 154 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 155 uvd_v5_0_enable_mgcg(adev, true); 156 157 ring->ready = true; 158 r = amdgpu_ring_test_ring(ring); 159 if (r) { 160 ring->ready = false; 161 goto done; 162 } 163 164 r = amdgpu_ring_alloc(ring, 10); 165 if (r) { 166 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 167 goto done; 168 } 169 170 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 171 amdgpu_ring_write(ring, tmp); 172 amdgpu_ring_write(ring, 0xFFFFF); 173 174 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 175 amdgpu_ring_write(ring, tmp); 176 amdgpu_ring_write(ring, 0xFFFFF); 177 178 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 179 amdgpu_ring_write(ring, tmp); 180 amdgpu_ring_write(ring, 0xFFFFF); 181 182 /* Clear timeout status bits */ 183 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 184 amdgpu_ring_write(ring, 0x8); 185 186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 187 amdgpu_ring_write(ring, 3); 188 189 amdgpu_ring_commit(ring); 190 191 done: 192 if (!r) 193 DRM_INFO("UVD initialized successfully.\n"); 194 195 return r; 196 197 } 198 199 /** 200 * uvd_v5_0_hw_fini - stop the hardware block 201 * 202 * @adev: amdgpu_device pointer 203 * 204 * Stop the UVD block, mark ring as not ready any more 205 */ 206 static int uvd_v5_0_hw_fini(void *handle) 207 { 208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 209 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 210 211 if (RREG32(mmUVD_STATUS) != 0) 212 uvd_v5_0_stop(adev); 213 214 ring->ready = false; 215 216 return 0; 217 } 218 219 static int uvd_v5_0_suspend(void *handle) 220 { 221 int r; 222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 223 224 r = uvd_v5_0_hw_fini(adev); 225 if (r) 226 return r; 227 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 228 229 return amdgpu_uvd_suspend(adev); 230 } 231 232 static int uvd_v5_0_resume(void *handle) 233 { 234 int r; 235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 236 237 r = amdgpu_uvd_resume(adev); 238 if (r) 239 return r; 240 241 return uvd_v5_0_hw_init(adev); 242 } 243 244 /** 245 * uvd_v5_0_mc_resume - memory controller programming 246 * 247 * @adev: amdgpu_device pointer 248 * 249 * Let the UVD memory controller know it's offsets 250 */ 251 static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 252 { 253 uint64_t offset; 254 uint32_t size; 255 256 /* programm memory controller bits 0-27 */ 257 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 258 lower_32_bits(adev->uvd.inst->gpu_addr)); 259 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 260 upper_32_bits(adev->uvd.inst->gpu_addr)); 261 262 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 263 size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 264 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 265 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 266 267 offset += size; 268 size = AMDGPU_UVD_HEAP_SIZE; 269 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 270 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 271 272 offset += size; 273 size = AMDGPU_UVD_STACK_SIZE + 274 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 275 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 276 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 277 278 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 279 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 280 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 281 } 282 283 /** 284 * uvd_v5_0_start - start UVD block 285 * 286 * @adev: amdgpu_device pointer 287 * 288 * Setup and start the UVD block 289 */ 290 static int uvd_v5_0_start(struct amdgpu_device *adev) 291 { 292 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 293 uint32_t rb_bufsz, tmp; 294 uint32_t lmi_swap_cntl; 295 uint32_t mp_swap_cntl; 296 int i, j, r; 297 298 /*disable DPG */ 299 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 300 301 /* disable byte swapping */ 302 lmi_swap_cntl = 0; 303 mp_swap_cntl = 0; 304 305 uvd_v5_0_mc_resume(adev); 306 307 /* disable interupt */ 308 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 309 310 /* stall UMC and register bus before resetting VCPU */ 311 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 312 mdelay(1); 313 314 /* put LMI, VCPU, RBC etc... into reset */ 315 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 316 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 317 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 318 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 319 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 320 mdelay(5); 321 322 /* take UVD block out of reset */ 323 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 324 mdelay(5); 325 326 /* initialize UVD memory controller */ 327 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 328 (1 << 21) | (1 << 9) | (1 << 20)); 329 330 #ifdef __BIG_ENDIAN 331 /* swap (8 in 32) RB and IB */ 332 lmi_swap_cntl = 0xa; 333 mp_swap_cntl = 0; 334 #endif 335 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 336 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 337 338 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 339 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 340 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 341 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 342 WREG32(mmUVD_MPC_SET_ALU, 0); 343 WREG32(mmUVD_MPC_SET_MUX, 0x88); 344 345 /* take all subblocks out of reset, except VCPU */ 346 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 347 mdelay(5); 348 349 /* enable VCPU clock */ 350 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 351 352 /* enable UMC */ 353 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 354 355 /* boot up the VCPU */ 356 WREG32(mmUVD_SOFT_RESET, 0); 357 mdelay(10); 358 359 for (i = 0; i < 10; ++i) { 360 uint32_t status; 361 for (j = 0; j < 100; ++j) { 362 status = RREG32(mmUVD_STATUS); 363 if (status & 2) 364 break; 365 mdelay(10); 366 } 367 r = 0; 368 if (status & 2) 369 break; 370 371 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 372 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 373 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 374 mdelay(10); 375 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 376 mdelay(10); 377 r = -1; 378 } 379 380 if (r) { 381 DRM_ERROR("UVD not responding, giving up!!!\n"); 382 return r; 383 } 384 /* enable master interrupt */ 385 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 386 387 /* clear the bit 4 of UVD_STATUS */ 388 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 389 390 rb_bufsz = order_base_2(ring->ring_size); 391 tmp = 0; 392 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 393 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 394 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 395 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 397 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 398 /* force RBC into idle state */ 399 WREG32(mmUVD_RBC_RB_CNTL, tmp); 400 401 /* set the write pointer delay */ 402 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 403 404 /* set the wb address */ 405 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 406 407 /* programm the RB_BASE for ring buffer */ 408 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 409 lower_32_bits(ring->gpu_addr)); 410 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 411 upper_32_bits(ring->gpu_addr)); 412 413 /* Initialize the ring buffer's read and write pointers */ 414 WREG32(mmUVD_RBC_RB_RPTR, 0); 415 416 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 417 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 418 419 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 420 421 return 0; 422 } 423 424 /** 425 * uvd_v5_0_stop - stop UVD block 426 * 427 * @adev: amdgpu_device pointer 428 * 429 * stop the UVD block 430 */ 431 static void uvd_v5_0_stop(struct amdgpu_device *adev) 432 { 433 /* force RBC into idle state */ 434 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 435 436 /* Stall UMC and register bus before resetting VCPU */ 437 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 438 mdelay(1); 439 440 /* put VCPU into reset */ 441 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 442 mdelay(5); 443 444 /* disable VCPU clock */ 445 WREG32(mmUVD_VCPU_CNTL, 0x0); 446 447 /* Unstall UMC and register bus */ 448 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 449 450 WREG32(mmUVD_STATUS, 0); 451 } 452 453 /** 454 * uvd_v5_0_ring_emit_fence - emit an fence & trap command 455 * 456 * @ring: amdgpu_ring pointer 457 * @fence: fence to emit 458 * 459 * Write a fence and a trap command to the ring. 460 */ 461 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 462 unsigned flags) 463 { 464 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 465 466 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 467 amdgpu_ring_write(ring, seq); 468 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 469 amdgpu_ring_write(ring, addr & 0xffffffff); 470 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 471 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 472 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 473 amdgpu_ring_write(ring, 0); 474 475 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 476 amdgpu_ring_write(ring, 0); 477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 478 amdgpu_ring_write(ring, 0); 479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 480 amdgpu_ring_write(ring, 2); 481 } 482 483 /** 484 * uvd_v5_0_ring_test_ring - register write test 485 * 486 * @ring: amdgpu_ring pointer 487 * 488 * Test if we can successfully write to the context register 489 */ 490 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 491 { 492 struct amdgpu_device *adev = ring->adev; 493 uint32_t tmp = 0; 494 unsigned i; 495 int r; 496 497 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 498 r = amdgpu_ring_alloc(ring, 3); 499 if (r) { 500 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 501 ring->idx, r); 502 return r; 503 } 504 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 505 amdgpu_ring_write(ring, 0xDEADBEEF); 506 amdgpu_ring_commit(ring); 507 for (i = 0; i < adev->usec_timeout; i++) { 508 tmp = RREG32(mmUVD_CONTEXT_ID); 509 if (tmp == 0xDEADBEEF) 510 break; 511 DRM_UDELAY(1); 512 } 513 514 if (i < adev->usec_timeout) { 515 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 516 ring->idx, i); 517 } else { 518 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 519 ring->idx, tmp); 520 r = -EINVAL; 521 } 522 return r; 523 } 524 525 /** 526 * uvd_v5_0_ring_emit_ib - execute indirect buffer 527 * 528 * @ring: amdgpu_ring pointer 529 * @ib: indirect buffer to execute 530 * 531 * Write ring commands to execute the indirect buffer 532 */ 533 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 534 struct amdgpu_ib *ib, 535 unsigned vmid, bool ctx_switch) 536 { 537 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 538 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 539 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 540 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 541 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 542 amdgpu_ring_write(ring, ib->length_dw); 543 } 544 545 static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 546 { 547 int i; 548 549 WARN_ON(ring->wptr % 2 || count % 2); 550 551 for (i = 0; i < count / 2; i++) { 552 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 553 amdgpu_ring_write(ring, 0); 554 } 555 } 556 557 static bool uvd_v5_0_is_idle(void *handle) 558 { 559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 560 561 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 562 } 563 564 static int uvd_v5_0_wait_for_idle(void *handle) 565 { 566 unsigned i; 567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 568 569 for (i = 0; i < adev->usec_timeout; i++) { 570 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 571 return 0; 572 } 573 return -ETIMEDOUT; 574 } 575 576 static int uvd_v5_0_soft_reset(void *handle) 577 { 578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 579 580 uvd_v5_0_stop(adev); 581 582 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 583 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 584 mdelay(5); 585 586 return uvd_v5_0_start(adev); 587 } 588 589 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 590 struct amdgpu_irq_src *source, 591 unsigned type, 592 enum amdgpu_interrupt_state state) 593 { 594 // TODO 595 return 0; 596 } 597 598 static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 599 struct amdgpu_irq_src *source, 600 struct amdgpu_iv_entry *entry) 601 { 602 DRM_DEBUG("IH: UVD TRAP\n"); 603 amdgpu_fence_process(&adev->uvd.inst->ring); 604 return 0; 605 } 606 607 static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 608 { 609 uint32_t data1, data3, suvd_flags; 610 611 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 612 data3 = RREG32(mmUVD_CGC_GATE); 613 614 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 615 UVD_SUVD_CGC_GATE__SIT_MASK | 616 UVD_SUVD_CGC_GATE__SMP_MASK | 617 UVD_SUVD_CGC_GATE__SCM_MASK | 618 UVD_SUVD_CGC_GATE__SDB_MASK; 619 620 if (enable) { 621 data3 |= (UVD_CGC_GATE__SYS_MASK | 622 UVD_CGC_GATE__UDEC_MASK | 623 UVD_CGC_GATE__MPEG2_MASK | 624 UVD_CGC_GATE__RBC_MASK | 625 UVD_CGC_GATE__LMI_MC_MASK | 626 UVD_CGC_GATE__IDCT_MASK | 627 UVD_CGC_GATE__MPRD_MASK | 628 UVD_CGC_GATE__MPC_MASK | 629 UVD_CGC_GATE__LBSI_MASK | 630 UVD_CGC_GATE__LRBBM_MASK | 631 UVD_CGC_GATE__UDEC_RE_MASK | 632 UVD_CGC_GATE__UDEC_CM_MASK | 633 UVD_CGC_GATE__UDEC_IT_MASK | 634 UVD_CGC_GATE__UDEC_DB_MASK | 635 UVD_CGC_GATE__UDEC_MP_MASK | 636 UVD_CGC_GATE__WCB_MASK | 637 UVD_CGC_GATE__JPEG_MASK | 638 UVD_CGC_GATE__SCPU_MASK); 639 /* only in pg enabled, we can gate clock to vcpu*/ 640 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 641 data3 |= UVD_CGC_GATE__VCPU_MASK; 642 data3 &= ~UVD_CGC_GATE__REGS_MASK; 643 data1 |= suvd_flags; 644 } else { 645 data3 = 0; 646 data1 = 0; 647 } 648 649 WREG32(mmUVD_SUVD_CGC_GATE, data1); 650 WREG32(mmUVD_CGC_GATE, data3); 651 } 652 653 static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 654 { 655 uint32_t data, data2; 656 657 data = RREG32(mmUVD_CGC_CTRL); 658 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 659 660 661 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 662 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 663 664 665 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 666 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 667 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 668 669 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 670 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 671 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 674 UVD_CGC_CTRL__SYS_MODE_MASK | 675 UVD_CGC_CTRL__UDEC_MODE_MASK | 676 UVD_CGC_CTRL__MPEG2_MODE_MASK | 677 UVD_CGC_CTRL__REGS_MODE_MASK | 678 UVD_CGC_CTRL__RBC_MODE_MASK | 679 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 680 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 681 UVD_CGC_CTRL__IDCT_MODE_MASK | 682 UVD_CGC_CTRL__MPRD_MODE_MASK | 683 UVD_CGC_CTRL__MPC_MODE_MASK | 684 UVD_CGC_CTRL__LBSI_MODE_MASK | 685 UVD_CGC_CTRL__LRBBM_MODE_MASK | 686 UVD_CGC_CTRL__WCB_MODE_MASK | 687 UVD_CGC_CTRL__VCPU_MODE_MASK | 688 UVD_CGC_CTRL__JPEG_MODE_MASK | 689 UVD_CGC_CTRL__SCPU_MODE_MASK); 690 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 691 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 692 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 693 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 694 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 695 696 WREG32(mmUVD_CGC_CTRL, data); 697 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 698 } 699 700 #if 0 701 static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 702 { 703 uint32_t data, data1, cgc_flags, suvd_flags; 704 705 data = RREG32(mmUVD_CGC_GATE); 706 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 707 708 cgc_flags = UVD_CGC_GATE__SYS_MASK | 709 UVD_CGC_GATE__UDEC_MASK | 710 UVD_CGC_GATE__MPEG2_MASK | 711 UVD_CGC_GATE__RBC_MASK | 712 UVD_CGC_GATE__LMI_MC_MASK | 713 UVD_CGC_GATE__IDCT_MASK | 714 UVD_CGC_GATE__MPRD_MASK | 715 UVD_CGC_GATE__MPC_MASK | 716 UVD_CGC_GATE__LBSI_MASK | 717 UVD_CGC_GATE__LRBBM_MASK | 718 UVD_CGC_GATE__UDEC_RE_MASK | 719 UVD_CGC_GATE__UDEC_CM_MASK | 720 UVD_CGC_GATE__UDEC_IT_MASK | 721 UVD_CGC_GATE__UDEC_DB_MASK | 722 UVD_CGC_GATE__UDEC_MP_MASK | 723 UVD_CGC_GATE__WCB_MASK | 724 UVD_CGC_GATE__VCPU_MASK | 725 UVD_CGC_GATE__SCPU_MASK; 726 727 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 728 UVD_SUVD_CGC_GATE__SIT_MASK | 729 UVD_SUVD_CGC_GATE__SMP_MASK | 730 UVD_SUVD_CGC_GATE__SCM_MASK | 731 UVD_SUVD_CGC_GATE__SDB_MASK; 732 733 data |= cgc_flags; 734 data1 |= suvd_flags; 735 736 WREG32(mmUVD_CGC_GATE, data); 737 WREG32(mmUVD_SUVD_CGC_GATE, data1); 738 } 739 #endif 740 741 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 742 bool enable) 743 { 744 u32 orig, data; 745 746 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 747 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 748 data |= 0xfff; 749 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 750 751 orig = data = RREG32(mmUVD_CGC_CTRL); 752 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 753 if (orig != data) 754 WREG32(mmUVD_CGC_CTRL, data); 755 } else { 756 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 757 data &= ~0xfff; 758 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 759 760 orig = data = RREG32(mmUVD_CGC_CTRL); 761 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 762 if (orig != data) 763 WREG32(mmUVD_CGC_CTRL, data); 764 } 765 } 766 767 static int uvd_v5_0_set_clockgating_state(void *handle, 768 enum amd_clockgating_state state) 769 { 770 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 771 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 772 773 if (enable) { 774 /* wait for STATUS to clear */ 775 if (uvd_v5_0_wait_for_idle(handle)) 776 return -EBUSY; 777 uvd_v5_0_enable_clock_gating(adev, true); 778 779 /* enable HW gates because UVD is idle */ 780 /* uvd_v5_0_set_hw_clock_gating(adev); */ 781 } else { 782 uvd_v5_0_enable_clock_gating(adev, false); 783 } 784 785 uvd_v5_0_set_sw_clock_gating(adev); 786 return 0; 787 } 788 789 static int uvd_v5_0_set_powergating_state(void *handle, 790 enum amd_powergating_state state) 791 { 792 /* This doesn't actually powergate the UVD block. 793 * That's done in the dpm code via the SMC. This 794 * just re-inits the block as necessary. The actual 795 * gating still happens in the dpm code. We should 796 * revisit this when there is a cleaner line between 797 * the smc and the hw blocks 798 */ 799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800 int ret = 0; 801 802 if (state == AMD_PG_STATE_GATE) { 803 uvd_v5_0_stop(adev); 804 } else { 805 ret = uvd_v5_0_start(adev); 806 if (ret) 807 goto out; 808 } 809 810 out: 811 return ret; 812 } 813 814 static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 815 { 816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 817 int data; 818 819 mutex_lock(&adev->pm.mutex); 820 821 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 822 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 823 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 824 goto out; 825 } 826 827 /* AMD_CG_SUPPORT_UVD_MGCG */ 828 data = RREG32(mmUVD_CGC_CTRL); 829 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 830 *flags |= AMD_CG_SUPPORT_UVD_MGCG; 831 832 out: 833 mutex_unlock(&adev->pm.mutex); 834 } 835 836 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 837 .name = "uvd_v5_0", 838 .early_init = uvd_v5_0_early_init, 839 .late_init = NULL, 840 .sw_init = uvd_v5_0_sw_init, 841 .sw_fini = uvd_v5_0_sw_fini, 842 .hw_init = uvd_v5_0_hw_init, 843 .hw_fini = uvd_v5_0_hw_fini, 844 .suspend = uvd_v5_0_suspend, 845 .resume = uvd_v5_0_resume, 846 .is_idle = uvd_v5_0_is_idle, 847 .wait_for_idle = uvd_v5_0_wait_for_idle, 848 .soft_reset = uvd_v5_0_soft_reset, 849 .set_clockgating_state = uvd_v5_0_set_clockgating_state, 850 .set_powergating_state = uvd_v5_0_set_powergating_state, 851 .get_clockgating_state = uvd_v5_0_get_clockgating_state, 852 }; 853 854 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 855 .type = AMDGPU_RING_TYPE_UVD, 856 .align_mask = 0xf, 857 .support_64bit_ptrs = false, 858 .get_rptr = uvd_v5_0_ring_get_rptr, 859 .get_wptr = uvd_v5_0_ring_get_wptr, 860 .set_wptr = uvd_v5_0_ring_set_wptr, 861 .parse_cs = amdgpu_uvd_ring_parse_cs, 862 .emit_frame_size = 863 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 864 .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 865 .emit_ib = uvd_v5_0_ring_emit_ib, 866 .emit_fence = uvd_v5_0_ring_emit_fence, 867 .test_ring = uvd_v5_0_ring_test_ring, 868 .test_ib = amdgpu_uvd_ring_test_ib, 869 .insert_nop = uvd_v5_0_ring_insert_nop, 870 .pad_ib = amdgpu_ring_generic_pad_ib, 871 .begin_use = amdgpu_uvd_ring_begin_use, 872 .end_use = amdgpu_uvd_ring_end_use, 873 }; 874 875 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 876 { 877 adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 878 } 879 880 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 881 .set = uvd_v5_0_set_interrupt_state, 882 .process = uvd_v5_0_process_interrupt, 883 }; 884 885 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 886 { 887 adev->uvd.inst->irq.num_types = 1; 888 adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 889 } 890 891 const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 892 { 893 .type = AMD_IP_BLOCK_TYPE_UVD, 894 .major = 5, 895 .minor = 0, 896 .rev = 0, 897 .funcs = &uvd_v5_0_ip_funcs, 898 }; 899