1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_5_0_d.h" 31 #include "uvd/uvd_5_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 35 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 36 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 37 static int uvd_v5_0_start(struct amdgpu_device *adev); 38 static void uvd_v5_0_stop(struct amdgpu_device *adev); 39 40 /** 41 * uvd_v5_0_ring_get_rptr - get read pointer 42 * 43 * @ring: amdgpu_ring pointer 44 * 45 * Returns the current hardware read pointer 46 */ 47 static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 48 { 49 struct amdgpu_device *adev = ring->adev; 50 51 return RREG32(mmUVD_RBC_RB_RPTR); 52 } 53 54 /** 55 * uvd_v5_0_ring_get_wptr - get write pointer 56 * 57 * @ring: amdgpu_ring pointer 58 * 59 * Returns the current hardware write pointer 60 */ 61 static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 62 { 63 struct amdgpu_device *adev = ring->adev; 64 65 return RREG32(mmUVD_RBC_RB_WPTR); 66 } 67 68 /** 69 * uvd_v5_0_ring_set_wptr - set write pointer 70 * 71 * @ring: amdgpu_ring pointer 72 * 73 * Commits the write pointer to the hardware 74 */ 75 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 76 { 77 struct amdgpu_device *adev = ring->adev; 78 79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 80 } 81 82 static int uvd_v5_0_early_init(void *handle) 83 { 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 86 uvd_v5_0_set_ring_funcs(adev); 87 uvd_v5_0_set_irq_funcs(adev); 88 89 return 0; 90 } 91 92 static int uvd_v5_0_sw_init(void *handle) 93 { 94 struct amdgpu_ring *ring; 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 int r; 97 98 /* UVD TRAP */ 99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 100 if (r) 101 return r; 102 103 r = amdgpu_uvd_sw_init(adev); 104 if (r) 105 return r; 106 107 r = amdgpu_uvd_resume(adev); 108 if (r) 109 return r; 110 111 ring = &adev->uvd.ring; 112 sprintf(ring->name, "uvd"); 113 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 114 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 115 116 return r; 117 } 118 119 static int uvd_v5_0_sw_fini(void *handle) 120 { 121 int r; 122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 123 124 r = amdgpu_uvd_suspend(adev); 125 if (r) 126 return r; 127 128 r = amdgpu_uvd_sw_fini(adev); 129 if (r) 130 return r; 131 132 return r; 133 } 134 135 /** 136 * uvd_v5_0_hw_init - start and test UVD block 137 * 138 * @adev: amdgpu_device pointer 139 * 140 * Initialize the hardware, boot up the VCPU and do some testing 141 */ 142 static int uvd_v5_0_hw_init(void *handle) 143 { 144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 145 struct amdgpu_ring *ring = &adev->uvd.ring; 146 uint32_t tmp; 147 int r; 148 149 /* raise clocks while booting up the VCPU */ 150 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 151 152 r = uvd_v5_0_start(adev); 153 if (r) 154 goto done; 155 156 ring->ready = true; 157 r = amdgpu_ring_test_ring(ring); 158 if (r) { 159 ring->ready = false; 160 goto done; 161 } 162 163 r = amdgpu_ring_alloc(ring, 10); 164 if (r) { 165 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 166 goto done; 167 } 168 169 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 170 amdgpu_ring_write(ring, tmp); 171 amdgpu_ring_write(ring, 0xFFFFF); 172 173 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 174 amdgpu_ring_write(ring, tmp); 175 amdgpu_ring_write(ring, 0xFFFFF); 176 177 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 178 amdgpu_ring_write(ring, tmp); 179 amdgpu_ring_write(ring, 0xFFFFF); 180 181 /* Clear timeout status bits */ 182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 183 amdgpu_ring_write(ring, 0x8); 184 185 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 186 amdgpu_ring_write(ring, 3); 187 188 amdgpu_ring_commit(ring); 189 190 done: 191 /* lower clocks again */ 192 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 193 194 if (!r) 195 DRM_INFO("UVD initialized successfully.\n"); 196 197 return r; 198 } 199 200 /** 201 * uvd_v5_0_hw_fini - stop the hardware block 202 * 203 * @adev: amdgpu_device pointer 204 * 205 * Stop the UVD block, mark ring as not ready any more 206 */ 207 static int uvd_v5_0_hw_fini(void *handle) 208 { 209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 210 struct amdgpu_ring *ring = &adev->uvd.ring; 211 212 uvd_v5_0_stop(adev); 213 ring->ready = false; 214 215 return 0; 216 } 217 218 static int uvd_v5_0_suspend(void *handle) 219 { 220 int r; 221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 222 223 r = amdgpu_uvd_suspend(adev); 224 if (r) 225 return r; 226 227 r = uvd_v5_0_hw_fini(adev); 228 if (r) 229 return r; 230 231 return r; 232 } 233 234 static int uvd_v5_0_resume(void *handle) 235 { 236 int r; 237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238 239 r = amdgpu_uvd_resume(adev); 240 if (r) 241 return r; 242 243 r = uvd_v5_0_hw_init(adev); 244 if (r) 245 return r; 246 247 return r; 248 } 249 250 /** 251 * uvd_v5_0_mc_resume - memory controller programming 252 * 253 * @adev: amdgpu_device pointer 254 * 255 * Let the UVD memory controller know it's offsets 256 */ 257 static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 258 { 259 uint64_t offset; 260 uint32_t size; 261 262 /* programm memory controller bits 0-27 */ 263 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 264 lower_32_bits(adev->uvd.gpu_addr)); 265 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 266 upper_32_bits(adev->uvd.gpu_addr)); 267 268 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 269 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 270 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 271 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 272 273 offset += size; 274 size = AMDGPU_UVD_STACK_SIZE; 275 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 276 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 277 278 offset += size; 279 size = AMDGPU_UVD_HEAP_SIZE; 280 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 281 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 282 } 283 284 /** 285 * uvd_v5_0_start - start UVD block 286 * 287 * @adev: amdgpu_device pointer 288 * 289 * Setup and start the UVD block 290 */ 291 static int uvd_v5_0_start(struct amdgpu_device *adev) 292 { 293 struct amdgpu_ring *ring = &adev->uvd.ring; 294 uint32_t rb_bufsz, tmp; 295 uint32_t lmi_swap_cntl; 296 uint32_t mp_swap_cntl; 297 int i, j, r; 298 299 /*disable DPG */ 300 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 301 302 /* disable byte swapping */ 303 lmi_swap_cntl = 0; 304 mp_swap_cntl = 0; 305 306 uvd_v5_0_mc_resume(adev); 307 308 /* disable clock gating */ 309 WREG32(mmUVD_CGC_GATE, 0); 310 311 /* disable interupt */ 312 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 313 314 /* stall UMC and register bus before resetting VCPU */ 315 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 316 mdelay(1); 317 318 /* put LMI, VCPU, RBC etc... into reset */ 319 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 320 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 321 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 322 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 323 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 324 mdelay(5); 325 326 /* take UVD block out of reset */ 327 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 328 mdelay(5); 329 330 /* initialize UVD memory controller */ 331 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 332 (1 << 21) | (1 << 9) | (1 << 20)); 333 334 #ifdef __BIG_ENDIAN 335 /* swap (8 in 32) RB and IB */ 336 lmi_swap_cntl = 0xa; 337 mp_swap_cntl = 0; 338 #endif 339 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 340 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 341 342 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 343 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 344 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 345 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 346 WREG32(mmUVD_MPC_SET_ALU, 0); 347 WREG32(mmUVD_MPC_SET_MUX, 0x88); 348 349 /* take all subblocks out of reset, except VCPU */ 350 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 351 mdelay(5); 352 353 /* enable VCPU clock */ 354 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 355 356 /* enable UMC */ 357 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 358 359 /* boot up the VCPU */ 360 WREG32(mmUVD_SOFT_RESET, 0); 361 mdelay(10); 362 363 for (i = 0; i < 10; ++i) { 364 uint32_t status; 365 for (j = 0; j < 100; ++j) { 366 status = RREG32(mmUVD_STATUS); 367 if (status & 2) 368 break; 369 mdelay(10); 370 } 371 r = 0; 372 if (status & 2) 373 break; 374 375 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 376 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 377 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 378 mdelay(10); 379 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 380 mdelay(10); 381 r = -1; 382 } 383 384 if (r) { 385 DRM_ERROR("UVD not responding, giving up!!!\n"); 386 return r; 387 } 388 /* enable master interrupt */ 389 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 390 391 /* clear the bit 4 of UVD_STATUS */ 392 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 393 394 rb_bufsz = order_base_2(ring->ring_size); 395 tmp = 0; 396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 397 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 398 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 401 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 402 /* force RBC into idle state */ 403 WREG32(mmUVD_RBC_RB_CNTL, tmp); 404 405 /* set the write pointer delay */ 406 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 407 408 /* set the wb address */ 409 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 410 411 /* programm the RB_BASE for ring buffer */ 412 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 413 lower_32_bits(ring->gpu_addr)); 414 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 415 upper_32_bits(ring->gpu_addr)); 416 417 /* Initialize the ring buffer's read and write pointers */ 418 WREG32(mmUVD_RBC_RB_RPTR, 0); 419 420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 421 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 422 423 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 424 425 return 0; 426 } 427 428 /** 429 * uvd_v5_0_stop - stop UVD block 430 * 431 * @adev: amdgpu_device pointer 432 * 433 * stop the UVD block 434 */ 435 static void uvd_v5_0_stop(struct amdgpu_device *adev) 436 { 437 /* force RBC into idle state */ 438 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 439 440 /* Stall UMC and register bus before resetting VCPU */ 441 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 442 mdelay(1); 443 444 /* put VCPU into reset */ 445 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 446 mdelay(5); 447 448 /* disable VCPU clock */ 449 WREG32(mmUVD_VCPU_CNTL, 0x0); 450 451 /* Unstall UMC and register bus */ 452 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 453 } 454 455 /** 456 * uvd_v5_0_ring_emit_fence - emit an fence & trap command 457 * 458 * @ring: amdgpu_ring pointer 459 * @fence: fence to emit 460 * 461 * Write a fence and a trap command to the ring. 462 */ 463 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 464 unsigned flags) 465 { 466 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 467 468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 469 amdgpu_ring_write(ring, seq); 470 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 471 amdgpu_ring_write(ring, addr & 0xffffffff); 472 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 473 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 474 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 475 amdgpu_ring_write(ring, 0); 476 477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 478 amdgpu_ring_write(ring, 0); 479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 480 amdgpu_ring_write(ring, 0); 481 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 482 amdgpu_ring_write(ring, 2); 483 } 484 485 /** 486 * uvd_v5_0_ring_test_ring - register write test 487 * 488 * @ring: amdgpu_ring pointer 489 * 490 * Test if we can successfully write to the context register 491 */ 492 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 493 { 494 struct amdgpu_device *adev = ring->adev; 495 uint32_t tmp = 0; 496 unsigned i; 497 int r; 498 499 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 500 r = amdgpu_ring_alloc(ring, 3); 501 if (r) { 502 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 503 ring->idx, r); 504 return r; 505 } 506 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 507 amdgpu_ring_write(ring, 0xDEADBEEF); 508 amdgpu_ring_commit(ring); 509 for (i = 0; i < adev->usec_timeout; i++) { 510 tmp = RREG32(mmUVD_CONTEXT_ID); 511 if (tmp == 0xDEADBEEF) 512 break; 513 DRM_UDELAY(1); 514 } 515 516 if (i < adev->usec_timeout) { 517 DRM_INFO("ring test on %d succeeded in %d usecs\n", 518 ring->idx, i); 519 } else { 520 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 521 ring->idx, tmp); 522 r = -EINVAL; 523 } 524 return r; 525 } 526 527 /** 528 * uvd_v5_0_ring_emit_ib - execute indirect buffer 529 * 530 * @ring: amdgpu_ring pointer 531 * @ib: indirect buffer to execute 532 * 533 * Write ring commands to execute the indirect buffer 534 */ 535 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 536 struct amdgpu_ib *ib) 537 { 538 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 539 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 540 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 541 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 542 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 543 amdgpu_ring_write(ring, ib->length_dw); 544 } 545 546 /** 547 * uvd_v5_0_ring_test_ib - test ib execution 548 * 549 * @ring: amdgpu_ring pointer 550 * 551 * Test if we can successfully execute an IB 552 */ 553 static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring) 554 { 555 struct amdgpu_device *adev = ring->adev; 556 struct fence *fence = NULL; 557 int r; 558 559 r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 560 if (r) { 561 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 562 return r; 563 } 564 565 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 566 if (r) { 567 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 568 goto error; 569 } 570 571 r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence); 572 if (r) { 573 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 574 goto error; 575 } 576 577 r = fence_wait(fence, false); 578 if (r) { 579 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 580 goto error; 581 } 582 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 583 error: 584 fence_put(fence); 585 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 586 return r; 587 } 588 589 static bool uvd_v5_0_is_idle(void *handle) 590 { 591 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 592 593 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 594 } 595 596 static int uvd_v5_0_wait_for_idle(void *handle) 597 { 598 unsigned i; 599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 600 601 for (i = 0; i < adev->usec_timeout; i++) { 602 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 603 return 0; 604 } 605 return -ETIMEDOUT; 606 } 607 608 static int uvd_v5_0_soft_reset(void *handle) 609 { 610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 611 612 uvd_v5_0_stop(adev); 613 614 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 615 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 616 mdelay(5); 617 618 return uvd_v5_0_start(adev); 619 } 620 621 static void uvd_v5_0_print_status(void *handle) 622 { 623 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 624 dev_info(adev->dev, "UVD 5.0 registers\n"); 625 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 626 RREG32(mmUVD_SEMA_ADDR_LOW)); 627 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 628 RREG32(mmUVD_SEMA_ADDR_HIGH)); 629 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 630 RREG32(mmUVD_SEMA_CMD)); 631 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 632 RREG32(mmUVD_GPCOM_VCPU_CMD)); 633 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 634 RREG32(mmUVD_GPCOM_VCPU_DATA0)); 635 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 636 RREG32(mmUVD_GPCOM_VCPU_DATA1)); 637 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 638 RREG32(mmUVD_ENGINE_CNTL)); 639 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 640 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 641 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 642 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 643 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 644 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 645 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 646 RREG32(mmUVD_SEMA_CNTL)); 647 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 648 RREG32(mmUVD_LMI_EXT40_ADDR)); 649 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 650 RREG32(mmUVD_CTX_INDEX)); 651 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 652 RREG32(mmUVD_CTX_DATA)); 653 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 654 RREG32(mmUVD_CGC_GATE)); 655 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 656 RREG32(mmUVD_CGC_CTRL)); 657 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 658 RREG32(mmUVD_LMI_CTRL2)); 659 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 660 RREG32(mmUVD_MASTINT_EN)); 661 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 662 RREG32(mmUVD_LMI_ADDR_EXT)); 663 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 664 RREG32(mmUVD_LMI_CTRL)); 665 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 666 RREG32(mmUVD_LMI_SWAP_CNTL)); 667 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 668 RREG32(mmUVD_MP_SWAP_CNTL)); 669 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 670 RREG32(mmUVD_MPC_SET_MUXA0)); 671 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 672 RREG32(mmUVD_MPC_SET_MUXA1)); 673 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 674 RREG32(mmUVD_MPC_SET_MUXB0)); 675 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 676 RREG32(mmUVD_MPC_SET_MUXB1)); 677 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 678 RREG32(mmUVD_MPC_SET_MUX)); 679 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 680 RREG32(mmUVD_MPC_SET_ALU)); 681 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 682 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 683 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 684 RREG32(mmUVD_VCPU_CACHE_SIZE0)); 685 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 686 RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 687 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 688 RREG32(mmUVD_VCPU_CACHE_SIZE1)); 689 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 690 RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 691 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 692 RREG32(mmUVD_VCPU_CACHE_SIZE2)); 693 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 694 RREG32(mmUVD_VCPU_CNTL)); 695 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 696 RREG32(mmUVD_SOFT_RESET)); 697 dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n", 698 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)); 699 dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n", 700 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)); 701 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 702 RREG32(mmUVD_RBC_IB_SIZE)); 703 dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n", 704 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)); 705 dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n", 706 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)); 707 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 708 RREG32(mmUVD_RBC_RB_RPTR)); 709 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 710 RREG32(mmUVD_RBC_RB_WPTR)); 711 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 712 RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 713 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 714 RREG32(mmUVD_RBC_RB_CNTL)); 715 dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 716 RREG32(mmUVD_STATUS)); 717 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 718 RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 719 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 720 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 721 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 722 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 723 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 724 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 725 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 726 RREG32(mmUVD_CONTEXT_ID)); 727 } 728 729 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 730 struct amdgpu_irq_src *source, 731 unsigned type, 732 enum amdgpu_interrupt_state state) 733 { 734 // TODO 735 return 0; 736 } 737 738 static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 739 struct amdgpu_irq_src *source, 740 struct amdgpu_iv_entry *entry) 741 { 742 DRM_DEBUG("IH: UVD TRAP\n"); 743 amdgpu_fence_process(&adev->uvd.ring); 744 return 0; 745 } 746 747 static int uvd_v5_0_set_clockgating_state(void *handle, 748 enum amd_clockgating_state state) 749 { 750 return 0; 751 } 752 753 static int uvd_v5_0_set_powergating_state(void *handle, 754 enum amd_powergating_state state) 755 { 756 /* This doesn't actually powergate the UVD block. 757 * That's done in the dpm code via the SMC. This 758 * just re-inits the block as necessary. The actual 759 * gating still happens in the dpm code. We should 760 * revisit this when there is a cleaner line between 761 * the smc and the hw blocks 762 */ 763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 764 765 if (state == AMD_PG_STATE_GATE) { 766 uvd_v5_0_stop(adev); 767 return 0; 768 } else { 769 return uvd_v5_0_start(adev); 770 } 771 } 772 773 const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 774 .early_init = uvd_v5_0_early_init, 775 .late_init = NULL, 776 .sw_init = uvd_v5_0_sw_init, 777 .sw_fini = uvd_v5_0_sw_fini, 778 .hw_init = uvd_v5_0_hw_init, 779 .hw_fini = uvd_v5_0_hw_fini, 780 .suspend = uvd_v5_0_suspend, 781 .resume = uvd_v5_0_resume, 782 .is_idle = uvd_v5_0_is_idle, 783 .wait_for_idle = uvd_v5_0_wait_for_idle, 784 .soft_reset = uvd_v5_0_soft_reset, 785 .print_status = uvd_v5_0_print_status, 786 .set_clockgating_state = uvd_v5_0_set_clockgating_state, 787 .set_powergating_state = uvd_v5_0_set_powergating_state, 788 }; 789 790 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 791 .get_rptr = uvd_v5_0_ring_get_rptr, 792 .get_wptr = uvd_v5_0_ring_get_wptr, 793 .set_wptr = uvd_v5_0_ring_set_wptr, 794 .parse_cs = amdgpu_uvd_ring_parse_cs, 795 .emit_ib = uvd_v5_0_ring_emit_ib, 796 .emit_fence = uvd_v5_0_ring_emit_fence, 797 .test_ring = uvd_v5_0_ring_test_ring, 798 .test_ib = uvd_v5_0_ring_test_ib, 799 .insert_nop = amdgpu_ring_insert_nop, 800 }; 801 802 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 803 { 804 adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; 805 } 806 807 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 808 .set = uvd_v5_0_set_interrupt_state, 809 .process = uvd_v5_0_process_interrupt, 810 }; 811 812 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 813 { 814 adev->uvd.irq.num_types = 1; 815 adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 816 } 817