1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25c366be54SSam Ravnborg #include <linux/delay.h> 26aaa36a97SAlex Deucher #include <linux/firmware.h> 27c366be54SSam Ravnborg 28aaa36a97SAlex Deucher #include "amdgpu.h" 29aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 30aaa36a97SAlex Deucher #include "vid.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 32aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 34aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 35d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 36be3ecca7STom St Denis #include "vi.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 384be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 39091aec0bSAndrey Grodzovsky #include "ivsrcid/ivsrcid_vislands30.h" 40aaa36a97SAlex Deucher 41aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 43aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 44aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 45809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 46809a6a62SRex Zhu enum amd_clockgating_state state); 47809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 48809a6a62SRex Zhu bool enable); 49aaa36a97SAlex Deucher /** 50aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 51aaa36a97SAlex Deucher * 52aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 53aaa36a97SAlex Deucher * 54aaa36a97SAlex Deucher * Returns the current hardware read pointer 55aaa36a97SAlex Deucher */ 56536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 57aaa36a97SAlex Deucher { 58aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 59aaa36a97SAlex Deucher 60aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 61aaa36a97SAlex Deucher } 62aaa36a97SAlex Deucher 63aaa36a97SAlex Deucher /** 64aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 65aaa36a97SAlex Deucher * 66aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 67aaa36a97SAlex Deucher * 68aaa36a97SAlex Deucher * Returns the current hardware write pointer 69aaa36a97SAlex Deucher */ 70536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 71aaa36a97SAlex Deucher { 72aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 73aaa36a97SAlex Deucher 74aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 75aaa36a97SAlex Deucher } 76aaa36a97SAlex Deucher 77aaa36a97SAlex Deucher /** 78aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 79aaa36a97SAlex Deucher * 80aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 81aaa36a97SAlex Deucher * 82aaa36a97SAlex Deucher * Commits the write pointer to the hardware 83aaa36a97SAlex Deucher */ 84aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 85aaa36a97SAlex Deucher { 86aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 87aaa36a97SAlex Deucher 88536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 89aaa36a97SAlex Deucher } 90aaa36a97SAlex Deucher 915fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 92aaa36a97SAlex Deucher { 935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 942bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 955fc3aeebSyanyang1 96aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 97aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 98aaa36a97SAlex Deucher 99aaa36a97SAlex Deucher return 0; 100aaa36a97SAlex Deucher } 101aaa36a97SAlex Deucher 1025fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 103aaa36a97SAlex Deucher { 104aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1055fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 106aaa36a97SAlex Deucher int r; 107aaa36a97SAlex Deucher 108aaa36a97SAlex Deucher /* UVD TRAP */ 1091ffdeca6SChristian König r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 110aaa36a97SAlex Deucher if (r) 111aaa36a97SAlex Deucher return r; 112aaa36a97SAlex Deucher 113aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 114aaa36a97SAlex Deucher if (r) 115aaa36a97SAlex Deucher return r; 116aaa36a97SAlex Deucher 1172bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 118aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 1191c6d567bSNirmoy Das r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 120c107171bSChristian König AMDGPU_RING_PRIO_DEFAULT, NULL); 12133d5bd07SEmily Deng if (r) 12233d5bd07SEmily Deng return r; 12333d5bd07SEmily Deng 1243b34c14fSChris Wilson r = amdgpu_uvd_resume(adev); 1253b34c14fSChris Wilson if (r) 1263b34c14fSChris Wilson return r; 1273b34c14fSChris Wilson 12833d5bd07SEmily Deng r = amdgpu_uvd_entity_init(adev); 129aaa36a97SAlex Deucher 130aaa36a97SAlex Deucher return r; 131aaa36a97SAlex Deucher } 132aaa36a97SAlex Deucher 1335fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 134aaa36a97SAlex Deucher { 135aaa36a97SAlex Deucher int r; 1365fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 139aaa36a97SAlex Deucher if (r) 140aaa36a97SAlex Deucher return r; 141aaa36a97SAlex Deucher 14250237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 143aaa36a97SAlex Deucher } 144aaa36a97SAlex Deucher 145aaa36a97SAlex Deucher /** 146aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 147aaa36a97SAlex Deucher * 148c890ace5SLee Jones * @handle: handle used to pass amdgpu_device pointer 149aaa36a97SAlex Deucher * 150aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 151aaa36a97SAlex Deucher */ 1525fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 153aaa36a97SAlex Deucher { 1545fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 156aaa36a97SAlex Deucher uint32_t tmp; 157aaa36a97SAlex Deucher int r; 158aaa36a97SAlex Deucher 159e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 161e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 162aaa36a97SAlex Deucher 163c66ed765SAndrey Grodzovsky r = amdgpu_ring_test_helper(ring); 164c66ed765SAndrey Grodzovsky if (r) 165aaa36a97SAlex Deucher goto done; 166aaa36a97SAlex Deucher 167a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 168aaa36a97SAlex Deucher if (r) { 169aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170aaa36a97SAlex Deucher goto done; 171aaa36a97SAlex Deucher } 172aaa36a97SAlex Deucher 173aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176aaa36a97SAlex Deucher 177aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180aaa36a97SAlex Deucher 181aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184aaa36a97SAlex Deucher 185aaa36a97SAlex Deucher /* Clear timeout status bits */ 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 188aaa36a97SAlex Deucher 189aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 191aaa36a97SAlex Deucher 192a27de35cSChristian König amdgpu_ring_commit(ring); 193e3e672e6SRex Zhu 194aaa36a97SAlex Deucher done: 195aaa36a97SAlex Deucher if (!r) 196aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher return r; 199e3e672e6SRex Zhu 200aaa36a97SAlex Deucher } 201aaa36a97SAlex Deucher 202aaa36a97SAlex Deucher /** 203aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 204aaa36a97SAlex Deucher * 205c890ace5SLee Jones * @handle: handle used to pass amdgpu_device pointer 206aaa36a97SAlex Deucher * 207aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 208aaa36a97SAlex Deucher */ 2095fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 210aaa36a97SAlex Deucher { 2115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212aaa36a97SAlex Deucher 213*d82e2c24SAndrey Grodzovsky cancel_delayed_work_sync(&adev->uvd.idle_work); 214*d82e2c24SAndrey Grodzovsky 215*d82e2c24SAndrey Grodzovsky if (RREG32(mmUVD_STATUS) != 0) 216*d82e2c24SAndrey Grodzovsky uvd_v5_0_stop(adev); 217*d82e2c24SAndrey Grodzovsky 218*d82e2c24SAndrey Grodzovsky return 0; 219*d82e2c24SAndrey Grodzovsky } 220*d82e2c24SAndrey Grodzovsky 221*d82e2c24SAndrey Grodzovsky static int uvd_v5_0_suspend(void *handle) 222*d82e2c24SAndrey Grodzovsky { 223*d82e2c24SAndrey Grodzovsky int r; 224*d82e2c24SAndrey Grodzovsky struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225*d82e2c24SAndrey Grodzovsky 226859e4659SEvan Quan /* 227859e4659SEvan Quan * Proper cleanups before halting the HW engine: 228859e4659SEvan Quan * - cancel the delayed idle work 229859e4659SEvan Quan * - enable powergating 230859e4659SEvan Quan * - enable clockgating 231859e4659SEvan Quan * - disable dpm 232859e4659SEvan Quan * 233859e4659SEvan Quan * TODO: to align with the VCN implementation, move the 234859e4659SEvan Quan * jobs for clockgating/powergating/dpm setting to 235859e4659SEvan Quan * ->set_powergating_state(). 236859e4659SEvan Quan */ 237859e4659SEvan Quan cancel_delayed_work_sync(&adev->uvd.idle_work); 238859e4659SEvan Quan 239859e4659SEvan Quan if (adev->pm.dpm_enabled) { 240859e4659SEvan Quan amdgpu_dpm_enable_uvd(adev, false); 241859e4659SEvan Quan } else { 242859e4659SEvan Quan amdgpu_asic_set_uvd_clocks(adev, 0, 0); 243859e4659SEvan Quan /* shutdown the UVD block */ 244859e4659SEvan Quan amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 245859e4659SEvan Quan AMD_PG_STATE_GATE); 246859e4659SEvan Quan amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 247859e4659SEvan Quan AMD_CG_STATE_GATE); 248859e4659SEvan Quan } 249859e4659SEvan Quan 2503f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 251aaa36a97SAlex Deucher if (r) 252aaa36a97SAlex Deucher return r; 253aaa36a97SAlex Deucher 25450237287SRex Zhu return amdgpu_uvd_suspend(adev); 255aaa36a97SAlex Deucher } 256aaa36a97SAlex Deucher 2575fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 258aaa36a97SAlex Deucher { 259aaa36a97SAlex Deucher int r; 2605fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 261aaa36a97SAlex Deucher 262aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 263aaa36a97SAlex Deucher if (r) 264aaa36a97SAlex Deucher return r; 265aaa36a97SAlex Deucher 26650237287SRex Zhu return uvd_v5_0_hw_init(adev); 267aaa36a97SAlex Deucher } 268aaa36a97SAlex Deucher 269aaa36a97SAlex Deucher /** 270aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 271aaa36a97SAlex Deucher * 272aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 273aaa36a97SAlex Deucher * 274aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 275aaa36a97SAlex Deucher */ 276aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 277aaa36a97SAlex Deucher { 278aaa36a97SAlex Deucher uint64_t offset; 279aaa36a97SAlex Deucher uint32_t size; 280aaa36a97SAlex Deucher 281f349f772SBernard Zhao /* program memory controller bits 0-27 */ 282aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 2832bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr)); 284aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 2852bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr)); 286aaa36a97SAlex Deucher 287aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 288c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 289aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 290aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 291aaa36a97SAlex Deucher 292aaa36a97SAlex Deucher offset += size; 293c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 294aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 295aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 296aaa36a97SAlex Deucher 297aaa36a97SAlex Deucher offset += size; 298c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 299c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 300aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 301aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 302549300ceSAlex Deucher 303549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 304549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 305549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 306aaa36a97SAlex Deucher } 307aaa36a97SAlex Deucher 308aaa36a97SAlex Deucher /** 309aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 310aaa36a97SAlex Deucher * 311aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 312aaa36a97SAlex Deucher * 313aaa36a97SAlex Deucher * Setup and start the UVD block 314aaa36a97SAlex Deucher */ 315aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 316aaa36a97SAlex Deucher { 3172bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 318aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 319aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 320aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 321aaa36a97SAlex Deucher int i, j, r; 322aaa36a97SAlex Deucher 323aaa36a97SAlex Deucher /*disable DPG */ 324aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 325aaa36a97SAlex Deucher 326aaa36a97SAlex Deucher /* disable byte swapping */ 327aaa36a97SAlex Deucher lmi_swap_cntl = 0; 328aaa36a97SAlex Deucher mp_swap_cntl = 0; 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 331aaa36a97SAlex Deucher 332aaa36a97SAlex Deucher /* disable interupt */ 333aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 334aaa36a97SAlex Deucher 335aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 336aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 337aaa36a97SAlex Deucher mdelay(1); 338aaa36a97SAlex Deucher 339aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 340aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 341aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 342aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 343aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 344aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 345aaa36a97SAlex Deucher mdelay(5); 346aaa36a97SAlex Deucher 347aaa36a97SAlex Deucher /* take UVD block out of reset */ 348aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 349aaa36a97SAlex Deucher mdelay(5); 350aaa36a97SAlex Deucher 351aaa36a97SAlex Deucher /* initialize UVD memory controller */ 352aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 353aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 354aaa36a97SAlex Deucher 355aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 356aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 357aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 358aaa36a97SAlex Deucher mp_swap_cntl = 0; 359aaa36a97SAlex Deucher #endif 360aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 361aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 362aaa36a97SAlex Deucher 363aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 364aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 365aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 366aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 367aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 368aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 369aaa36a97SAlex Deucher 370aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 371aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 372aaa36a97SAlex Deucher mdelay(5); 373aaa36a97SAlex Deucher 374aaa36a97SAlex Deucher /* enable VCPU clock */ 375aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 376aaa36a97SAlex Deucher 377aaa36a97SAlex Deucher /* enable UMC */ 378aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 379aaa36a97SAlex Deucher 380aaa36a97SAlex Deucher /* boot up the VCPU */ 381aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 382aaa36a97SAlex Deucher mdelay(10); 383aaa36a97SAlex Deucher 384aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 385aaa36a97SAlex Deucher uint32_t status; 386aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 387aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 388aaa36a97SAlex Deucher if (status & 2) 389aaa36a97SAlex Deucher break; 390aaa36a97SAlex Deucher mdelay(10); 391aaa36a97SAlex Deucher } 392aaa36a97SAlex Deucher r = 0; 393aaa36a97SAlex Deucher if (status & 2) 394aaa36a97SAlex Deucher break; 395aaa36a97SAlex Deucher 396aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 397aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 398aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 399aaa36a97SAlex Deucher mdelay(10); 400aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 401aaa36a97SAlex Deucher mdelay(10); 402aaa36a97SAlex Deucher r = -1; 403aaa36a97SAlex Deucher } 404aaa36a97SAlex Deucher 405aaa36a97SAlex Deucher if (r) { 406aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 407aaa36a97SAlex Deucher return r; 408aaa36a97SAlex Deucher } 409aaa36a97SAlex Deucher /* enable master interrupt */ 410aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 411aaa36a97SAlex Deucher 412aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 413aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 414aaa36a97SAlex Deucher 415aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 416aaa36a97SAlex Deucher tmp = 0; 417aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 418aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 419aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 420aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 421aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 422aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 423aaa36a97SAlex Deucher /* force RBC into idle state */ 424aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 425aaa36a97SAlex Deucher 426aaa36a97SAlex Deucher /* set the write pointer delay */ 427aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 428aaa36a97SAlex Deucher 429aaa36a97SAlex Deucher /* set the wb address */ 430aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 431aaa36a97SAlex Deucher 432f349f772SBernard Zhao /* program the RB_BASE for ring buffer */ 433aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 434aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 435aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 436aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 437aaa36a97SAlex Deucher 438aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 439aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 440aaa36a97SAlex Deucher 441aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 442536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 443aaa36a97SAlex Deucher 444aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 445aaa36a97SAlex Deucher 446aaa36a97SAlex Deucher return 0; 447aaa36a97SAlex Deucher } 448aaa36a97SAlex Deucher 449aaa36a97SAlex Deucher /** 450aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 451aaa36a97SAlex Deucher * 452aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 453aaa36a97SAlex Deucher * 454aaa36a97SAlex Deucher * stop the UVD block 455aaa36a97SAlex Deucher */ 456aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 457aaa36a97SAlex Deucher { 458aaa36a97SAlex Deucher /* force RBC into idle state */ 459aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 460aaa36a97SAlex Deucher 461aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 462aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 463aaa36a97SAlex Deucher mdelay(1); 464aaa36a97SAlex Deucher 465aaa36a97SAlex Deucher /* put VCPU into reset */ 466aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 467aaa36a97SAlex Deucher mdelay(5); 468aaa36a97SAlex Deucher 469aaa36a97SAlex Deucher /* disable VCPU clock */ 470aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 471aaa36a97SAlex Deucher 472aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 473aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 474e3e672e6SRex Zhu 475e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 476aaa36a97SAlex Deucher } 477aaa36a97SAlex Deucher 478aaa36a97SAlex Deucher /** 479aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 480aaa36a97SAlex Deucher * 481aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 482c890ace5SLee Jones * @addr: address 483c890ace5SLee Jones * @seq: sequence number 484c890ace5SLee Jones * @flags: fence related flags 485aaa36a97SAlex Deucher * 486aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 487aaa36a97SAlex Deucher */ 488aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 489890ee23fSChunming Zhou unsigned flags) 490aaa36a97SAlex Deucher { 491890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 492aaa36a97SAlex Deucher 493aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 494aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 495aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 496aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 497aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 498aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 499aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 500aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 501aaa36a97SAlex Deucher 502aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 503aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 504aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 505aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 506aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 507aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 508aaa36a97SAlex Deucher } 509aaa36a97SAlex Deucher 510aaa36a97SAlex Deucher /** 511aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 512aaa36a97SAlex Deucher * 513aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 514aaa36a97SAlex Deucher * 515aaa36a97SAlex Deucher * Test if we can successfully write to the context register 516aaa36a97SAlex Deucher */ 517aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 518aaa36a97SAlex Deucher { 519aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 520aaa36a97SAlex Deucher uint32_t tmp = 0; 521aaa36a97SAlex Deucher unsigned i; 522aaa36a97SAlex Deucher int r; 523aaa36a97SAlex Deucher 524aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 525a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 526dc9eeff8SChristian König if (r) 527aaa36a97SAlex Deucher return r; 528aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 529aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 530a27de35cSChristian König amdgpu_ring_commit(ring); 531aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 532aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 533aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 534aaa36a97SAlex Deucher break; 535c366be54SSam Ravnborg udelay(1); 536aaa36a97SAlex Deucher } 537aaa36a97SAlex Deucher 538dc9eeff8SChristian König if (i >= adev->usec_timeout) 539dc9eeff8SChristian König r = -ETIMEDOUT; 540dc9eeff8SChristian König 541aaa36a97SAlex Deucher return r; 542aaa36a97SAlex Deucher } 543aaa36a97SAlex Deucher 544aaa36a97SAlex Deucher /** 545aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 546aaa36a97SAlex Deucher * 547aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 548c890ace5SLee Jones * @job: job to retrieve vmid from 549aaa36a97SAlex Deucher * @ib: indirect buffer to execute 550c890ace5SLee Jones * @flags: unused 551aaa36a97SAlex Deucher * 552aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 553aaa36a97SAlex Deucher */ 554aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 55534955e03SRex Zhu struct amdgpu_job *job, 556d88bf583SChristian König struct amdgpu_ib *ib, 557c4c905ecSJack Xiao uint32_t flags) 558aaa36a97SAlex Deucher { 559aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 560aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 561aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 562aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 563aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 564aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 565aaa36a97SAlex Deucher } 566aaa36a97SAlex Deucher 5670232e306SLeo Liu static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 5680232e306SLeo Liu { 5690232e306SLeo Liu int i; 5700232e306SLeo Liu 5710232e306SLeo Liu WARN_ON(ring->wptr % 2 || count % 2); 5720232e306SLeo Liu 5730232e306SLeo Liu for (i = 0; i < count / 2; i++) { 5740232e306SLeo Liu amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 5750232e306SLeo Liu amdgpu_ring_write(ring, 0); 5760232e306SLeo Liu } 5770232e306SLeo Liu } 5780232e306SLeo Liu 5795fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 580aaa36a97SAlex Deucher { 5815fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5825fc3aeebSyanyang1 583aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 584aaa36a97SAlex Deucher } 585aaa36a97SAlex Deucher 5865fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 587aaa36a97SAlex Deucher { 588aaa36a97SAlex Deucher unsigned i; 5895fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 590aaa36a97SAlex Deucher 591aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 592aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 593aaa36a97SAlex Deucher return 0; 594aaa36a97SAlex Deucher } 595aaa36a97SAlex Deucher return -ETIMEDOUT; 596aaa36a97SAlex Deucher } 597aaa36a97SAlex Deucher 5985fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 599aaa36a97SAlex Deucher { 6005fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6015fc3aeebSyanyang1 602aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 603aaa36a97SAlex Deucher 604aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 605aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 606aaa36a97SAlex Deucher mdelay(5); 607aaa36a97SAlex Deucher 608aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 609aaa36a97SAlex Deucher } 610aaa36a97SAlex Deucher 611aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 612aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 613aaa36a97SAlex Deucher unsigned type, 614aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 615aaa36a97SAlex Deucher { 616aaa36a97SAlex Deucher // TODO 617aaa36a97SAlex Deucher return 0; 618aaa36a97SAlex Deucher } 619aaa36a97SAlex Deucher 620aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 621aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 622aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 623aaa36a97SAlex Deucher { 624aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 6252bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 626aaa36a97SAlex Deucher return 0; 627aaa36a97SAlex Deucher } 628aaa36a97SAlex Deucher 629809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 630be3ecca7STom St Denis { 631809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 632be3ecca7STom St Denis 633be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 634809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 635be3ecca7STom St Denis 636be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 637be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 638be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 639be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 640be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 641be3ecca7STom St Denis 642809a6a62SRex Zhu if (enable) { 643809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 644809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 645809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 646809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 647809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 648809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 649809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 650809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 651809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 652809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 653809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 654809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 655809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 656809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 657809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 658809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 659809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 660809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6613c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6623c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6633c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 664809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 665809a6a62SRex Zhu data1 |= suvd_flags; 666809a6a62SRex Zhu } else { 667809a6a62SRex Zhu data3 = 0; 668809a6a62SRex Zhu data1 = 0; 669809a6a62SRex Zhu } 670809a6a62SRex Zhu 671809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 672809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 673809a6a62SRex Zhu } 674809a6a62SRex Zhu 675809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 676809a6a62SRex Zhu { 677809a6a62SRex Zhu uint32_t data, data2; 678809a6a62SRex Zhu 679809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 680809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 681809a6a62SRex Zhu 682809a6a62SRex Zhu 683809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 684809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 685809a6a62SRex Zhu 686809a6a62SRex Zhu 687be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 688be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 689be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 690be3ecca7STom St Denis 691be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 692be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 693be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 694be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 695be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 696be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 697be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 698be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 699be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 700be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 701be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 702be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 703be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 704be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 705be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 706be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 707be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 708be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 709be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 710be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 711be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 712be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 713be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 714be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 715be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 716be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 717be3ecca7STom St Denis 718be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 719be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 720be3ecca7STom St Denis } 721be3ecca7STom St Denis 722be3ecca7STom St Denis #if 0 723be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 724be3ecca7STom St Denis { 725be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 726be3ecca7STom St Denis 727be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 728be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 729be3ecca7STom St Denis 730be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 731be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 732be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 733be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 734be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 735be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 736be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 737be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 738be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 739be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 740be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 741be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 742be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 743be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 744be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 745be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 746be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 747be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 748be3ecca7STom St Denis 749be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 750be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 751be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 752be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 753be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 754be3ecca7STom St Denis 755be3ecca7STom St Denis data |= cgc_flags; 756be3ecca7STom St Denis data1 |= suvd_flags; 757be3ecca7STom St Denis 758be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 759be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 760be3ecca7STom St Denis } 761be3ecca7STom St Denis #endif 762be3ecca7STom St Denis 763809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 764809a6a62SRex Zhu bool enable) 765809a6a62SRex Zhu { 766809a6a62SRex Zhu u32 orig, data; 767809a6a62SRex Zhu 768809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 769809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 770809a6a62SRex Zhu data |= 0xfff; 771809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 772809a6a62SRex Zhu 773809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 774809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 775809a6a62SRex Zhu if (orig != data) 776809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 777809a6a62SRex Zhu } else { 778809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 779809a6a62SRex Zhu data &= ~0xfff; 780809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 781809a6a62SRex Zhu 782809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 783809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 784809a6a62SRex Zhu if (orig != data) 785809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 786809a6a62SRex Zhu } 787809a6a62SRex Zhu } 7884be5097cSRex Zhu 7895fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7905fc3aeebSyanyang1 enum amd_clockgating_state state) 791aaa36a97SAlex Deucher { 79235e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 793a9d4fe2fSNirmoy Das bool enable = (state == AMD_CG_STATE_GATE); 79435e5912dSAlex Deucher 795be3ecca7STom St Denis if (enable) { 796be3ecca7STom St Denis /* wait for STATUS to clear */ 797be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 798be3ecca7STom St Denis return -EBUSY; 799809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 800be3ecca7STom St Denis 801be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 802be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 803809a6a62SRex Zhu } else { 804809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 805be3ecca7STom St Denis } 806be3ecca7STom St Denis 807809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 808aaa36a97SAlex Deucher return 0; 809aaa36a97SAlex Deucher } 810aaa36a97SAlex Deucher 8115fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 8125fc3aeebSyanyang1 enum amd_powergating_state state) 813aaa36a97SAlex Deucher { 814aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 815aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 816aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 817aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 818aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 819aaa36a97SAlex Deucher * the smc and the hw blocks 820aaa36a97SAlex Deucher */ 8215fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 822c8781f56SHuang Rui int ret = 0; 8235fc3aeebSyanyang1 8245fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 825aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 826aaa36a97SAlex Deucher } else { 827c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 828c8781f56SHuang Rui if (ret) 829c8781f56SHuang Rui goto out; 830aaa36a97SAlex Deucher } 831c8781f56SHuang Rui 832c8781f56SHuang Rui out: 833c8781f56SHuang Rui return ret; 834c8781f56SHuang Rui } 835c8781f56SHuang Rui 836c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 837c8781f56SHuang Rui { 838c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 839c8781f56SHuang Rui int data; 840c8781f56SHuang Rui 841c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 842c8781f56SHuang Rui 843254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 844254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 845c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 846c8781f56SHuang Rui goto out; 847c8781f56SHuang Rui } 848c8781f56SHuang Rui 849c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 850c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 851c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 852c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 853c8781f56SHuang Rui 854c8781f56SHuang Rui out: 855c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 856aaa36a97SAlex Deucher } 857aaa36a97SAlex Deucher 858a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 85988a907d6STom St Denis .name = "uvd_v5_0", 860aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 861aaa36a97SAlex Deucher .late_init = NULL, 862aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 863aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 864aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 865aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 866aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 867aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 868aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 869aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 870aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 871aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 872aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 873c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 874aaa36a97SAlex Deucher }; 875aaa36a97SAlex Deucher 876aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 87721cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 87879887142SChristian König .align_mask = 0xf, 879536fbf94SKen Wang .support_64bit_ptrs = false, 8807ee250b1SLeo Liu .no_user_fence = true, 881aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 882aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 883aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 884aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 885e12f3d7aSChristian König .emit_frame_size = 886e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 887e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 888aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 889aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 890aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8918de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 8920232e306SLeo Liu .insert_nop = uvd_v5_0_ring_insert_nop, 8939e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 894c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 895c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 896aaa36a97SAlex Deucher }; 897aaa36a97SAlex Deucher 898aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 899aaa36a97SAlex Deucher { 9002bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 901aaa36a97SAlex Deucher } 902aaa36a97SAlex Deucher 903aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 904aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 905aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 906aaa36a97SAlex Deucher }; 907aaa36a97SAlex Deucher 908aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 909aaa36a97SAlex Deucher { 9102bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 9112bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 912aaa36a97SAlex Deucher } 913a1255107SAlex Deucher 914a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 915a1255107SAlex Deucher { 916a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 917a1255107SAlex Deucher .major = 5, 918a1255107SAlex Deucher .minor = 0, 919a1255107SAlex Deucher .rev = 0, 920a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 921a1255107SAlex Deucher }; 922