1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25c366be54SSam Ravnborg #include <linux/delay.h> 26aaa36a97SAlex Deucher #include <linux/firmware.h> 27c366be54SSam Ravnborg 28aaa36a97SAlex Deucher #include <drm/drmP.h> 29aaa36a97SAlex Deucher #include "amdgpu.h" 30aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 31aaa36a97SAlex Deucher #include "vid.h" 32aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 33aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 34aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 35aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 37be3ecca7STom St Denis #include "vi.h" 384be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 394be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 40091aec0bSAndrey Grodzovsky #include "ivsrcid/ivsrcid_vislands30.h" 41aaa36a97SAlex Deucher 42aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 43aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 44aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 45aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 46809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 47809a6a62SRex Zhu enum amd_clockgating_state state); 48809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 49809a6a62SRex Zhu bool enable); 50aaa36a97SAlex Deucher /** 51aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 52aaa36a97SAlex Deucher * 53aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 54aaa36a97SAlex Deucher * 55aaa36a97SAlex Deucher * Returns the current hardware read pointer 56aaa36a97SAlex Deucher */ 57536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 58aaa36a97SAlex Deucher { 59aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 60aaa36a97SAlex Deucher 61aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 62aaa36a97SAlex Deucher } 63aaa36a97SAlex Deucher 64aaa36a97SAlex Deucher /** 65aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 66aaa36a97SAlex Deucher * 67aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 68aaa36a97SAlex Deucher * 69aaa36a97SAlex Deucher * Returns the current hardware write pointer 70aaa36a97SAlex Deucher */ 71536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 72aaa36a97SAlex Deucher { 73aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 74aaa36a97SAlex Deucher 75aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 76aaa36a97SAlex Deucher } 77aaa36a97SAlex Deucher 78aaa36a97SAlex Deucher /** 79aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 80aaa36a97SAlex Deucher * 81aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 82aaa36a97SAlex Deucher * 83aaa36a97SAlex Deucher * Commits the write pointer to the hardware 84aaa36a97SAlex Deucher */ 85aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 86aaa36a97SAlex Deucher { 87aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 88aaa36a97SAlex Deucher 89536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 90aaa36a97SAlex Deucher } 91aaa36a97SAlex Deucher 925fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 93aaa36a97SAlex Deucher { 945fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 952bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 965fc3aeebSyanyang1 97aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 98aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 99aaa36a97SAlex Deucher 100aaa36a97SAlex Deucher return 0; 101aaa36a97SAlex Deucher } 102aaa36a97SAlex Deucher 1035fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 104aaa36a97SAlex Deucher { 105aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1065fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 107aaa36a97SAlex Deucher int r; 108aaa36a97SAlex Deucher 109aaa36a97SAlex Deucher /* UVD TRAP */ 1101ffdeca6SChristian König r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 111aaa36a97SAlex Deucher if (r) 112aaa36a97SAlex Deucher return r; 113aaa36a97SAlex Deucher 114aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 115aaa36a97SAlex Deucher if (r) 116aaa36a97SAlex Deucher return r; 117aaa36a97SAlex Deucher 1182bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 119aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 1202bb795f5SJames Zhu r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 12133d5bd07SEmily Deng if (r) 12233d5bd07SEmily Deng return r; 12333d5bd07SEmily Deng 1243b34c14fSChris Wilson r = amdgpu_uvd_resume(adev); 1253b34c14fSChris Wilson if (r) 1263b34c14fSChris Wilson return r; 1273b34c14fSChris Wilson 12833d5bd07SEmily Deng r = amdgpu_uvd_entity_init(adev); 129aaa36a97SAlex Deucher 130aaa36a97SAlex Deucher return r; 131aaa36a97SAlex Deucher } 132aaa36a97SAlex Deucher 1335fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 134aaa36a97SAlex Deucher { 135aaa36a97SAlex Deucher int r; 1365fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 139aaa36a97SAlex Deucher if (r) 140aaa36a97SAlex Deucher return r; 141aaa36a97SAlex Deucher 14250237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 143aaa36a97SAlex Deucher } 144aaa36a97SAlex Deucher 145aaa36a97SAlex Deucher /** 146aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 147aaa36a97SAlex Deucher * 148aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 149aaa36a97SAlex Deucher * 150aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 151aaa36a97SAlex Deucher */ 1525fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 153aaa36a97SAlex Deucher { 1545fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 156aaa36a97SAlex Deucher uint32_t tmp; 157aaa36a97SAlex Deucher int r; 158aaa36a97SAlex Deucher 159e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 161e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 162aaa36a97SAlex Deucher 163c66ed765SAndrey Grodzovsky r = amdgpu_ring_test_helper(ring); 164c66ed765SAndrey Grodzovsky if (r) 165aaa36a97SAlex Deucher goto done; 166aaa36a97SAlex Deucher 167a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 168aaa36a97SAlex Deucher if (r) { 169aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170aaa36a97SAlex Deucher goto done; 171aaa36a97SAlex Deucher } 172aaa36a97SAlex Deucher 173aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176aaa36a97SAlex Deucher 177aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180aaa36a97SAlex Deucher 181aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184aaa36a97SAlex Deucher 185aaa36a97SAlex Deucher /* Clear timeout status bits */ 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 188aaa36a97SAlex Deucher 189aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 191aaa36a97SAlex Deucher 192a27de35cSChristian König amdgpu_ring_commit(ring); 193e3e672e6SRex Zhu 194aaa36a97SAlex Deucher done: 195aaa36a97SAlex Deucher if (!r) 196aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher return r; 199e3e672e6SRex Zhu 200aaa36a97SAlex Deucher } 201aaa36a97SAlex Deucher 202aaa36a97SAlex Deucher /** 203aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 204aaa36a97SAlex Deucher * 205aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 206aaa36a97SAlex Deucher * 207aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 208aaa36a97SAlex Deucher */ 2095fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 210aaa36a97SAlex Deucher { 2115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2122bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 213aaa36a97SAlex Deucher 214e3e672e6SRex Zhu if (RREG32(mmUVD_STATUS) != 0) 215aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 216e3e672e6SRex Zhu 217c66ed765SAndrey Grodzovsky ring->sched.ready = false; 218aaa36a97SAlex Deucher 219aaa36a97SAlex Deucher return 0; 220aaa36a97SAlex Deucher } 221aaa36a97SAlex Deucher 2225fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 223aaa36a97SAlex Deucher { 224aaa36a97SAlex Deucher int r; 2255fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226aaa36a97SAlex Deucher 2273f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 228aaa36a97SAlex Deucher if (r) 229aaa36a97SAlex Deucher return r; 230809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 231aaa36a97SAlex Deucher 23250237287SRex Zhu return amdgpu_uvd_suspend(adev); 233aaa36a97SAlex Deucher } 234aaa36a97SAlex Deucher 2355fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 236aaa36a97SAlex Deucher { 237aaa36a97SAlex Deucher int r; 2385fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 239aaa36a97SAlex Deucher 240aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 241aaa36a97SAlex Deucher if (r) 242aaa36a97SAlex Deucher return r; 243aaa36a97SAlex Deucher 24450237287SRex Zhu return uvd_v5_0_hw_init(adev); 245aaa36a97SAlex Deucher } 246aaa36a97SAlex Deucher 247aaa36a97SAlex Deucher /** 248aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 249aaa36a97SAlex Deucher * 250aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 251aaa36a97SAlex Deucher * 252aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 253aaa36a97SAlex Deucher */ 254aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 255aaa36a97SAlex Deucher { 256aaa36a97SAlex Deucher uint64_t offset; 257aaa36a97SAlex Deucher uint32_t size; 258aaa36a97SAlex Deucher 259aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 260aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 2612bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr)); 262aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 2632bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr)); 264aaa36a97SAlex Deucher 265aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 266c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 267aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 268aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 269aaa36a97SAlex Deucher 270aaa36a97SAlex Deucher offset += size; 271c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 272aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 273aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 274aaa36a97SAlex Deucher 275aaa36a97SAlex Deucher offset += size; 276c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 277c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 278aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 279aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 280549300ceSAlex Deucher 281549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 282549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 283549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 284aaa36a97SAlex Deucher } 285aaa36a97SAlex Deucher 286aaa36a97SAlex Deucher /** 287aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 288aaa36a97SAlex Deucher * 289aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 290aaa36a97SAlex Deucher * 291aaa36a97SAlex Deucher * Setup and start the UVD block 292aaa36a97SAlex Deucher */ 293aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 294aaa36a97SAlex Deucher { 2952bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 296aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 297aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 298aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 299aaa36a97SAlex Deucher int i, j, r; 300aaa36a97SAlex Deucher 301aaa36a97SAlex Deucher /*disable DPG */ 302aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 303aaa36a97SAlex Deucher 304aaa36a97SAlex Deucher /* disable byte swapping */ 305aaa36a97SAlex Deucher lmi_swap_cntl = 0; 306aaa36a97SAlex Deucher mp_swap_cntl = 0; 307aaa36a97SAlex Deucher 308aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 309aaa36a97SAlex Deucher 310aaa36a97SAlex Deucher /* disable interupt */ 311aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 312aaa36a97SAlex Deucher 313aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 314aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 315aaa36a97SAlex Deucher mdelay(1); 316aaa36a97SAlex Deucher 317aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 318aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 319aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 320aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 321aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 322aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 323aaa36a97SAlex Deucher mdelay(5); 324aaa36a97SAlex Deucher 325aaa36a97SAlex Deucher /* take UVD block out of reset */ 326aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 327aaa36a97SAlex Deucher mdelay(5); 328aaa36a97SAlex Deucher 329aaa36a97SAlex Deucher /* initialize UVD memory controller */ 330aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 331aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 332aaa36a97SAlex Deucher 333aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 334aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 335aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 336aaa36a97SAlex Deucher mp_swap_cntl = 0; 337aaa36a97SAlex Deucher #endif 338aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 339aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 340aaa36a97SAlex Deucher 341aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 342aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 343aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 344aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 345aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 346aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 347aaa36a97SAlex Deucher 348aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 349aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 350aaa36a97SAlex Deucher mdelay(5); 351aaa36a97SAlex Deucher 352aaa36a97SAlex Deucher /* enable VCPU clock */ 353aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 354aaa36a97SAlex Deucher 355aaa36a97SAlex Deucher /* enable UMC */ 356aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 357aaa36a97SAlex Deucher 358aaa36a97SAlex Deucher /* boot up the VCPU */ 359aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 360aaa36a97SAlex Deucher mdelay(10); 361aaa36a97SAlex Deucher 362aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 363aaa36a97SAlex Deucher uint32_t status; 364aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 365aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 366aaa36a97SAlex Deucher if (status & 2) 367aaa36a97SAlex Deucher break; 368aaa36a97SAlex Deucher mdelay(10); 369aaa36a97SAlex Deucher } 370aaa36a97SAlex Deucher r = 0; 371aaa36a97SAlex Deucher if (status & 2) 372aaa36a97SAlex Deucher break; 373aaa36a97SAlex Deucher 374aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 375aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 376aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 377aaa36a97SAlex Deucher mdelay(10); 378aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 379aaa36a97SAlex Deucher mdelay(10); 380aaa36a97SAlex Deucher r = -1; 381aaa36a97SAlex Deucher } 382aaa36a97SAlex Deucher 383aaa36a97SAlex Deucher if (r) { 384aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 385aaa36a97SAlex Deucher return r; 386aaa36a97SAlex Deucher } 387aaa36a97SAlex Deucher /* enable master interrupt */ 388aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 389aaa36a97SAlex Deucher 390aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 391aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 392aaa36a97SAlex Deucher 393aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 394aaa36a97SAlex Deucher tmp = 0; 395aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 396aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 397aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 398aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 399aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 400aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 401aaa36a97SAlex Deucher /* force RBC into idle state */ 402aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 403aaa36a97SAlex Deucher 404aaa36a97SAlex Deucher /* set the write pointer delay */ 405aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 406aaa36a97SAlex Deucher 407aaa36a97SAlex Deucher /* set the wb address */ 408aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 409aaa36a97SAlex Deucher 410aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 411aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 412aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 413aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 414aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 415aaa36a97SAlex Deucher 416aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 417aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 418aaa36a97SAlex Deucher 419aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 420536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 421aaa36a97SAlex Deucher 422aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 423aaa36a97SAlex Deucher 424aaa36a97SAlex Deucher return 0; 425aaa36a97SAlex Deucher } 426aaa36a97SAlex Deucher 427aaa36a97SAlex Deucher /** 428aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 429aaa36a97SAlex Deucher * 430aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 431aaa36a97SAlex Deucher * 432aaa36a97SAlex Deucher * stop the UVD block 433aaa36a97SAlex Deucher */ 434aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 435aaa36a97SAlex Deucher { 436aaa36a97SAlex Deucher /* force RBC into idle state */ 437aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 438aaa36a97SAlex Deucher 439aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 440aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 441aaa36a97SAlex Deucher mdelay(1); 442aaa36a97SAlex Deucher 443aaa36a97SAlex Deucher /* put VCPU into reset */ 444aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 445aaa36a97SAlex Deucher mdelay(5); 446aaa36a97SAlex Deucher 447aaa36a97SAlex Deucher /* disable VCPU clock */ 448aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 449aaa36a97SAlex Deucher 450aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 451aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 452e3e672e6SRex Zhu 453e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 454aaa36a97SAlex Deucher } 455aaa36a97SAlex Deucher 456aaa36a97SAlex Deucher /** 457aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 458aaa36a97SAlex Deucher * 459aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 460aaa36a97SAlex Deucher * @fence: fence to emit 461aaa36a97SAlex Deucher * 462aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 463aaa36a97SAlex Deucher */ 464aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 465890ee23fSChunming Zhou unsigned flags) 466aaa36a97SAlex Deucher { 467890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 468aaa36a97SAlex Deucher 469aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 470aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 471aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 472aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 473aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 477aaa36a97SAlex Deucher 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 480aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 481aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 482aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 483aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 484aaa36a97SAlex Deucher } 485aaa36a97SAlex Deucher 486aaa36a97SAlex Deucher /** 487aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 488aaa36a97SAlex Deucher * 489aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 490aaa36a97SAlex Deucher * 491aaa36a97SAlex Deucher * Test if we can successfully write to the context register 492aaa36a97SAlex Deucher */ 493aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 494aaa36a97SAlex Deucher { 495aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 496aaa36a97SAlex Deucher uint32_t tmp = 0; 497aaa36a97SAlex Deucher unsigned i; 498aaa36a97SAlex Deucher int r; 499aaa36a97SAlex Deucher 500aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 501a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 502dc9eeff8SChristian König if (r) 503aaa36a97SAlex Deucher return r; 504aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 505aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 506a27de35cSChristian König amdgpu_ring_commit(ring); 507aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 508aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 509aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 510aaa36a97SAlex Deucher break; 511c366be54SSam Ravnborg udelay(1); 512aaa36a97SAlex Deucher } 513aaa36a97SAlex Deucher 514dc9eeff8SChristian König if (i >= adev->usec_timeout) 515dc9eeff8SChristian König r = -ETIMEDOUT; 516dc9eeff8SChristian König 517aaa36a97SAlex Deucher return r; 518aaa36a97SAlex Deucher } 519aaa36a97SAlex Deucher 520aaa36a97SAlex Deucher /** 521aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 522aaa36a97SAlex Deucher * 523aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 524aaa36a97SAlex Deucher * @ib: indirect buffer to execute 525aaa36a97SAlex Deucher * 526aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 527aaa36a97SAlex Deucher */ 528aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 52934955e03SRex Zhu struct amdgpu_job *job, 530d88bf583SChristian König struct amdgpu_ib *ib, 531c4c905ecSJack Xiao uint32_t flags) 532aaa36a97SAlex Deucher { 533aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 534aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 535aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 536aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 537aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 538aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 539aaa36a97SAlex Deucher } 540aaa36a97SAlex Deucher 5410232e306SLeo Liu static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 5420232e306SLeo Liu { 5430232e306SLeo Liu int i; 5440232e306SLeo Liu 5450232e306SLeo Liu WARN_ON(ring->wptr % 2 || count % 2); 5460232e306SLeo Liu 5470232e306SLeo Liu for (i = 0; i < count / 2; i++) { 5480232e306SLeo Liu amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 5490232e306SLeo Liu amdgpu_ring_write(ring, 0); 5500232e306SLeo Liu } 5510232e306SLeo Liu } 5520232e306SLeo Liu 5535fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 554aaa36a97SAlex Deucher { 5555fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5565fc3aeebSyanyang1 557aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 558aaa36a97SAlex Deucher } 559aaa36a97SAlex Deucher 5605fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 561aaa36a97SAlex Deucher { 562aaa36a97SAlex Deucher unsigned i; 5635fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 564aaa36a97SAlex Deucher 565aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 566aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 567aaa36a97SAlex Deucher return 0; 568aaa36a97SAlex Deucher } 569aaa36a97SAlex Deucher return -ETIMEDOUT; 570aaa36a97SAlex Deucher } 571aaa36a97SAlex Deucher 5725fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 573aaa36a97SAlex Deucher { 5745fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5755fc3aeebSyanyang1 576aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 577aaa36a97SAlex Deucher 578aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 579aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 580aaa36a97SAlex Deucher mdelay(5); 581aaa36a97SAlex Deucher 582aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 583aaa36a97SAlex Deucher } 584aaa36a97SAlex Deucher 585aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 586aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 587aaa36a97SAlex Deucher unsigned type, 588aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 589aaa36a97SAlex Deucher { 590aaa36a97SAlex Deucher // TODO 591aaa36a97SAlex Deucher return 0; 592aaa36a97SAlex Deucher } 593aaa36a97SAlex Deucher 594aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 595aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 596aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 597aaa36a97SAlex Deucher { 598aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 5992bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 600aaa36a97SAlex Deucher return 0; 601aaa36a97SAlex Deucher } 602aaa36a97SAlex Deucher 603809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 604be3ecca7STom St Denis { 605809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 606be3ecca7STom St Denis 607be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 608809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 609be3ecca7STom St Denis 610be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 611be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 612be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 613be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 614be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 615be3ecca7STom St Denis 616809a6a62SRex Zhu if (enable) { 617809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 618809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 619809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 620809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 621809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 622809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 623809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 624809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 625809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 626809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 627809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 628809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 629809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 630809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 631809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 632809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 633809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 634809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6353c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6363c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6373c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 638809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 639809a6a62SRex Zhu data1 |= suvd_flags; 640809a6a62SRex Zhu } else { 641809a6a62SRex Zhu data3 = 0; 642809a6a62SRex Zhu data1 = 0; 643809a6a62SRex Zhu } 644809a6a62SRex Zhu 645809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 646809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 647809a6a62SRex Zhu } 648809a6a62SRex Zhu 649809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 650809a6a62SRex Zhu { 651809a6a62SRex Zhu uint32_t data, data2; 652809a6a62SRex Zhu 653809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 654809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 655809a6a62SRex Zhu 656809a6a62SRex Zhu 657809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 658809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 659809a6a62SRex Zhu 660809a6a62SRex Zhu 661be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 662be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 663be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 664be3ecca7STom St Denis 665be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 666be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 667be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 668be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 669be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 670be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 671be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 672be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 673be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 674be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 675be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 676be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 677be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 678be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 679be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 680be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 681be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 682be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 683be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 684be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 685be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 686be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 687be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 688be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 689be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 690be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 691be3ecca7STom St Denis 692be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 693be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 694be3ecca7STom St Denis } 695be3ecca7STom St Denis 696be3ecca7STom St Denis #if 0 697be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 698be3ecca7STom St Denis { 699be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 700be3ecca7STom St Denis 701be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 702be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 703be3ecca7STom St Denis 704be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 705be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 706be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 707be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 708be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 709be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 710be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 711be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 712be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 713be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 714be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 715be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 716be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 717be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 718be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 719be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 720be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 721be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 722be3ecca7STom St Denis 723be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 724be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 725be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 726be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 727be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 728be3ecca7STom St Denis 729be3ecca7STom St Denis data |= cgc_flags; 730be3ecca7STom St Denis data1 |= suvd_flags; 731be3ecca7STom St Denis 732be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 733be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 734be3ecca7STom St Denis } 735be3ecca7STom St Denis #endif 736be3ecca7STom St Denis 737809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 738809a6a62SRex Zhu bool enable) 739809a6a62SRex Zhu { 740809a6a62SRex Zhu u32 orig, data; 741809a6a62SRex Zhu 742809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 743809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 744809a6a62SRex Zhu data |= 0xfff; 745809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 746809a6a62SRex Zhu 747809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 748809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 749809a6a62SRex Zhu if (orig != data) 750809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 751809a6a62SRex Zhu } else { 752809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 753809a6a62SRex Zhu data &= ~0xfff; 754809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 755809a6a62SRex Zhu 756809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 757809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 758809a6a62SRex Zhu if (orig != data) 759809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 760809a6a62SRex Zhu } 761809a6a62SRex Zhu } 7624be5097cSRex Zhu 7635fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7645fc3aeebSyanyang1 enum amd_clockgating_state state) 765aaa36a97SAlex Deucher { 76635e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 767be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 76835e5912dSAlex Deucher 769be3ecca7STom St Denis if (enable) { 770be3ecca7STom St Denis /* wait for STATUS to clear */ 771be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 772be3ecca7STom St Denis return -EBUSY; 773809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 774be3ecca7STom St Denis 775be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 776be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 777809a6a62SRex Zhu } else { 778809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 779be3ecca7STom St Denis } 780be3ecca7STom St Denis 781809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 782aaa36a97SAlex Deucher return 0; 783aaa36a97SAlex Deucher } 784aaa36a97SAlex Deucher 7855fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 7865fc3aeebSyanyang1 enum amd_powergating_state state) 787aaa36a97SAlex Deucher { 788aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 789aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 790aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 791aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 792aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 793aaa36a97SAlex Deucher * the smc and the hw blocks 794aaa36a97SAlex Deucher */ 7955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 796c8781f56SHuang Rui int ret = 0; 7975fc3aeebSyanyang1 7985fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 799aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 800aaa36a97SAlex Deucher } else { 801c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 802c8781f56SHuang Rui if (ret) 803c8781f56SHuang Rui goto out; 804aaa36a97SAlex Deucher } 805c8781f56SHuang Rui 806c8781f56SHuang Rui out: 807c8781f56SHuang Rui return ret; 808c8781f56SHuang Rui } 809c8781f56SHuang Rui 810c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 811c8781f56SHuang Rui { 812c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 813c8781f56SHuang Rui int data; 814c8781f56SHuang Rui 815c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 816c8781f56SHuang Rui 817254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 818254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 819c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 820c8781f56SHuang Rui goto out; 821c8781f56SHuang Rui } 822c8781f56SHuang Rui 823c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 824c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 825c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 826c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 827c8781f56SHuang Rui 828c8781f56SHuang Rui out: 829c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 830aaa36a97SAlex Deucher } 831aaa36a97SAlex Deucher 832a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 83388a907d6STom St Denis .name = "uvd_v5_0", 834aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 835aaa36a97SAlex Deucher .late_init = NULL, 836aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 837aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 838aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 839aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 840aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 841aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 842aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 843aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 844aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 845aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 846aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 847c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 848aaa36a97SAlex Deucher }; 849aaa36a97SAlex Deucher 850aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 85121cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 85279887142SChristian König .align_mask = 0xf, 853536fbf94SKen Wang .support_64bit_ptrs = false, 854aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 855aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 856aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 857aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 858e12f3d7aSChristian König .emit_frame_size = 859e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 860e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 861aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 862aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 863aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8648de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 8650232e306SLeo Liu .insert_nop = uvd_v5_0_ring_insert_nop, 8669e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 867c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 868c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 869aaa36a97SAlex Deucher }; 870aaa36a97SAlex Deucher 871aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 872aaa36a97SAlex Deucher { 8732bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 874aaa36a97SAlex Deucher } 875aaa36a97SAlex Deucher 876aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 877aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 878aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 879aaa36a97SAlex Deucher }; 880aaa36a97SAlex Deucher 881aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 882aaa36a97SAlex Deucher { 8832bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 8842bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 885aaa36a97SAlex Deucher } 886a1255107SAlex Deucher 887a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 888a1255107SAlex Deucher { 889a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 890a1255107SAlex Deucher .major = 5, 891a1255107SAlex Deucher .minor = 0, 892a1255107SAlex Deucher .rev = 0, 893a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 894a1255107SAlex Deucher }; 895