1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34be3ecca7STom St Denis #include "vi.h" 35aaa36a97SAlex Deucher 36aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 37aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 38aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 39aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 40aaa36a97SAlex Deucher 41aaa36a97SAlex Deucher /** 42aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 43aaa36a97SAlex Deucher * 44aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 45aaa36a97SAlex Deucher * 46aaa36a97SAlex Deucher * Returns the current hardware read pointer 47aaa36a97SAlex Deucher */ 48aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 49aaa36a97SAlex Deucher { 50aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 51aaa36a97SAlex Deucher 52aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 53aaa36a97SAlex Deucher } 54aaa36a97SAlex Deucher 55aaa36a97SAlex Deucher /** 56aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 57aaa36a97SAlex Deucher * 58aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 59aaa36a97SAlex Deucher * 60aaa36a97SAlex Deucher * Returns the current hardware write pointer 61aaa36a97SAlex Deucher */ 62aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 63aaa36a97SAlex Deucher { 64aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 65aaa36a97SAlex Deucher 66aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 67aaa36a97SAlex Deucher } 68aaa36a97SAlex Deucher 69aaa36a97SAlex Deucher /** 70aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 71aaa36a97SAlex Deucher * 72aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 73aaa36a97SAlex Deucher * 74aaa36a97SAlex Deucher * Commits the write pointer to the hardware 75aaa36a97SAlex Deucher */ 76aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 77aaa36a97SAlex Deucher { 78aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 79aaa36a97SAlex Deucher 80aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 81aaa36a97SAlex Deucher } 82aaa36a97SAlex Deucher 835fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 84aaa36a97SAlex Deucher { 855fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 865fc3aeebSyanyang1 87aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 88aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 89aaa36a97SAlex Deucher 90aaa36a97SAlex Deucher return 0; 91aaa36a97SAlex Deucher } 92aaa36a97SAlex Deucher 935fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 94aaa36a97SAlex Deucher { 95aaa36a97SAlex Deucher struct amdgpu_ring *ring; 965fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 97aaa36a97SAlex Deucher int r; 98aaa36a97SAlex Deucher 99aaa36a97SAlex Deucher /* UVD TRAP */ 100aaa36a97SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 101aaa36a97SAlex Deucher if (r) 102aaa36a97SAlex Deucher return r; 103aaa36a97SAlex Deucher 104aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 105aaa36a97SAlex Deucher if (r) 106aaa36a97SAlex Deucher return r; 107aaa36a97SAlex Deucher 108aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 109aaa36a97SAlex Deucher if (r) 110aaa36a97SAlex Deucher return r; 111aaa36a97SAlex Deucher 112aaa36a97SAlex Deucher ring = &adev->uvd.ring; 113aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 114aaa36a97SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 115aaa36a97SAlex Deucher &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 116aaa36a97SAlex Deucher 117aaa36a97SAlex Deucher return r; 118aaa36a97SAlex Deucher } 119aaa36a97SAlex Deucher 1205fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 121aaa36a97SAlex Deucher { 122aaa36a97SAlex Deucher int r; 1235fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 124aaa36a97SAlex Deucher 125aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 126aaa36a97SAlex Deucher if (r) 127aaa36a97SAlex Deucher return r; 128aaa36a97SAlex Deucher 129aaa36a97SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 130aaa36a97SAlex Deucher if (r) 131aaa36a97SAlex Deucher return r; 132aaa36a97SAlex Deucher 133aaa36a97SAlex Deucher return r; 134aaa36a97SAlex Deucher } 135aaa36a97SAlex Deucher 136aaa36a97SAlex Deucher /** 137aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 138aaa36a97SAlex Deucher * 139aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 140aaa36a97SAlex Deucher * 141aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 142aaa36a97SAlex Deucher */ 1435fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 144aaa36a97SAlex Deucher { 1455fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 146aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 147aaa36a97SAlex Deucher uint32_t tmp; 148aaa36a97SAlex Deucher int r; 149aaa36a97SAlex Deucher 150aaa36a97SAlex Deucher /* raise clocks while booting up the VCPU */ 151aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 152aaa36a97SAlex Deucher 153aaa36a97SAlex Deucher r = uvd_v5_0_start(adev); 154aaa36a97SAlex Deucher if (r) 155aaa36a97SAlex Deucher goto done; 156aaa36a97SAlex Deucher 157aaa36a97SAlex Deucher ring->ready = true; 158aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 159aaa36a97SAlex Deucher if (r) { 160aaa36a97SAlex Deucher ring->ready = false; 161aaa36a97SAlex Deucher goto done; 162aaa36a97SAlex Deucher } 163aaa36a97SAlex Deucher 164a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 165aaa36a97SAlex Deucher if (r) { 166aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 167aaa36a97SAlex Deucher goto done; 168aaa36a97SAlex Deucher } 169aaa36a97SAlex Deucher 170aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 171aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 172aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 173aaa36a97SAlex Deucher 174aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 176aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 177aaa36a97SAlex Deucher 178aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 180aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 181aaa36a97SAlex Deucher 182aaa36a97SAlex Deucher /* Clear timeout status bits */ 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 184aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 185aaa36a97SAlex Deucher 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 187aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 188aaa36a97SAlex Deucher 189a27de35cSChristian König amdgpu_ring_commit(ring); 190aaa36a97SAlex Deucher 191aaa36a97SAlex Deucher done: 192aaa36a97SAlex Deucher /* lower clocks again */ 193aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 194aaa36a97SAlex Deucher 195aaa36a97SAlex Deucher if (!r) 196aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher return r; 199aaa36a97SAlex Deucher } 200aaa36a97SAlex Deucher 201aaa36a97SAlex Deucher /** 202aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 203aaa36a97SAlex Deucher * 204aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 205aaa36a97SAlex Deucher * 206aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 207aaa36a97SAlex Deucher */ 2085fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 209aaa36a97SAlex Deucher { 2105fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 211aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 212aaa36a97SAlex Deucher 213aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 214aaa36a97SAlex Deucher ring->ready = false; 215aaa36a97SAlex Deucher 216aaa36a97SAlex Deucher return 0; 217aaa36a97SAlex Deucher } 218aaa36a97SAlex Deucher 2195fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 220aaa36a97SAlex Deucher { 221aaa36a97SAlex Deucher int r; 2225fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 223aaa36a97SAlex Deucher 2243f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 225aaa36a97SAlex Deucher if (r) 226aaa36a97SAlex Deucher return r; 227aaa36a97SAlex Deucher 2283f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 229aaa36a97SAlex Deucher if (r) 230aaa36a97SAlex Deucher return r; 231aaa36a97SAlex Deucher 232aaa36a97SAlex Deucher return r; 233aaa36a97SAlex Deucher } 234aaa36a97SAlex Deucher 2355fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 236aaa36a97SAlex Deucher { 237aaa36a97SAlex Deucher int r; 2385fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 239aaa36a97SAlex Deucher 240aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 241aaa36a97SAlex Deucher if (r) 242aaa36a97SAlex Deucher return r; 243aaa36a97SAlex Deucher 244aaa36a97SAlex Deucher r = uvd_v5_0_hw_init(adev); 245aaa36a97SAlex Deucher if (r) 246aaa36a97SAlex Deucher return r; 247aaa36a97SAlex Deucher 248aaa36a97SAlex Deucher return r; 249aaa36a97SAlex Deucher } 250aaa36a97SAlex Deucher 251aaa36a97SAlex Deucher /** 252aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 253aaa36a97SAlex Deucher * 254aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 255aaa36a97SAlex Deucher * 256aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 257aaa36a97SAlex Deucher */ 258aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 259aaa36a97SAlex Deucher { 260aaa36a97SAlex Deucher uint64_t offset; 261aaa36a97SAlex Deucher uint32_t size; 262aaa36a97SAlex Deucher 263aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 264aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 265aaa36a97SAlex Deucher lower_32_bits(adev->uvd.gpu_addr)); 266aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 267aaa36a97SAlex Deucher upper_32_bits(adev->uvd.gpu_addr)); 268aaa36a97SAlex Deucher 269aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 270aaa36a97SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 271aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 272aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 273aaa36a97SAlex Deucher 274aaa36a97SAlex Deucher offset += size; 275aaa36a97SAlex Deucher size = AMDGPU_UVD_STACK_SIZE; 276aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 277aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 278aaa36a97SAlex Deucher 279aaa36a97SAlex Deucher offset += size; 280aaa36a97SAlex Deucher size = AMDGPU_UVD_HEAP_SIZE; 281aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 282aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 283549300ceSAlex Deucher 284549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 285549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 286549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 287aaa36a97SAlex Deucher } 288aaa36a97SAlex Deucher 289aaa36a97SAlex Deucher /** 290aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 291aaa36a97SAlex Deucher * 292aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 293aaa36a97SAlex Deucher * 294aaa36a97SAlex Deucher * Setup and start the UVD block 295aaa36a97SAlex Deucher */ 296aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 297aaa36a97SAlex Deucher { 298aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 299aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 300aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 301aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 302aaa36a97SAlex Deucher int i, j, r; 303aaa36a97SAlex Deucher 304aaa36a97SAlex Deucher /*disable DPG */ 305aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 306aaa36a97SAlex Deucher 307aaa36a97SAlex Deucher /* disable byte swapping */ 308aaa36a97SAlex Deucher lmi_swap_cntl = 0; 309aaa36a97SAlex Deucher mp_swap_cntl = 0; 310aaa36a97SAlex Deucher 311aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 312aaa36a97SAlex Deucher 313aaa36a97SAlex Deucher /* disable clock gating */ 314aaa36a97SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 315aaa36a97SAlex Deucher 316aaa36a97SAlex Deucher /* disable interupt */ 317aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 318aaa36a97SAlex Deucher 319aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 320aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 321aaa36a97SAlex Deucher mdelay(1); 322aaa36a97SAlex Deucher 323aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 324aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 325aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 326aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 327aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 328aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 329aaa36a97SAlex Deucher mdelay(5); 330aaa36a97SAlex Deucher 331aaa36a97SAlex Deucher /* take UVD block out of reset */ 332aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 333aaa36a97SAlex Deucher mdelay(5); 334aaa36a97SAlex Deucher 335aaa36a97SAlex Deucher /* initialize UVD memory controller */ 336aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 337aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 338aaa36a97SAlex Deucher 339aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 340aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 341aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 342aaa36a97SAlex Deucher mp_swap_cntl = 0; 343aaa36a97SAlex Deucher #endif 344aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 345aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 346aaa36a97SAlex Deucher 347aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 348aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 349aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 350aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 351aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 352aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 353aaa36a97SAlex Deucher 354aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 355aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 356aaa36a97SAlex Deucher mdelay(5); 357aaa36a97SAlex Deucher 358aaa36a97SAlex Deucher /* enable VCPU clock */ 359aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 360aaa36a97SAlex Deucher 361aaa36a97SAlex Deucher /* enable UMC */ 362aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 363aaa36a97SAlex Deucher 364aaa36a97SAlex Deucher /* boot up the VCPU */ 365aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 366aaa36a97SAlex Deucher mdelay(10); 367aaa36a97SAlex Deucher 368aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 369aaa36a97SAlex Deucher uint32_t status; 370aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 371aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 372aaa36a97SAlex Deucher if (status & 2) 373aaa36a97SAlex Deucher break; 374aaa36a97SAlex Deucher mdelay(10); 375aaa36a97SAlex Deucher } 376aaa36a97SAlex Deucher r = 0; 377aaa36a97SAlex Deucher if (status & 2) 378aaa36a97SAlex Deucher break; 379aaa36a97SAlex Deucher 380aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 381aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 382aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 383aaa36a97SAlex Deucher mdelay(10); 384aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 385aaa36a97SAlex Deucher mdelay(10); 386aaa36a97SAlex Deucher r = -1; 387aaa36a97SAlex Deucher } 388aaa36a97SAlex Deucher 389aaa36a97SAlex Deucher if (r) { 390aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 391aaa36a97SAlex Deucher return r; 392aaa36a97SAlex Deucher } 393aaa36a97SAlex Deucher /* enable master interrupt */ 394aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 395aaa36a97SAlex Deucher 396aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 397aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 398aaa36a97SAlex Deucher 399aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 400aaa36a97SAlex Deucher tmp = 0; 401aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 402aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 403aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 404aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 405aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 406aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 407aaa36a97SAlex Deucher /* force RBC into idle state */ 408aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 409aaa36a97SAlex Deucher 410aaa36a97SAlex Deucher /* set the write pointer delay */ 411aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 412aaa36a97SAlex Deucher 413aaa36a97SAlex Deucher /* set the wb address */ 414aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 415aaa36a97SAlex Deucher 416aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 417aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 418aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 419aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 420aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 421aaa36a97SAlex Deucher 422aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 423aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 424aaa36a97SAlex Deucher 425aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 426aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 427aaa36a97SAlex Deucher 428aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 429aaa36a97SAlex Deucher 430aaa36a97SAlex Deucher return 0; 431aaa36a97SAlex Deucher } 432aaa36a97SAlex Deucher 433aaa36a97SAlex Deucher /** 434aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 435aaa36a97SAlex Deucher * 436aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 437aaa36a97SAlex Deucher * 438aaa36a97SAlex Deucher * stop the UVD block 439aaa36a97SAlex Deucher */ 440aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 441aaa36a97SAlex Deucher { 442aaa36a97SAlex Deucher /* force RBC into idle state */ 443aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 444aaa36a97SAlex Deucher 445aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 446aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 447aaa36a97SAlex Deucher mdelay(1); 448aaa36a97SAlex Deucher 449aaa36a97SAlex Deucher /* put VCPU into reset */ 450aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 451aaa36a97SAlex Deucher mdelay(5); 452aaa36a97SAlex Deucher 453aaa36a97SAlex Deucher /* disable VCPU clock */ 454aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 455aaa36a97SAlex Deucher 456aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 457aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 458aaa36a97SAlex Deucher } 459aaa36a97SAlex Deucher 460aaa36a97SAlex Deucher /** 461aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 462aaa36a97SAlex Deucher * 463aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 464aaa36a97SAlex Deucher * @fence: fence to emit 465aaa36a97SAlex Deucher * 466aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 467aaa36a97SAlex Deucher */ 468aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 469890ee23fSChunming Zhou unsigned flags) 470aaa36a97SAlex Deucher { 471890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 472aaa36a97SAlex Deucher 473aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 480aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 481aaa36a97SAlex Deucher 482aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 483aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 484aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 485aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 486aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 487aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 488aaa36a97SAlex Deucher } 489aaa36a97SAlex Deucher 490aaa36a97SAlex Deucher /** 491aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 492aaa36a97SAlex Deucher * 493aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 494aaa36a97SAlex Deucher * 495aaa36a97SAlex Deucher * Test if we can successfully write to the context register 496aaa36a97SAlex Deucher */ 497aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 498aaa36a97SAlex Deucher { 499aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 500aaa36a97SAlex Deucher uint32_t tmp = 0; 501aaa36a97SAlex Deucher unsigned i; 502aaa36a97SAlex Deucher int r; 503aaa36a97SAlex Deucher 504aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 505a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 506aaa36a97SAlex Deucher if (r) { 507aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 508aaa36a97SAlex Deucher ring->idx, r); 509aaa36a97SAlex Deucher return r; 510aaa36a97SAlex Deucher } 511aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 512aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 513a27de35cSChristian König amdgpu_ring_commit(ring); 514aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 515aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 516aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 517aaa36a97SAlex Deucher break; 518aaa36a97SAlex Deucher DRM_UDELAY(1); 519aaa36a97SAlex Deucher } 520aaa36a97SAlex Deucher 521aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 522aaa36a97SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 523aaa36a97SAlex Deucher ring->idx, i); 524aaa36a97SAlex Deucher } else { 525aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 526aaa36a97SAlex Deucher ring->idx, tmp); 527aaa36a97SAlex Deucher r = -EINVAL; 528aaa36a97SAlex Deucher } 529aaa36a97SAlex Deucher return r; 530aaa36a97SAlex Deucher } 531aaa36a97SAlex Deucher 532aaa36a97SAlex Deucher /** 533aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 534aaa36a97SAlex Deucher * 535aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 536aaa36a97SAlex Deucher * @ib: indirect buffer to execute 537aaa36a97SAlex Deucher * 538aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 539aaa36a97SAlex Deucher */ 540aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 541aaa36a97SAlex Deucher struct amdgpu_ib *ib) 542aaa36a97SAlex Deucher { 543aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 544aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 545aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 546aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 547aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 548aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 549aaa36a97SAlex Deucher } 550aaa36a97SAlex Deucher 551aaa36a97SAlex Deucher /** 552aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ib - test ib execution 553aaa36a97SAlex Deucher * 554aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 555aaa36a97SAlex Deucher * 556aaa36a97SAlex Deucher * Test if we can successfully execute an IB 557aaa36a97SAlex Deucher */ 558aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring) 559aaa36a97SAlex Deucher { 560aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 5610e3f154aSChunming Zhou struct fence *fence = NULL; 562aaa36a97SAlex Deucher int r; 563aaa36a97SAlex Deucher 564aaa36a97SAlex Deucher r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 565aaa36a97SAlex Deucher if (r) { 566aaa36a97SAlex Deucher DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 567aaa36a97SAlex Deucher return r; 568aaa36a97SAlex Deucher } 569aaa36a97SAlex Deucher 570aaa36a97SAlex Deucher r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 571aaa36a97SAlex Deucher if (r) { 572aaa36a97SAlex Deucher DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 573aaa36a97SAlex Deucher goto error; 574aaa36a97SAlex Deucher } 575aaa36a97SAlex Deucher 576d7af97dbSChristian König r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 577aaa36a97SAlex Deucher if (r) { 578aaa36a97SAlex Deucher DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 579aaa36a97SAlex Deucher goto error; 580aaa36a97SAlex Deucher } 581aaa36a97SAlex Deucher 5820e3f154aSChunming Zhou r = fence_wait(fence, false); 583aaa36a97SAlex Deucher if (r) { 584aaa36a97SAlex Deucher DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 585aaa36a97SAlex Deucher goto error; 586aaa36a97SAlex Deucher } 587aaa36a97SAlex Deucher DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 588aaa36a97SAlex Deucher error: 5890e3f154aSChunming Zhou fence_put(fence); 590aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 591aaa36a97SAlex Deucher return r; 592aaa36a97SAlex Deucher } 593aaa36a97SAlex Deucher 5945fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 595aaa36a97SAlex Deucher { 5965fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5975fc3aeebSyanyang1 598aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 599aaa36a97SAlex Deucher } 600aaa36a97SAlex Deucher 6015fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 602aaa36a97SAlex Deucher { 603aaa36a97SAlex Deucher unsigned i; 6045fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 605aaa36a97SAlex Deucher 606aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 607aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 608aaa36a97SAlex Deucher return 0; 609aaa36a97SAlex Deucher } 610aaa36a97SAlex Deucher return -ETIMEDOUT; 611aaa36a97SAlex Deucher } 612aaa36a97SAlex Deucher 6135fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 614aaa36a97SAlex Deucher { 6155fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6165fc3aeebSyanyang1 617aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 618aaa36a97SAlex Deucher 619aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 620aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 621aaa36a97SAlex Deucher mdelay(5); 622aaa36a97SAlex Deucher 623aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 624aaa36a97SAlex Deucher } 625aaa36a97SAlex Deucher 6265fc3aeebSyanyang1 static void uvd_v5_0_print_status(void *handle) 627aaa36a97SAlex Deucher { 6285fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 629aaa36a97SAlex Deucher dev_info(adev->dev, "UVD 5.0 registers\n"); 630aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 631aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_ADDR_LOW)); 632aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 633aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_ADDR_HIGH)); 634aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 635aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_CMD)); 636aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 637aaa36a97SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_CMD)); 638aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 639aaa36a97SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA0)); 640aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 641aaa36a97SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA1)); 642aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 643aaa36a97SAlex Deucher RREG32(mmUVD_ENGINE_CNTL)); 644aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 645aaa36a97SAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 646aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 647aaa36a97SAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 648aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 649aaa36a97SAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 650aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 651aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_CNTL)); 652aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 653aaa36a97SAlex Deucher RREG32(mmUVD_LMI_EXT40_ADDR)); 654aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 655aaa36a97SAlex Deucher RREG32(mmUVD_CTX_INDEX)); 656aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 657aaa36a97SAlex Deucher RREG32(mmUVD_CTX_DATA)); 658aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 659aaa36a97SAlex Deucher RREG32(mmUVD_CGC_GATE)); 660aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 661aaa36a97SAlex Deucher RREG32(mmUVD_CGC_CTRL)); 662aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 663aaa36a97SAlex Deucher RREG32(mmUVD_LMI_CTRL2)); 664aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 665aaa36a97SAlex Deucher RREG32(mmUVD_MASTINT_EN)); 666aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 667aaa36a97SAlex Deucher RREG32(mmUVD_LMI_ADDR_EXT)); 668aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 669aaa36a97SAlex Deucher RREG32(mmUVD_LMI_CTRL)); 670aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 671aaa36a97SAlex Deucher RREG32(mmUVD_LMI_SWAP_CNTL)); 672aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 673aaa36a97SAlex Deucher RREG32(mmUVD_MP_SWAP_CNTL)); 674aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 675aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA0)); 676aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 677aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA1)); 678aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 679aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB0)); 680aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 681aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB1)); 682aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 683aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUX)); 684aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 685aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_ALU)); 686aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 687aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 688aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 689aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE0)); 690aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 691aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 692aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 693aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE1)); 694aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 695aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 696aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 697aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE2)); 698aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 699aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CNTL)); 700aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 701aaa36a97SAlex Deucher RREG32(mmUVD_SOFT_RESET)); 702aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n", 703aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)); 704aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n", 705aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)); 706aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 707aaa36a97SAlex Deucher RREG32(mmUVD_RBC_IB_SIZE)); 708aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n", 709aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)); 710aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n", 711aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)); 712aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 713aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_RPTR)); 714aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 715aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR)); 716aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 717aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 718aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 719aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_CNTL)); 720aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 721aaa36a97SAlex Deucher RREG32(mmUVD_STATUS)); 722aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 723aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 724aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 725aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 726aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 727aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 728aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 729aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 730aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 731aaa36a97SAlex Deucher RREG32(mmUVD_CONTEXT_ID)); 732549300ceSAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 733549300ceSAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 734549300ceSAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 735549300ceSAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 736549300ceSAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 737549300ceSAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 738aaa36a97SAlex Deucher } 739aaa36a97SAlex Deucher 740aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 741aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 742aaa36a97SAlex Deucher unsigned type, 743aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 744aaa36a97SAlex Deucher { 745aaa36a97SAlex Deucher // TODO 746aaa36a97SAlex Deucher return 0; 747aaa36a97SAlex Deucher } 748aaa36a97SAlex Deucher 749aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 750aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 751aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 752aaa36a97SAlex Deucher { 753aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 754aaa36a97SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 755aaa36a97SAlex Deucher return 0; 756aaa36a97SAlex Deucher } 757aaa36a97SAlex Deucher 758be3ecca7STom St Denis static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 759be3ecca7STom St Denis { 760be3ecca7STom St Denis uint32_t data, data1, data2, suvd_flags; 761be3ecca7STom St Denis 762be3ecca7STom St Denis data = RREG32(mmUVD_CGC_CTRL); 763be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 764be3ecca7STom St Denis data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 765be3ecca7STom St Denis 766be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 767be3ecca7STom St Denis UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 768be3ecca7STom St Denis 769be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 770be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 771be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 772be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 773be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 774be3ecca7STom St Denis 775be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 776be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 777be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 778be3ecca7STom St Denis 779be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 780be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 781be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 782be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 783be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 784be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 785be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 786be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 787be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 788be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 789be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 790be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 791be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 792be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 793be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 794be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 795be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 796be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 797be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 798be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 799be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 800be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 801be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 802be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 803be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 804be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 805be3ecca7STom St Denis data1 |= suvd_flags; 806be3ecca7STom St Denis 807be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 808be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, 0); 809be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 810be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 811be3ecca7STom St Denis } 812be3ecca7STom St Denis 813be3ecca7STom St Denis #if 0 814be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 815be3ecca7STom St Denis { 816be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 817be3ecca7STom St Denis 818be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 819be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 820be3ecca7STom St Denis 821be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 822be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 823be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 824be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 825be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 826be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 827be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 828be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 829be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 830be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 831be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 832be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 833be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 834be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 835be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 836be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 837be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 838be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 839be3ecca7STom St Denis 840be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 841be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 842be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 843be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 844be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 845be3ecca7STom St Denis 846be3ecca7STom St Denis data |= cgc_flags; 847be3ecca7STom St Denis data1 |= suvd_flags; 848be3ecca7STom St Denis 849be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 850be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 851be3ecca7STom St Denis } 852be3ecca7STom St Denis #endif 853be3ecca7STom St Denis 8545fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 8555fc3aeebSyanyang1 enum amd_clockgating_state state) 856aaa36a97SAlex Deucher { 85735e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 858be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 859be3ecca7STom St Denis static int curstate = -1; 86035e5912dSAlex Deucher 861e3b04bc7SAlex Deucher if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 86235e5912dSAlex Deucher return 0; 86335e5912dSAlex Deucher 864be3ecca7STom St Denis if (curstate == state) 865be3ecca7STom St Denis return 0; 866be3ecca7STom St Denis 867be3ecca7STom St Denis curstate = state; 868be3ecca7STom St Denis if (enable) { 869be3ecca7STom St Denis /* disable HW gating and enable Sw gating */ 870be3ecca7STom St Denis uvd_v5_0_set_sw_clock_gating(adev); 871be3ecca7STom St Denis } else { 872be3ecca7STom St Denis /* wait for STATUS to clear */ 873be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 874be3ecca7STom St Denis return -EBUSY; 875be3ecca7STom St Denis 876be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 877be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 878be3ecca7STom St Denis } 879be3ecca7STom St Denis 880aaa36a97SAlex Deucher return 0; 881aaa36a97SAlex Deucher } 882aaa36a97SAlex Deucher 8835fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 8845fc3aeebSyanyang1 enum amd_powergating_state state) 885aaa36a97SAlex Deucher { 886aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 887aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 888aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 889aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 890aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 891aaa36a97SAlex Deucher * the smc and the hw blocks 892aaa36a97SAlex Deucher */ 8935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8945fc3aeebSyanyang1 895e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 896b6df77fcSAlex Deucher return 0; 897b6df77fcSAlex Deucher 8985fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 899aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 900aaa36a97SAlex Deucher return 0; 901aaa36a97SAlex Deucher } else { 902aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 903aaa36a97SAlex Deucher } 904aaa36a97SAlex Deucher } 905aaa36a97SAlex Deucher 9065fc3aeebSyanyang1 const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 907aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 908aaa36a97SAlex Deucher .late_init = NULL, 909aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 910aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 911aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 912aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 913aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 914aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 915aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 916aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 917aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 918aaa36a97SAlex Deucher .print_status = uvd_v5_0_print_status, 919aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 920aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 921aaa36a97SAlex Deucher }; 922aaa36a97SAlex Deucher 923aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 924aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 925aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 926aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 927aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 928aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 929aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 930aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 931aaa36a97SAlex Deucher .test_ib = uvd_v5_0_ring_test_ib, 932edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 9339e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 934aaa36a97SAlex Deucher }; 935aaa36a97SAlex Deucher 936aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 937aaa36a97SAlex Deucher { 938aaa36a97SAlex Deucher adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; 939aaa36a97SAlex Deucher } 940aaa36a97SAlex Deucher 941aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 942aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 943aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 944aaa36a97SAlex Deucher }; 945aaa36a97SAlex Deucher 946aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 947aaa36a97SAlex Deucher { 948aaa36a97SAlex Deucher adev->uvd.irq.num_types = 1; 949aaa36a97SAlex Deucher adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 950aaa36a97SAlex Deucher } 951