1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 35be3ecca7STom St Denis #include "vi.h" 364be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 38aaa36a97SAlex Deucher 39aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 40aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 41aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 43809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 44809a6a62SRex Zhu enum amd_clockgating_state state); 45809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 46809a6a62SRex Zhu bool enable); 47aaa36a97SAlex Deucher /** 48aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 49aaa36a97SAlex Deucher * 50aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 51aaa36a97SAlex Deucher * 52aaa36a97SAlex Deucher * Returns the current hardware read pointer 53aaa36a97SAlex Deucher */ 54536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 55aaa36a97SAlex Deucher { 56aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 57aaa36a97SAlex Deucher 58aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 59aaa36a97SAlex Deucher } 60aaa36a97SAlex Deucher 61aaa36a97SAlex Deucher /** 62aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 63aaa36a97SAlex Deucher * 64aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 65aaa36a97SAlex Deucher * 66aaa36a97SAlex Deucher * Returns the current hardware write pointer 67aaa36a97SAlex Deucher */ 68536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 69aaa36a97SAlex Deucher { 70aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 71aaa36a97SAlex Deucher 72aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 73aaa36a97SAlex Deucher } 74aaa36a97SAlex Deucher 75aaa36a97SAlex Deucher /** 76aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 77aaa36a97SAlex Deucher * 78aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 79aaa36a97SAlex Deucher * 80aaa36a97SAlex Deucher * Commits the write pointer to the hardware 81aaa36a97SAlex Deucher */ 82aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 83aaa36a97SAlex Deucher { 84aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 85aaa36a97SAlex Deucher 86536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 87aaa36a97SAlex Deucher } 88aaa36a97SAlex Deucher 895fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 90aaa36a97SAlex Deucher { 915fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 925fc3aeebSyanyang1 93aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 94aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 95aaa36a97SAlex Deucher 96aaa36a97SAlex Deucher return 0; 97aaa36a97SAlex Deucher } 98aaa36a97SAlex Deucher 995fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 100aaa36a97SAlex Deucher { 101aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1025fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 103aaa36a97SAlex Deucher int r; 104aaa36a97SAlex Deucher 105aaa36a97SAlex Deucher /* UVD TRAP */ 106d766e6a3SAlex Deucher r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq); 107aaa36a97SAlex Deucher if (r) 108aaa36a97SAlex Deucher return r; 109aaa36a97SAlex Deucher 110aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 111aaa36a97SAlex Deucher if (r) 112aaa36a97SAlex Deucher return r; 113aaa36a97SAlex Deucher 114aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 115aaa36a97SAlex Deucher if (r) 116aaa36a97SAlex Deucher return r; 117aaa36a97SAlex Deucher 118aaa36a97SAlex Deucher ring = &adev->uvd.ring; 119aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 12079887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 121aaa36a97SAlex Deucher 122aaa36a97SAlex Deucher return r; 123aaa36a97SAlex Deucher } 124aaa36a97SAlex Deucher 1255fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 126aaa36a97SAlex Deucher { 127aaa36a97SAlex Deucher int r; 1285fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 129aaa36a97SAlex Deucher 130aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 131aaa36a97SAlex Deucher if (r) 132aaa36a97SAlex Deucher return r; 133aaa36a97SAlex Deucher 13450237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 135aaa36a97SAlex Deucher } 136aaa36a97SAlex Deucher 137aaa36a97SAlex Deucher /** 138aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 139aaa36a97SAlex Deucher * 140aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 141aaa36a97SAlex Deucher * 142aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 143aaa36a97SAlex Deucher */ 1445fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 145aaa36a97SAlex Deucher { 1465fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 147aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 148aaa36a97SAlex Deucher uint32_t tmp; 149aaa36a97SAlex Deucher int r; 150aaa36a97SAlex Deucher 151e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 152e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 153e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 154aaa36a97SAlex Deucher 155aaa36a97SAlex Deucher ring->ready = true; 156aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 157aaa36a97SAlex Deucher if (r) { 158aaa36a97SAlex Deucher ring->ready = false; 159aaa36a97SAlex Deucher goto done; 160aaa36a97SAlex Deucher } 161aaa36a97SAlex Deucher 162a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 163aaa36a97SAlex Deucher if (r) { 164aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 165aaa36a97SAlex Deucher goto done; 166aaa36a97SAlex Deucher } 167aaa36a97SAlex Deucher 168aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 169aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 170aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 171aaa36a97SAlex Deucher 172aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 173aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 175aaa36a97SAlex Deucher 176aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 177aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 179aaa36a97SAlex Deucher 180aaa36a97SAlex Deucher /* Clear timeout status bits */ 181aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 183aaa36a97SAlex Deucher 184aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 185aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 186aaa36a97SAlex Deucher 187a27de35cSChristian König amdgpu_ring_commit(ring); 188e3e672e6SRex Zhu 189aaa36a97SAlex Deucher done: 190aaa36a97SAlex Deucher if (!r) 191aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 192aaa36a97SAlex Deucher 193aaa36a97SAlex Deucher return r; 194e3e672e6SRex Zhu 195aaa36a97SAlex Deucher } 196aaa36a97SAlex Deucher 197aaa36a97SAlex Deucher /** 198aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 199aaa36a97SAlex Deucher * 200aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 201aaa36a97SAlex Deucher * 202aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 203aaa36a97SAlex Deucher */ 2045fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 205aaa36a97SAlex Deucher { 2065fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 207aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 208aaa36a97SAlex Deucher 209e3e672e6SRex Zhu if (RREG32(mmUVD_STATUS) != 0) 210aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 211e3e672e6SRex Zhu 212aaa36a97SAlex Deucher ring->ready = false; 213aaa36a97SAlex Deucher 214aaa36a97SAlex Deucher return 0; 215aaa36a97SAlex Deucher } 216aaa36a97SAlex Deucher 2175fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 218aaa36a97SAlex Deucher { 219aaa36a97SAlex Deucher int r; 2205fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 221aaa36a97SAlex Deucher 2223f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 223aaa36a97SAlex Deucher if (r) 224aaa36a97SAlex Deucher return r; 225809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 226aaa36a97SAlex Deucher 22750237287SRex Zhu return amdgpu_uvd_suspend(adev); 228aaa36a97SAlex Deucher } 229aaa36a97SAlex Deucher 2305fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 231aaa36a97SAlex Deucher { 232aaa36a97SAlex Deucher int r; 2335fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 234aaa36a97SAlex Deucher 235aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 236aaa36a97SAlex Deucher if (r) 237aaa36a97SAlex Deucher return r; 238aaa36a97SAlex Deucher 23950237287SRex Zhu return uvd_v5_0_hw_init(adev); 240aaa36a97SAlex Deucher } 241aaa36a97SAlex Deucher 242aaa36a97SAlex Deucher /** 243aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 244aaa36a97SAlex Deucher * 245aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 246aaa36a97SAlex Deucher * 247aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 248aaa36a97SAlex Deucher */ 249aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 250aaa36a97SAlex Deucher { 251aaa36a97SAlex Deucher uint64_t offset; 252aaa36a97SAlex Deucher uint32_t size; 253aaa36a97SAlex Deucher 254aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 255aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 256aaa36a97SAlex Deucher lower_32_bits(adev->uvd.gpu_addr)); 257aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 258aaa36a97SAlex Deucher upper_32_bits(adev->uvd.gpu_addr)); 259aaa36a97SAlex Deucher 260aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 261aaa36a97SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 262aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 263aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 264aaa36a97SAlex Deucher 265aaa36a97SAlex Deucher offset += size; 266c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 267aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 268aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 269aaa36a97SAlex Deucher 270aaa36a97SAlex Deucher offset += size; 271c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 272c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 273aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 274aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 275549300ceSAlex Deucher 276549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 277549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 278549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 279aaa36a97SAlex Deucher } 280aaa36a97SAlex Deucher 281aaa36a97SAlex Deucher /** 282aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 283aaa36a97SAlex Deucher * 284aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 285aaa36a97SAlex Deucher * 286aaa36a97SAlex Deucher * Setup and start the UVD block 287aaa36a97SAlex Deucher */ 288aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 289aaa36a97SAlex Deucher { 290aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 291aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 292aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 293aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 294aaa36a97SAlex Deucher int i, j, r; 295aaa36a97SAlex Deucher 296aaa36a97SAlex Deucher /*disable DPG */ 297aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 298aaa36a97SAlex Deucher 299aaa36a97SAlex Deucher /* disable byte swapping */ 300aaa36a97SAlex Deucher lmi_swap_cntl = 0; 301aaa36a97SAlex Deucher mp_swap_cntl = 0; 302aaa36a97SAlex Deucher 303aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 304aaa36a97SAlex Deucher 305aaa36a97SAlex Deucher /* disable interupt */ 306aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 307aaa36a97SAlex Deucher 308aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 309aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 310aaa36a97SAlex Deucher mdelay(1); 311aaa36a97SAlex Deucher 312aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 313aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 314aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 315aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 316aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 317aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 318aaa36a97SAlex Deucher mdelay(5); 319aaa36a97SAlex Deucher 320aaa36a97SAlex Deucher /* take UVD block out of reset */ 321aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 322aaa36a97SAlex Deucher mdelay(5); 323aaa36a97SAlex Deucher 324aaa36a97SAlex Deucher /* initialize UVD memory controller */ 325aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 326aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 327aaa36a97SAlex Deucher 328aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 329aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 330aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 331aaa36a97SAlex Deucher mp_swap_cntl = 0; 332aaa36a97SAlex Deucher #endif 333aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 334aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 335aaa36a97SAlex Deucher 336aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 337aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 338aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 339aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 340aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 341aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 342aaa36a97SAlex Deucher 343aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 344aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 345aaa36a97SAlex Deucher mdelay(5); 346aaa36a97SAlex Deucher 347aaa36a97SAlex Deucher /* enable VCPU clock */ 348aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 349aaa36a97SAlex Deucher 350aaa36a97SAlex Deucher /* enable UMC */ 351aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 352aaa36a97SAlex Deucher 353aaa36a97SAlex Deucher /* boot up the VCPU */ 354aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 355aaa36a97SAlex Deucher mdelay(10); 356aaa36a97SAlex Deucher 357aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 358aaa36a97SAlex Deucher uint32_t status; 359aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 360aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 361aaa36a97SAlex Deucher if (status & 2) 362aaa36a97SAlex Deucher break; 363aaa36a97SAlex Deucher mdelay(10); 364aaa36a97SAlex Deucher } 365aaa36a97SAlex Deucher r = 0; 366aaa36a97SAlex Deucher if (status & 2) 367aaa36a97SAlex Deucher break; 368aaa36a97SAlex Deucher 369aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 370aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 371aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 372aaa36a97SAlex Deucher mdelay(10); 373aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 374aaa36a97SAlex Deucher mdelay(10); 375aaa36a97SAlex Deucher r = -1; 376aaa36a97SAlex Deucher } 377aaa36a97SAlex Deucher 378aaa36a97SAlex Deucher if (r) { 379aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 380aaa36a97SAlex Deucher return r; 381aaa36a97SAlex Deucher } 382aaa36a97SAlex Deucher /* enable master interrupt */ 383aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 384aaa36a97SAlex Deucher 385aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 386aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 387aaa36a97SAlex Deucher 388aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 389aaa36a97SAlex Deucher tmp = 0; 390aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 391aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 392aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 393aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 394aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 395aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 396aaa36a97SAlex Deucher /* force RBC into idle state */ 397aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 398aaa36a97SAlex Deucher 399aaa36a97SAlex Deucher /* set the write pointer delay */ 400aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 401aaa36a97SAlex Deucher 402aaa36a97SAlex Deucher /* set the wb address */ 403aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 404aaa36a97SAlex Deucher 405aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 406aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 407aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 408aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 409aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 410aaa36a97SAlex Deucher 411aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 412aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 413aaa36a97SAlex Deucher 414aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 415536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 416aaa36a97SAlex Deucher 417aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 418aaa36a97SAlex Deucher 419aaa36a97SAlex Deucher return 0; 420aaa36a97SAlex Deucher } 421aaa36a97SAlex Deucher 422aaa36a97SAlex Deucher /** 423aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 424aaa36a97SAlex Deucher * 425aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 426aaa36a97SAlex Deucher * 427aaa36a97SAlex Deucher * stop the UVD block 428aaa36a97SAlex Deucher */ 429aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 430aaa36a97SAlex Deucher { 431aaa36a97SAlex Deucher /* force RBC into idle state */ 432aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 433aaa36a97SAlex Deucher 434aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 435aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 436aaa36a97SAlex Deucher mdelay(1); 437aaa36a97SAlex Deucher 438aaa36a97SAlex Deucher /* put VCPU into reset */ 439aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 440aaa36a97SAlex Deucher mdelay(5); 441aaa36a97SAlex Deucher 442aaa36a97SAlex Deucher /* disable VCPU clock */ 443aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 444aaa36a97SAlex Deucher 445aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 446aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 447e3e672e6SRex Zhu 448e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 449aaa36a97SAlex Deucher } 450aaa36a97SAlex Deucher 451aaa36a97SAlex Deucher /** 452aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 453aaa36a97SAlex Deucher * 454aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 455aaa36a97SAlex Deucher * @fence: fence to emit 456aaa36a97SAlex Deucher * 457aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 458aaa36a97SAlex Deucher */ 459aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 460890ee23fSChunming Zhou unsigned flags) 461aaa36a97SAlex Deucher { 462890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 463aaa36a97SAlex Deucher 464aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 465aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 466aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 467aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 468aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 469aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 470aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 471aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 472aaa36a97SAlex Deucher 473aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 479aaa36a97SAlex Deucher } 480aaa36a97SAlex Deucher 481aaa36a97SAlex Deucher /** 482d5b4e25dSChristian König * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush 483d5b4e25dSChristian König * 484d5b4e25dSChristian König * @ring: amdgpu_ring pointer 485d5b4e25dSChristian König * 486d5b4e25dSChristian König * Emits an hdp flush. 487d5b4e25dSChristian König */ 488d5b4e25dSChristian König static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 489d5b4e25dSChristian König { 490d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 491d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 492d5b4e25dSChristian König } 493d5b4e25dSChristian König 494d5b4e25dSChristian König /** 495d5b4e25dSChristian König * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate 496d5b4e25dSChristian König * 497d5b4e25dSChristian König * @ring: amdgpu_ring pointer 498d5b4e25dSChristian König * 499d5b4e25dSChristian König * Emits an hdp invalidate. 500d5b4e25dSChristian König */ 501d5b4e25dSChristian König static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 502d5b4e25dSChristian König { 503d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 504d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 505d5b4e25dSChristian König } 506d5b4e25dSChristian König 507d5b4e25dSChristian König /** 508aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 509aaa36a97SAlex Deucher * 510aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 511aaa36a97SAlex Deucher * 512aaa36a97SAlex Deucher * Test if we can successfully write to the context register 513aaa36a97SAlex Deucher */ 514aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 515aaa36a97SAlex Deucher { 516aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 517aaa36a97SAlex Deucher uint32_t tmp = 0; 518aaa36a97SAlex Deucher unsigned i; 519aaa36a97SAlex Deucher int r; 520aaa36a97SAlex Deucher 521aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 522a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 523aaa36a97SAlex Deucher if (r) { 524aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 525aaa36a97SAlex Deucher ring->idx, r); 526aaa36a97SAlex Deucher return r; 527aaa36a97SAlex Deucher } 528aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 529aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 530a27de35cSChristian König amdgpu_ring_commit(ring); 531aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 532aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 533aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 534aaa36a97SAlex Deucher break; 535aaa36a97SAlex Deucher DRM_UDELAY(1); 536aaa36a97SAlex Deucher } 537aaa36a97SAlex Deucher 538aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 5399953b72fSpding DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 540aaa36a97SAlex Deucher ring->idx, i); 541aaa36a97SAlex Deucher } else { 542aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 543aaa36a97SAlex Deucher ring->idx, tmp); 544aaa36a97SAlex Deucher r = -EINVAL; 545aaa36a97SAlex Deucher } 546aaa36a97SAlex Deucher return r; 547aaa36a97SAlex Deucher } 548aaa36a97SAlex Deucher 549aaa36a97SAlex Deucher /** 550aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 551aaa36a97SAlex Deucher * 552aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 553aaa36a97SAlex Deucher * @ib: indirect buffer to execute 554aaa36a97SAlex Deucher * 555aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 556aaa36a97SAlex Deucher */ 557aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 558d88bf583SChristian König struct amdgpu_ib *ib, 559d88bf583SChristian König unsigned vm_id, bool ctx_switch) 560aaa36a97SAlex Deucher { 561aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 562aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 563aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 564aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 565aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 566aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 567aaa36a97SAlex Deucher } 568aaa36a97SAlex Deucher 5695fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 570aaa36a97SAlex Deucher { 5715fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5725fc3aeebSyanyang1 573aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 574aaa36a97SAlex Deucher } 575aaa36a97SAlex Deucher 5765fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 577aaa36a97SAlex Deucher { 578aaa36a97SAlex Deucher unsigned i; 5795fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 580aaa36a97SAlex Deucher 581aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 582aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 583aaa36a97SAlex Deucher return 0; 584aaa36a97SAlex Deucher } 585aaa36a97SAlex Deucher return -ETIMEDOUT; 586aaa36a97SAlex Deucher } 587aaa36a97SAlex Deucher 5885fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 589aaa36a97SAlex Deucher { 5905fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5915fc3aeebSyanyang1 592aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 593aaa36a97SAlex Deucher 594aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 595aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 596aaa36a97SAlex Deucher mdelay(5); 597aaa36a97SAlex Deucher 598aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 599aaa36a97SAlex Deucher } 600aaa36a97SAlex Deucher 601aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 602aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 603aaa36a97SAlex Deucher unsigned type, 604aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 605aaa36a97SAlex Deucher { 606aaa36a97SAlex Deucher // TODO 607aaa36a97SAlex Deucher return 0; 608aaa36a97SAlex Deucher } 609aaa36a97SAlex Deucher 610aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 611aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 612aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 613aaa36a97SAlex Deucher { 614aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 615aaa36a97SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 616aaa36a97SAlex Deucher return 0; 617aaa36a97SAlex Deucher } 618aaa36a97SAlex Deucher 619809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 620be3ecca7STom St Denis { 621809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 622be3ecca7STom St Denis 623be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 624809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 625be3ecca7STom St Denis 626be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 627be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 628be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 629be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 630be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 631be3ecca7STom St Denis 632809a6a62SRex Zhu if (enable) { 633809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 634809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 635809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 636809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 637809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 638809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 639809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 640809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 641809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 642809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 643809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 644809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 645809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 646809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 647809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 648809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 649809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 650809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6513c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6523c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6533c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 654809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 655809a6a62SRex Zhu data1 |= suvd_flags; 656809a6a62SRex Zhu } else { 657809a6a62SRex Zhu data3 = 0; 658809a6a62SRex Zhu data1 = 0; 659809a6a62SRex Zhu } 660809a6a62SRex Zhu 661809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 662809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 663809a6a62SRex Zhu } 664809a6a62SRex Zhu 665809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 666809a6a62SRex Zhu { 667809a6a62SRex Zhu uint32_t data, data2; 668809a6a62SRex Zhu 669809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 670809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 671809a6a62SRex Zhu 672809a6a62SRex Zhu 673809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 674809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 675809a6a62SRex Zhu 676809a6a62SRex Zhu 677be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 678be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 679be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 680be3ecca7STom St Denis 681be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 682be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 683be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 684be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 685be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 686be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 687be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 688be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 689be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 690be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 691be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 692be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 693be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 694be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 695be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 696be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 697be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 698be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 699be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 700be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 701be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 702be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 703be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 704be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 705be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 706be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 707be3ecca7STom St Denis 708be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 709be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 710be3ecca7STom St Denis } 711be3ecca7STom St Denis 712be3ecca7STom St Denis #if 0 713be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 714be3ecca7STom St Denis { 715be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 716be3ecca7STom St Denis 717be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 718be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 719be3ecca7STom St Denis 720be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 721be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 722be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 723be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 724be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 725be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 726be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 727be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 728be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 729be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 730be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 731be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 732be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 733be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 734be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 735be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 736be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 737be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 738be3ecca7STom St Denis 739be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 740be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 741be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 742be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 743be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 744be3ecca7STom St Denis 745be3ecca7STom St Denis data |= cgc_flags; 746be3ecca7STom St Denis data1 |= suvd_flags; 747be3ecca7STom St Denis 748be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 749be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 750be3ecca7STom St Denis } 751be3ecca7STom St Denis #endif 752be3ecca7STom St Denis 753809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 754809a6a62SRex Zhu bool enable) 755809a6a62SRex Zhu { 756809a6a62SRex Zhu u32 orig, data; 757809a6a62SRex Zhu 758809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 759809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 760809a6a62SRex Zhu data |= 0xfff; 761809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 762809a6a62SRex Zhu 763809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 764809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 765809a6a62SRex Zhu if (orig != data) 766809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 767809a6a62SRex Zhu } else { 768809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 769809a6a62SRex Zhu data &= ~0xfff; 770809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 771809a6a62SRex Zhu 772809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 773809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 774809a6a62SRex Zhu if (orig != data) 775809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 776809a6a62SRex Zhu } 777809a6a62SRex Zhu } 7784be5097cSRex Zhu 7795fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7805fc3aeebSyanyang1 enum amd_clockgating_state state) 781aaa36a97SAlex Deucher { 78235e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 783be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 78435e5912dSAlex Deucher 785be3ecca7STom St Denis if (enable) { 786be3ecca7STom St Denis /* wait for STATUS to clear */ 787be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 788be3ecca7STom St Denis return -EBUSY; 789809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 790be3ecca7STom St Denis 791be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 792be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 793809a6a62SRex Zhu } else { 794809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 795be3ecca7STom St Denis } 796be3ecca7STom St Denis 797809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 798aaa36a97SAlex Deucher return 0; 799aaa36a97SAlex Deucher } 800aaa36a97SAlex Deucher 8015fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 8025fc3aeebSyanyang1 enum amd_powergating_state state) 803aaa36a97SAlex Deucher { 804aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 805aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 806aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 807aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 808aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 809aaa36a97SAlex Deucher * the smc and the hw blocks 810aaa36a97SAlex Deucher */ 8115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812c8781f56SHuang Rui int ret = 0; 8135fc3aeebSyanyang1 8145fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 815aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 816aaa36a97SAlex Deucher } else { 817c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 818c8781f56SHuang Rui if (ret) 819c8781f56SHuang Rui goto out; 820aaa36a97SAlex Deucher } 821c8781f56SHuang Rui 822c8781f56SHuang Rui out: 823c8781f56SHuang Rui return ret; 824c8781f56SHuang Rui } 825c8781f56SHuang Rui 826c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 827c8781f56SHuang Rui { 828c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 829c8781f56SHuang Rui int data; 830c8781f56SHuang Rui 831c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 832c8781f56SHuang Rui 833254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 834254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 835c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 836c8781f56SHuang Rui goto out; 837c8781f56SHuang Rui } 838c8781f56SHuang Rui 839c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 840c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 841c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 842c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 843c8781f56SHuang Rui 844c8781f56SHuang Rui out: 845c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 846aaa36a97SAlex Deucher } 847aaa36a97SAlex Deucher 848a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 84988a907d6STom St Denis .name = "uvd_v5_0", 850aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 851aaa36a97SAlex Deucher .late_init = NULL, 852aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 853aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 854aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 855aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 856aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 857aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 858aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 859aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 860aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 861aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 862aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 863c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 864aaa36a97SAlex Deucher }; 865aaa36a97SAlex Deucher 866aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 86721cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 86879887142SChristian König .align_mask = 0xf, 86979887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 870536fbf94SKen Wang .support_64bit_ptrs = false, 871aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 872aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 873aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 874aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 875e12f3d7aSChristian König .emit_frame_size = 876e12f3d7aSChristian König 2 + /* uvd_v5_0_ring_emit_hdp_flush */ 877e12f3d7aSChristian König 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ 878e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 879e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 880aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 881aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 882d5b4e25dSChristian König .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, 883d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate, 884aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8858de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 886edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 8879e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 888c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 889c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 890aaa36a97SAlex Deucher }; 891aaa36a97SAlex Deucher 892aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 893aaa36a97SAlex Deucher { 894aaa36a97SAlex Deucher adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; 895aaa36a97SAlex Deucher } 896aaa36a97SAlex Deucher 897aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 898aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 899aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 900aaa36a97SAlex Deucher }; 901aaa36a97SAlex Deucher 902aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 903aaa36a97SAlex Deucher { 904aaa36a97SAlex Deucher adev->uvd.irq.num_types = 1; 905aaa36a97SAlex Deucher adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 906aaa36a97SAlex Deucher } 907a1255107SAlex Deucher 908a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 909a1255107SAlex Deucher { 910a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 911a1255107SAlex Deucher .major = 5, 912a1255107SAlex Deucher .minor = 0, 913a1255107SAlex Deucher .rev = 0, 914a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 915a1255107SAlex Deucher }; 916