1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25c366be54SSam Ravnborg #include <linux/delay.h> 26aaa36a97SAlex Deucher #include <linux/firmware.h> 27c366be54SSam Ravnborg 28aaa36a97SAlex Deucher #include "amdgpu.h" 29aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 30aaa36a97SAlex Deucher #include "vid.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 32aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 34aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 35d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 36be3ecca7STom St Denis #include "vi.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 384be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 39091aec0bSAndrey Grodzovsky #include "ivsrcid/ivsrcid_vislands30.h" 40aaa36a97SAlex Deucher 41aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 43aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 44aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 45809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 46809a6a62SRex Zhu enum amd_clockgating_state state); 47809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 48809a6a62SRex Zhu bool enable); 49aaa36a97SAlex Deucher /** 50aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 51aaa36a97SAlex Deucher * 52aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 53aaa36a97SAlex Deucher * 54aaa36a97SAlex Deucher * Returns the current hardware read pointer 55aaa36a97SAlex Deucher */ 56536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 57aaa36a97SAlex Deucher { 58aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 59aaa36a97SAlex Deucher 60aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 61aaa36a97SAlex Deucher } 62aaa36a97SAlex Deucher 63aaa36a97SAlex Deucher /** 64aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 65aaa36a97SAlex Deucher * 66aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 67aaa36a97SAlex Deucher * 68aaa36a97SAlex Deucher * Returns the current hardware write pointer 69aaa36a97SAlex Deucher */ 70536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 71aaa36a97SAlex Deucher { 72aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 73aaa36a97SAlex Deucher 74aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 75aaa36a97SAlex Deucher } 76aaa36a97SAlex Deucher 77aaa36a97SAlex Deucher /** 78aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 79aaa36a97SAlex Deucher * 80aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 81aaa36a97SAlex Deucher * 82aaa36a97SAlex Deucher * Commits the write pointer to the hardware 83aaa36a97SAlex Deucher */ 84aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 85aaa36a97SAlex Deucher { 86aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 87aaa36a97SAlex Deucher 88536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 89aaa36a97SAlex Deucher } 90aaa36a97SAlex Deucher 915fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 92aaa36a97SAlex Deucher { 935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 942bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 955fc3aeebSyanyang1 96aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 97aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 98aaa36a97SAlex Deucher 99aaa36a97SAlex Deucher return 0; 100aaa36a97SAlex Deucher } 101aaa36a97SAlex Deucher 1025fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 103aaa36a97SAlex Deucher { 104aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1055fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 106aaa36a97SAlex Deucher int r; 107aaa36a97SAlex Deucher 108aaa36a97SAlex Deucher /* UVD TRAP */ 1091ffdeca6SChristian König r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 110aaa36a97SAlex Deucher if (r) 111aaa36a97SAlex Deucher return r; 112aaa36a97SAlex Deucher 113aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 114aaa36a97SAlex Deucher if (r) 115aaa36a97SAlex Deucher return r; 116aaa36a97SAlex Deucher 1172bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 118aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 1191c6d567bSNirmoy Das r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 120c107171bSChristian König AMDGPU_RING_PRIO_DEFAULT, NULL); 12133d5bd07SEmily Deng if (r) 12233d5bd07SEmily Deng return r; 12333d5bd07SEmily Deng 1243b34c14fSChris Wilson r = amdgpu_uvd_resume(adev); 1253b34c14fSChris Wilson if (r) 1263b34c14fSChris Wilson return r; 1273b34c14fSChris Wilson 12833d5bd07SEmily Deng r = amdgpu_uvd_entity_init(adev); 129aaa36a97SAlex Deucher 130aaa36a97SAlex Deucher return r; 131aaa36a97SAlex Deucher } 132aaa36a97SAlex Deucher 1335fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 134aaa36a97SAlex Deucher { 135aaa36a97SAlex Deucher int r; 1365fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 139aaa36a97SAlex Deucher if (r) 140aaa36a97SAlex Deucher return r; 141aaa36a97SAlex Deucher 14250237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 143aaa36a97SAlex Deucher } 144aaa36a97SAlex Deucher 145aaa36a97SAlex Deucher /** 146aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 147aaa36a97SAlex Deucher * 148c890ace5SLee Jones * @handle: handle used to pass amdgpu_device pointer 149aaa36a97SAlex Deucher * 150aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 151aaa36a97SAlex Deucher */ 1525fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 153aaa36a97SAlex Deucher { 1545fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 156aaa36a97SAlex Deucher uint32_t tmp; 157aaa36a97SAlex Deucher int r; 158aaa36a97SAlex Deucher 159e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 161e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 162aaa36a97SAlex Deucher 163c66ed765SAndrey Grodzovsky r = amdgpu_ring_test_helper(ring); 164c66ed765SAndrey Grodzovsky if (r) 165aaa36a97SAlex Deucher goto done; 166aaa36a97SAlex Deucher 167a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 168aaa36a97SAlex Deucher if (r) { 169aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170aaa36a97SAlex Deucher goto done; 171aaa36a97SAlex Deucher } 172aaa36a97SAlex Deucher 173aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176aaa36a97SAlex Deucher 177aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180aaa36a97SAlex Deucher 181aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184aaa36a97SAlex Deucher 185aaa36a97SAlex Deucher /* Clear timeout status bits */ 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 188aaa36a97SAlex Deucher 189aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 191aaa36a97SAlex Deucher 192a27de35cSChristian König amdgpu_ring_commit(ring); 193e3e672e6SRex Zhu 194aaa36a97SAlex Deucher done: 195aaa36a97SAlex Deucher if (!r) 196aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher return r; 199e3e672e6SRex Zhu 200aaa36a97SAlex Deucher } 201aaa36a97SAlex Deucher 202aaa36a97SAlex Deucher /** 203aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 204aaa36a97SAlex Deucher * 205c890ace5SLee Jones * @handle: handle used to pass amdgpu_device pointer 206aaa36a97SAlex Deucher * 207aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 208aaa36a97SAlex Deucher */ 2095fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 210aaa36a97SAlex Deucher { 2115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212aaa36a97SAlex Deucher 213*859e4659SEvan Quan /* 214*859e4659SEvan Quan * Proper cleanups before halting the HW engine: 215*859e4659SEvan Quan * - cancel the delayed idle work 216*859e4659SEvan Quan * - enable powergating 217*859e4659SEvan Quan * - enable clockgating 218*859e4659SEvan Quan * - disable dpm 219*859e4659SEvan Quan * 220*859e4659SEvan Quan * TODO: to align with the VCN implementation, move the 221*859e4659SEvan Quan * jobs for clockgating/powergating/dpm setting to 222*859e4659SEvan Quan * ->set_powergating_state(). 223*859e4659SEvan Quan */ 224*859e4659SEvan Quan cancel_delayed_work_sync(&adev->uvd.idle_work); 225*859e4659SEvan Quan 226*859e4659SEvan Quan if (adev->pm.dpm_enabled) { 227*859e4659SEvan Quan amdgpu_dpm_enable_uvd(adev, false); 228*859e4659SEvan Quan } else { 229*859e4659SEvan Quan amdgpu_asic_set_uvd_clocks(adev, 0, 0); 230*859e4659SEvan Quan /* shutdown the UVD block */ 231*859e4659SEvan Quan amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 232*859e4659SEvan Quan AMD_PG_STATE_GATE); 233*859e4659SEvan Quan amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 234*859e4659SEvan Quan AMD_CG_STATE_GATE); 235*859e4659SEvan Quan } 236*859e4659SEvan Quan 237e3e672e6SRex Zhu if (RREG32(mmUVD_STATUS) != 0) 238aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 239e3e672e6SRex Zhu 240aaa36a97SAlex Deucher return 0; 241aaa36a97SAlex Deucher } 242aaa36a97SAlex Deucher 2435fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 244aaa36a97SAlex Deucher { 245aaa36a97SAlex Deucher int r; 2465fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 247aaa36a97SAlex Deucher 2483f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 249aaa36a97SAlex Deucher if (r) 250aaa36a97SAlex Deucher return r; 251aaa36a97SAlex Deucher 25250237287SRex Zhu return amdgpu_uvd_suspend(adev); 253aaa36a97SAlex Deucher } 254aaa36a97SAlex Deucher 2555fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 256aaa36a97SAlex Deucher { 257aaa36a97SAlex Deucher int r; 2585fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 259aaa36a97SAlex Deucher 260aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 261aaa36a97SAlex Deucher if (r) 262aaa36a97SAlex Deucher return r; 263aaa36a97SAlex Deucher 26450237287SRex Zhu return uvd_v5_0_hw_init(adev); 265aaa36a97SAlex Deucher } 266aaa36a97SAlex Deucher 267aaa36a97SAlex Deucher /** 268aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 269aaa36a97SAlex Deucher * 270aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 271aaa36a97SAlex Deucher * 272aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 273aaa36a97SAlex Deucher */ 274aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 275aaa36a97SAlex Deucher { 276aaa36a97SAlex Deucher uint64_t offset; 277aaa36a97SAlex Deucher uint32_t size; 278aaa36a97SAlex Deucher 279f349f772SBernard Zhao /* program memory controller bits 0-27 */ 280aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 2812bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr)); 282aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 2832bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr)); 284aaa36a97SAlex Deucher 285aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 286c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 287aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 288aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 289aaa36a97SAlex Deucher 290aaa36a97SAlex Deucher offset += size; 291c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 292aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 293aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 294aaa36a97SAlex Deucher 295aaa36a97SAlex Deucher offset += size; 296c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 297c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 298aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 299aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 300549300ceSAlex Deucher 301549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 302549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 303549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 304aaa36a97SAlex Deucher } 305aaa36a97SAlex Deucher 306aaa36a97SAlex Deucher /** 307aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 308aaa36a97SAlex Deucher * 309aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 310aaa36a97SAlex Deucher * 311aaa36a97SAlex Deucher * Setup and start the UVD block 312aaa36a97SAlex Deucher */ 313aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 314aaa36a97SAlex Deucher { 3152bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 316aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 317aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 318aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 319aaa36a97SAlex Deucher int i, j, r; 320aaa36a97SAlex Deucher 321aaa36a97SAlex Deucher /*disable DPG */ 322aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 323aaa36a97SAlex Deucher 324aaa36a97SAlex Deucher /* disable byte swapping */ 325aaa36a97SAlex Deucher lmi_swap_cntl = 0; 326aaa36a97SAlex Deucher mp_swap_cntl = 0; 327aaa36a97SAlex Deucher 328aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher /* disable interupt */ 331aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 332aaa36a97SAlex Deucher 333aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 334aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 335aaa36a97SAlex Deucher mdelay(1); 336aaa36a97SAlex Deucher 337aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 338aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 339aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 340aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 341aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 342aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 343aaa36a97SAlex Deucher mdelay(5); 344aaa36a97SAlex Deucher 345aaa36a97SAlex Deucher /* take UVD block out of reset */ 346aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 347aaa36a97SAlex Deucher mdelay(5); 348aaa36a97SAlex Deucher 349aaa36a97SAlex Deucher /* initialize UVD memory controller */ 350aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 351aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 352aaa36a97SAlex Deucher 353aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 354aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 355aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 356aaa36a97SAlex Deucher mp_swap_cntl = 0; 357aaa36a97SAlex Deucher #endif 358aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 359aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 360aaa36a97SAlex Deucher 361aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 362aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 363aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 364aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 365aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 366aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 367aaa36a97SAlex Deucher 368aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 369aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 370aaa36a97SAlex Deucher mdelay(5); 371aaa36a97SAlex Deucher 372aaa36a97SAlex Deucher /* enable VCPU clock */ 373aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 374aaa36a97SAlex Deucher 375aaa36a97SAlex Deucher /* enable UMC */ 376aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 377aaa36a97SAlex Deucher 378aaa36a97SAlex Deucher /* boot up the VCPU */ 379aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 380aaa36a97SAlex Deucher mdelay(10); 381aaa36a97SAlex Deucher 382aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 383aaa36a97SAlex Deucher uint32_t status; 384aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 385aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 386aaa36a97SAlex Deucher if (status & 2) 387aaa36a97SAlex Deucher break; 388aaa36a97SAlex Deucher mdelay(10); 389aaa36a97SAlex Deucher } 390aaa36a97SAlex Deucher r = 0; 391aaa36a97SAlex Deucher if (status & 2) 392aaa36a97SAlex Deucher break; 393aaa36a97SAlex Deucher 394aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 395aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 396aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 397aaa36a97SAlex Deucher mdelay(10); 398aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 399aaa36a97SAlex Deucher mdelay(10); 400aaa36a97SAlex Deucher r = -1; 401aaa36a97SAlex Deucher } 402aaa36a97SAlex Deucher 403aaa36a97SAlex Deucher if (r) { 404aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 405aaa36a97SAlex Deucher return r; 406aaa36a97SAlex Deucher } 407aaa36a97SAlex Deucher /* enable master interrupt */ 408aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 409aaa36a97SAlex Deucher 410aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 411aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 412aaa36a97SAlex Deucher 413aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 414aaa36a97SAlex Deucher tmp = 0; 415aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 416aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 417aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 418aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 419aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 420aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 421aaa36a97SAlex Deucher /* force RBC into idle state */ 422aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 423aaa36a97SAlex Deucher 424aaa36a97SAlex Deucher /* set the write pointer delay */ 425aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 426aaa36a97SAlex Deucher 427aaa36a97SAlex Deucher /* set the wb address */ 428aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 429aaa36a97SAlex Deucher 430f349f772SBernard Zhao /* program the RB_BASE for ring buffer */ 431aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 432aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 433aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 434aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 435aaa36a97SAlex Deucher 436aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 437aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 438aaa36a97SAlex Deucher 439aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 440536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 441aaa36a97SAlex Deucher 442aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 443aaa36a97SAlex Deucher 444aaa36a97SAlex Deucher return 0; 445aaa36a97SAlex Deucher } 446aaa36a97SAlex Deucher 447aaa36a97SAlex Deucher /** 448aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 449aaa36a97SAlex Deucher * 450aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 451aaa36a97SAlex Deucher * 452aaa36a97SAlex Deucher * stop the UVD block 453aaa36a97SAlex Deucher */ 454aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 455aaa36a97SAlex Deucher { 456aaa36a97SAlex Deucher /* force RBC into idle state */ 457aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 458aaa36a97SAlex Deucher 459aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 460aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 461aaa36a97SAlex Deucher mdelay(1); 462aaa36a97SAlex Deucher 463aaa36a97SAlex Deucher /* put VCPU into reset */ 464aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 465aaa36a97SAlex Deucher mdelay(5); 466aaa36a97SAlex Deucher 467aaa36a97SAlex Deucher /* disable VCPU clock */ 468aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 469aaa36a97SAlex Deucher 470aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 471aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 472e3e672e6SRex Zhu 473e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 474aaa36a97SAlex Deucher } 475aaa36a97SAlex Deucher 476aaa36a97SAlex Deucher /** 477aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 478aaa36a97SAlex Deucher * 479aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 480c890ace5SLee Jones * @addr: address 481c890ace5SLee Jones * @seq: sequence number 482c890ace5SLee Jones * @flags: fence related flags 483aaa36a97SAlex Deucher * 484aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 485aaa36a97SAlex Deucher */ 486aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 487890ee23fSChunming Zhou unsigned flags) 488aaa36a97SAlex Deucher { 489890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 490aaa36a97SAlex Deucher 491aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 492aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 493aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 494aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 495aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 496aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 497aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 498aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 499aaa36a97SAlex Deucher 500aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 501aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 502aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 503aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 504aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 505aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 506aaa36a97SAlex Deucher } 507aaa36a97SAlex Deucher 508aaa36a97SAlex Deucher /** 509aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 510aaa36a97SAlex Deucher * 511aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 512aaa36a97SAlex Deucher * 513aaa36a97SAlex Deucher * Test if we can successfully write to the context register 514aaa36a97SAlex Deucher */ 515aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 516aaa36a97SAlex Deucher { 517aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 518aaa36a97SAlex Deucher uint32_t tmp = 0; 519aaa36a97SAlex Deucher unsigned i; 520aaa36a97SAlex Deucher int r; 521aaa36a97SAlex Deucher 522aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 523a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 524dc9eeff8SChristian König if (r) 525aaa36a97SAlex Deucher return r; 526aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 527aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 528a27de35cSChristian König amdgpu_ring_commit(ring); 529aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 530aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 531aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 532aaa36a97SAlex Deucher break; 533c366be54SSam Ravnborg udelay(1); 534aaa36a97SAlex Deucher } 535aaa36a97SAlex Deucher 536dc9eeff8SChristian König if (i >= adev->usec_timeout) 537dc9eeff8SChristian König r = -ETIMEDOUT; 538dc9eeff8SChristian König 539aaa36a97SAlex Deucher return r; 540aaa36a97SAlex Deucher } 541aaa36a97SAlex Deucher 542aaa36a97SAlex Deucher /** 543aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 544aaa36a97SAlex Deucher * 545aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 546c890ace5SLee Jones * @job: job to retrieve vmid from 547aaa36a97SAlex Deucher * @ib: indirect buffer to execute 548c890ace5SLee Jones * @flags: unused 549aaa36a97SAlex Deucher * 550aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 551aaa36a97SAlex Deucher */ 552aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 55334955e03SRex Zhu struct amdgpu_job *job, 554d88bf583SChristian König struct amdgpu_ib *ib, 555c4c905ecSJack Xiao uint32_t flags) 556aaa36a97SAlex Deucher { 557aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 558aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 559aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 560aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 561aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 562aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 563aaa36a97SAlex Deucher } 564aaa36a97SAlex Deucher 5650232e306SLeo Liu static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 5660232e306SLeo Liu { 5670232e306SLeo Liu int i; 5680232e306SLeo Liu 5690232e306SLeo Liu WARN_ON(ring->wptr % 2 || count % 2); 5700232e306SLeo Liu 5710232e306SLeo Liu for (i = 0; i < count / 2; i++) { 5720232e306SLeo Liu amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 5730232e306SLeo Liu amdgpu_ring_write(ring, 0); 5740232e306SLeo Liu } 5750232e306SLeo Liu } 5760232e306SLeo Liu 5775fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 578aaa36a97SAlex Deucher { 5795fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5805fc3aeebSyanyang1 581aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 582aaa36a97SAlex Deucher } 583aaa36a97SAlex Deucher 5845fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 585aaa36a97SAlex Deucher { 586aaa36a97SAlex Deucher unsigned i; 5875fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 588aaa36a97SAlex Deucher 589aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 590aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 591aaa36a97SAlex Deucher return 0; 592aaa36a97SAlex Deucher } 593aaa36a97SAlex Deucher return -ETIMEDOUT; 594aaa36a97SAlex Deucher } 595aaa36a97SAlex Deucher 5965fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 597aaa36a97SAlex Deucher { 5985fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5995fc3aeebSyanyang1 600aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 601aaa36a97SAlex Deucher 602aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 603aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 604aaa36a97SAlex Deucher mdelay(5); 605aaa36a97SAlex Deucher 606aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 607aaa36a97SAlex Deucher } 608aaa36a97SAlex Deucher 609aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 610aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 611aaa36a97SAlex Deucher unsigned type, 612aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 613aaa36a97SAlex Deucher { 614aaa36a97SAlex Deucher // TODO 615aaa36a97SAlex Deucher return 0; 616aaa36a97SAlex Deucher } 617aaa36a97SAlex Deucher 618aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 619aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 620aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 621aaa36a97SAlex Deucher { 622aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 6232bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 624aaa36a97SAlex Deucher return 0; 625aaa36a97SAlex Deucher } 626aaa36a97SAlex Deucher 627809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 628be3ecca7STom St Denis { 629809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 630be3ecca7STom St Denis 631be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 632809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 633be3ecca7STom St Denis 634be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 635be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 636be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 637be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 638be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 639be3ecca7STom St Denis 640809a6a62SRex Zhu if (enable) { 641809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 642809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 643809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 644809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 645809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 646809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 647809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 648809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 649809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 650809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 651809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 652809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 653809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 654809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 655809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 656809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 657809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 658809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6593c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6603c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6613c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 662809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 663809a6a62SRex Zhu data1 |= suvd_flags; 664809a6a62SRex Zhu } else { 665809a6a62SRex Zhu data3 = 0; 666809a6a62SRex Zhu data1 = 0; 667809a6a62SRex Zhu } 668809a6a62SRex Zhu 669809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 670809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 671809a6a62SRex Zhu } 672809a6a62SRex Zhu 673809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 674809a6a62SRex Zhu { 675809a6a62SRex Zhu uint32_t data, data2; 676809a6a62SRex Zhu 677809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 678809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 679809a6a62SRex Zhu 680809a6a62SRex Zhu 681809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 682809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 683809a6a62SRex Zhu 684809a6a62SRex Zhu 685be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 686be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 687be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 688be3ecca7STom St Denis 689be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 690be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 691be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 692be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 693be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 694be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 695be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 696be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 697be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 698be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 699be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 700be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 701be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 702be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 703be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 704be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 705be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 706be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 707be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 708be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 709be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 710be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 711be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 712be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 713be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 714be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 715be3ecca7STom St Denis 716be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 717be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 718be3ecca7STom St Denis } 719be3ecca7STom St Denis 720be3ecca7STom St Denis #if 0 721be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 722be3ecca7STom St Denis { 723be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 724be3ecca7STom St Denis 725be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 726be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 727be3ecca7STom St Denis 728be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 729be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 730be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 731be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 732be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 733be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 734be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 735be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 736be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 737be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 738be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 739be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 740be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 741be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 742be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 743be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 744be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 745be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 746be3ecca7STom St Denis 747be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 748be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 749be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 750be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 751be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 752be3ecca7STom St Denis 753be3ecca7STom St Denis data |= cgc_flags; 754be3ecca7STom St Denis data1 |= suvd_flags; 755be3ecca7STom St Denis 756be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 757be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 758be3ecca7STom St Denis } 759be3ecca7STom St Denis #endif 760be3ecca7STom St Denis 761809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 762809a6a62SRex Zhu bool enable) 763809a6a62SRex Zhu { 764809a6a62SRex Zhu u32 orig, data; 765809a6a62SRex Zhu 766809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 767809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 768809a6a62SRex Zhu data |= 0xfff; 769809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 770809a6a62SRex Zhu 771809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 772809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 773809a6a62SRex Zhu if (orig != data) 774809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 775809a6a62SRex Zhu } else { 776809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 777809a6a62SRex Zhu data &= ~0xfff; 778809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 779809a6a62SRex Zhu 780809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 781809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 782809a6a62SRex Zhu if (orig != data) 783809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 784809a6a62SRex Zhu } 785809a6a62SRex Zhu } 7864be5097cSRex Zhu 7875fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7885fc3aeebSyanyang1 enum amd_clockgating_state state) 789aaa36a97SAlex Deucher { 79035e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 791a9d4fe2fSNirmoy Das bool enable = (state == AMD_CG_STATE_GATE); 79235e5912dSAlex Deucher 793be3ecca7STom St Denis if (enable) { 794be3ecca7STom St Denis /* wait for STATUS to clear */ 795be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 796be3ecca7STom St Denis return -EBUSY; 797809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 798be3ecca7STom St Denis 799be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 800be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 801809a6a62SRex Zhu } else { 802809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 803be3ecca7STom St Denis } 804be3ecca7STom St Denis 805809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 806aaa36a97SAlex Deucher return 0; 807aaa36a97SAlex Deucher } 808aaa36a97SAlex Deucher 8095fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 8105fc3aeebSyanyang1 enum amd_powergating_state state) 811aaa36a97SAlex Deucher { 812aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 813aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 814aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 815aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 816aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 817aaa36a97SAlex Deucher * the smc and the hw blocks 818aaa36a97SAlex Deucher */ 8195fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 820c8781f56SHuang Rui int ret = 0; 8215fc3aeebSyanyang1 8225fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 823aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 824aaa36a97SAlex Deucher } else { 825c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 826c8781f56SHuang Rui if (ret) 827c8781f56SHuang Rui goto out; 828aaa36a97SAlex Deucher } 829c8781f56SHuang Rui 830c8781f56SHuang Rui out: 831c8781f56SHuang Rui return ret; 832c8781f56SHuang Rui } 833c8781f56SHuang Rui 834c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 835c8781f56SHuang Rui { 836c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 837c8781f56SHuang Rui int data; 838c8781f56SHuang Rui 839c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 840c8781f56SHuang Rui 841254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 842254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 843c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 844c8781f56SHuang Rui goto out; 845c8781f56SHuang Rui } 846c8781f56SHuang Rui 847c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 848c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 849c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 850c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 851c8781f56SHuang Rui 852c8781f56SHuang Rui out: 853c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 854aaa36a97SAlex Deucher } 855aaa36a97SAlex Deucher 856a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 85788a907d6STom St Denis .name = "uvd_v5_0", 858aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 859aaa36a97SAlex Deucher .late_init = NULL, 860aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 861aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 862aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 863aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 864aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 865aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 866aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 867aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 868aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 869aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 870aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 871c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 872aaa36a97SAlex Deucher }; 873aaa36a97SAlex Deucher 874aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 87521cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 87679887142SChristian König .align_mask = 0xf, 877536fbf94SKen Wang .support_64bit_ptrs = false, 8787ee250b1SLeo Liu .no_user_fence = true, 879aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 880aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 881aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 882aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 883e12f3d7aSChristian König .emit_frame_size = 884e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 885e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 886aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 887aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 888aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8898de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 8900232e306SLeo Liu .insert_nop = uvd_v5_0_ring_insert_nop, 8919e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 892c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 893c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 894aaa36a97SAlex Deucher }; 895aaa36a97SAlex Deucher 896aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 897aaa36a97SAlex Deucher { 8982bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 899aaa36a97SAlex Deucher } 900aaa36a97SAlex Deucher 901aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 902aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 903aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 904aaa36a97SAlex Deucher }; 905aaa36a97SAlex Deucher 906aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 907aaa36a97SAlex Deucher { 9082bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 9092bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 910aaa36a97SAlex Deucher } 911a1255107SAlex Deucher 912a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 913a1255107SAlex Deucher { 914a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 915a1255107SAlex Deucher .major = 5, 916a1255107SAlex Deucher .minor = 0, 917a1255107SAlex Deucher .rev = 0, 918a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 919a1255107SAlex Deucher }; 920