1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 35be3ecca7STom St Denis #include "vi.h" 364be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 38aaa36a97SAlex Deucher 39aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 40aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 41aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 43809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 44809a6a62SRex Zhu enum amd_clockgating_state state); 45809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 46809a6a62SRex Zhu bool enable); 47aaa36a97SAlex Deucher /** 48aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 49aaa36a97SAlex Deucher * 50aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 51aaa36a97SAlex Deucher * 52aaa36a97SAlex Deucher * Returns the current hardware read pointer 53aaa36a97SAlex Deucher */ 54aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 55aaa36a97SAlex Deucher { 56aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 57aaa36a97SAlex Deucher 58aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 59aaa36a97SAlex Deucher } 60aaa36a97SAlex Deucher 61aaa36a97SAlex Deucher /** 62aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 63aaa36a97SAlex Deucher * 64aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 65aaa36a97SAlex Deucher * 66aaa36a97SAlex Deucher * Returns the current hardware write pointer 67aaa36a97SAlex Deucher */ 68aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 69aaa36a97SAlex Deucher { 70aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 71aaa36a97SAlex Deucher 72aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 73aaa36a97SAlex Deucher } 74aaa36a97SAlex Deucher 75aaa36a97SAlex Deucher /** 76aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 77aaa36a97SAlex Deucher * 78aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 79aaa36a97SAlex Deucher * 80aaa36a97SAlex Deucher * Commits the write pointer to the hardware 81aaa36a97SAlex Deucher */ 82aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 83aaa36a97SAlex Deucher { 84aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 85aaa36a97SAlex Deucher 86aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 87aaa36a97SAlex Deucher } 88aaa36a97SAlex Deucher 895fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 90aaa36a97SAlex Deucher { 915fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 925fc3aeebSyanyang1 93aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 94aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 95aaa36a97SAlex Deucher 96aaa36a97SAlex Deucher return 0; 97aaa36a97SAlex Deucher } 98aaa36a97SAlex Deucher 995fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 100aaa36a97SAlex Deucher { 101aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1025fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 103aaa36a97SAlex Deucher int r; 104aaa36a97SAlex Deucher 105aaa36a97SAlex Deucher /* UVD TRAP */ 106aaa36a97SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 107aaa36a97SAlex Deucher if (r) 108aaa36a97SAlex Deucher return r; 109aaa36a97SAlex Deucher 110aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 111aaa36a97SAlex Deucher if (r) 112aaa36a97SAlex Deucher return r; 113aaa36a97SAlex Deucher 114aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 115aaa36a97SAlex Deucher if (r) 116aaa36a97SAlex Deucher return r; 117aaa36a97SAlex Deucher 118aaa36a97SAlex Deucher ring = &adev->uvd.ring; 119aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 12079887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 121aaa36a97SAlex Deucher 122aaa36a97SAlex Deucher return r; 123aaa36a97SAlex Deucher } 124aaa36a97SAlex Deucher 1255fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 126aaa36a97SAlex Deucher { 127aaa36a97SAlex Deucher int r; 1285fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 129aaa36a97SAlex Deucher 130aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 131aaa36a97SAlex Deucher if (r) 132aaa36a97SAlex Deucher return r; 133aaa36a97SAlex Deucher 134aaa36a97SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 135aaa36a97SAlex Deucher if (r) 136aaa36a97SAlex Deucher return r; 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher return r; 139aaa36a97SAlex Deucher } 140aaa36a97SAlex Deucher 141aaa36a97SAlex Deucher /** 142aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 143aaa36a97SAlex Deucher * 144aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 145aaa36a97SAlex Deucher * 146aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 147aaa36a97SAlex Deucher */ 1485fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 149aaa36a97SAlex Deucher { 1505fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 151aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 152aaa36a97SAlex Deucher uint32_t tmp; 153aaa36a97SAlex Deucher int r; 154aaa36a97SAlex Deucher 155aaa36a97SAlex Deucher r = uvd_v5_0_start(adev); 156aaa36a97SAlex Deucher if (r) 157aaa36a97SAlex Deucher goto done; 158aaa36a97SAlex Deucher 159aaa36a97SAlex Deucher ring->ready = true; 160aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 161aaa36a97SAlex Deucher if (r) { 162aaa36a97SAlex Deucher ring->ready = false; 163aaa36a97SAlex Deucher goto done; 164aaa36a97SAlex Deucher } 165aaa36a97SAlex Deucher 166a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 167aaa36a97SAlex Deucher if (r) { 168aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 169aaa36a97SAlex Deucher goto done; 170aaa36a97SAlex Deucher } 171aaa36a97SAlex Deucher 172aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 173aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 175aaa36a97SAlex Deucher 176aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 177aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 179aaa36a97SAlex Deucher 180aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 181aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 183aaa36a97SAlex Deucher 184aaa36a97SAlex Deucher /* Clear timeout status bits */ 185aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 187aaa36a97SAlex Deucher 188aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 189aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 190aaa36a97SAlex Deucher 191a27de35cSChristian König amdgpu_ring_commit(ring); 192aaa36a97SAlex Deucher done: 193aaa36a97SAlex Deucher if (!r) 194aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 195aaa36a97SAlex Deucher 196aaa36a97SAlex Deucher return r; 197aaa36a97SAlex Deucher } 198aaa36a97SAlex Deucher 199aaa36a97SAlex Deucher /** 200aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 201aaa36a97SAlex Deucher * 202aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 203aaa36a97SAlex Deucher * 204aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 205aaa36a97SAlex Deucher */ 2065fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 207aaa36a97SAlex Deucher { 2085fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 209aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 210aaa36a97SAlex Deucher 211aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 212aaa36a97SAlex Deucher ring->ready = false; 213aaa36a97SAlex Deucher 214aaa36a97SAlex Deucher return 0; 215aaa36a97SAlex Deucher } 216aaa36a97SAlex Deucher 2175fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 218aaa36a97SAlex Deucher { 219aaa36a97SAlex Deucher int r; 2205fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 221aaa36a97SAlex Deucher 2223f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 223aaa36a97SAlex Deucher if (r) 224aaa36a97SAlex Deucher return r; 225809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 226aaa36a97SAlex Deucher 2273f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 228aaa36a97SAlex Deucher if (r) 229aaa36a97SAlex Deucher return r; 230aaa36a97SAlex Deucher 231aaa36a97SAlex Deucher return r; 232aaa36a97SAlex Deucher } 233aaa36a97SAlex Deucher 2345fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 235aaa36a97SAlex Deucher { 236aaa36a97SAlex Deucher int r; 2375fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238aaa36a97SAlex Deucher 239aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 240aaa36a97SAlex Deucher if (r) 241aaa36a97SAlex Deucher return r; 242aaa36a97SAlex Deucher 243aaa36a97SAlex Deucher r = uvd_v5_0_hw_init(adev); 244aaa36a97SAlex Deucher if (r) 245aaa36a97SAlex Deucher return r; 246aaa36a97SAlex Deucher 247aaa36a97SAlex Deucher return r; 248aaa36a97SAlex Deucher } 249aaa36a97SAlex Deucher 250aaa36a97SAlex Deucher /** 251aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 252aaa36a97SAlex Deucher * 253aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 254aaa36a97SAlex Deucher * 255aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 256aaa36a97SAlex Deucher */ 257aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 258aaa36a97SAlex Deucher { 259aaa36a97SAlex Deucher uint64_t offset; 260aaa36a97SAlex Deucher uint32_t size; 261aaa36a97SAlex Deucher 262aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 263aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 264aaa36a97SAlex Deucher lower_32_bits(adev->uvd.gpu_addr)); 265aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 266aaa36a97SAlex Deucher upper_32_bits(adev->uvd.gpu_addr)); 267aaa36a97SAlex Deucher 268aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 269aaa36a97SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 270aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 271aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 272aaa36a97SAlex Deucher 273aaa36a97SAlex Deucher offset += size; 274c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 275aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 276aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 277aaa36a97SAlex Deucher 278aaa36a97SAlex Deucher offset += size; 279c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 280c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 281aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 282aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 283549300ceSAlex Deucher 284549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 285549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 286549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 287aaa36a97SAlex Deucher } 288aaa36a97SAlex Deucher 289aaa36a97SAlex Deucher /** 290aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 291aaa36a97SAlex Deucher * 292aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 293aaa36a97SAlex Deucher * 294aaa36a97SAlex Deucher * Setup and start the UVD block 295aaa36a97SAlex Deucher */ 296aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 297aaa36a97SAlex Deucher { 298aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 299aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 300aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 301aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 302aaa36a97SAlex Deucher int i, j, r; 303aaa36a97SAlex Deucher 304aaa36a97SAlex Deucher /*disable DPG */ 305aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 306aaa36a97SAlex Deucher 307aaa36a97SAlex Deucher /* disable byte swapping */ 308aaa36a97SAlex Deucher lmi_swap_cntl = 0; 309aaa36a97SAlex Deucher mp_swap_cntl = 0; 310aaa36a97SAlex Deucher 311aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 312aaa36a97SAlex Deucher 313809a6a62SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 314809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 315809a6a62SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 316aaa36a97SAlex Deucher 317aaa36a97SAlex Deucher /* disable interupt */ 318aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 319aaa36a97SAlex Deucher 320aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 321aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 322aaa36a97SAlex Deucher mdelay(1); 323aaa36a97SAlex Deucher 324aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 325aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 326aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 327aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 328aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 329aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 330aaa36a97SAlex Deucher mdelay(5); 331aaa36a97SAlex Deucher 332aaa36a97SAlex Deucher /* take UVD block out of reset */ 333aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 334aaa36a97SAlex Deucher mdelay(5); 335aaa36a97SAlex Deucher 336aaa36a97SAlex Deucher /* initialize UVD memory controller */ 337aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 338aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 339aaa36a97SAlex Deucher 340aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 341aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 342aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 343aaa36a97SAlex Deucher mp_swap_cntl = 0; 344aaa36a97SAlex Deucher #endif 345aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 346aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 347aaa36a97SAlex Deucher 348aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 349aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 350aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 351aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 352aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 353aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 354aaa36a97SAlex Deucher 355aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 356aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 357aaa36a97SAlex Deucher mdelay(5); 358aaa36a97SAlex Deucher 359aaa36a97SAlex Deucher /* enable VCPU clock */ 360aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 361aaa36a97SAlex Deucher 362aaa36a97SAlex Deucher /* enable UMC */ 363aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 364aaa36a97SAlex Deucher 365aaa36a97SAlex Deucher /* boot up the VCPU */ 366aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 367aaa36a97SAlex Deucher mdelay(10); 368aaa36a97SAlex Deucher 369aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 370aaa36a97SAlex Deucher uint32_t status; 371aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 372aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 373aaa36a97SAlex Deucher if (status & 2) 374aaa36a97SAlex Deucher break; 375aaa36a97SAlex Deucher mdelay(10); 376aaa36a97SAlex Deucher } 377aaa36a97SAlex Deucher r = 0; 378aaa36a97SAlex Deucher if (status & 2) 379aaa36a97SAlex Deucher break; 380aaa36a97SAlex Deucher 381aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 382aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 383aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 384aaa36a97SAlex Deucher mdelay(10); 385aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 386aaa36a97SAlex Deucher mdelay(10); 387aaa36a97SAlex Deucher r = -1; 388aaa36a97SAlex Deucher } 389aaa36a97SAlex Deucher 390aaa36a97SAlex Deucher if (r) { 391aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 392aaa36a97SAlex Deucher return r; 393aaa36a97SAlex Deucher } 394aaa36a97SAlex Deucher /* enable master interrupt */ 395aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 396aaa36a97SAlex Deucher 397aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 398aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 399aaa36a97SAlex Deucher 400aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 401aaa36a97SAlex Deucher tmp = 0; 402aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 403aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 404aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 405aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 406aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 407aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 408aaa36a97SAlex Deucher /* force RBC into idle state */ 409aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 410aaa36a97SAlex Deucher 411aaa36a97SAlex Deucher /* set the write pointer delay */ 412aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 413aaa36a97SAlex Deucher 414aaa36a97SAlex Deucher /* set the wb address */ 415aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 416aaa36a97SAlex Deucher 417aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 418aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 419aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 420aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 421aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 422aaa36a97SAlex Deucher 423aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 424aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 425aaa36a97SAlex Deucher 426aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 427aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 428aaa36a97SAlex Deucher 429aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 430aaa36a97SAlex Deucher 431aaa36a97SAlex Deucher return 0; 432aaa36a97SAlex Deucher } 433aaa36a97SAlex Deucher 434aaa36a97SAlex Deucher /** 435aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 436aaa36a97SAlex Deucher * 437aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 438aaa36a97SAlex Deucher * 439aaa36a97SAlex Deucher * stop the UVD block 440aaa36a97SAlex Deucher */ 441aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 442aaa36a97SAlex Deucher { 443aaa36a97SAlex Deucher /* force RBC into idle state */ 444aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 445aaa36a97SAlex Deucher 446aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 447aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 448aaa36a97SAlex Deucher mdelay(1); 449aaa36a97SAlex Deucher 450aaa36a97SAlex Deucher /* put VCPU into reset */ 451aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 452aaa36a97SAlex Deucher mdelay(5); 453aaa36a97SAlex Deucher 454aaa36a97SAlex Deucher /* disable VCPU clock */ 455aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 456aaa36a97SAlex Deucher 457aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 458aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 459aaa36a97SAlex Deucher } 460aaa36a97SAlex Deucher 461aaa36a97SAlex Deucher /** 462aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 463aaa36a97SAlex Deucher * 464aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 465aaa36a97SAlex Deucher * @fence: fence to emit 466aaa36a97SAlex Deucher * 467aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 468aaa36a97SAlex Deucher */ 469aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 470890ee23fSChunming Zhou unsigned flags) 471aaa36a97SAlex Deucher { 472890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 473aaa36a97SAlex Deucher 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 480aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 481aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 482aaa36a97SAlex Deucher 483aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 484aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 485aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 486aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 487aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 488aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 489aaa36a97SAlex Deucher } 490aaa36a97SAlex Deucher 491aaa36a97SAlex Deucher /** 492d5b4e25dSChristian König * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush 493d5b4e25dSChristian König * 494d5b4e25dSChristian König * @ring: amdgpu_ring pointer 495d5b4e25dSChristian König * 496d5b4e25dSChristian König * Emits an hdp flush. 497d5b4e25dSChristian König */ 498d5b4e25dSChristian König static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 499d5b4e25dSChristian König { 500d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 501d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 502d5b4e25dSChristian König } 503d5b4e25dSChristian König 504d5b4e25dSChristian König /** 505d5b4e25dSChristian König * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate 506d5b4e25dSChristian König * 507d5b4e25dSChristian König * @ring: amdgpu_ring pointer 508d5b4e25dSChristian König * 509d5b4e25dSChristian König * Emits an hdp invalidate. 510d5b4e25dSChristian König */ 511d5b4e25dSChristian König static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 512d5b4e25dSChristian König { 513d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 514d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 515d5b4e25dSChristian König } 516d5b4e25dSChristian König 517d5b4e25dSChristian König /** 518aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 519aaa36a97SAlex Deucher * 520aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 521aaa36a97SAlex Deucher * 522aaa36a97SAlex Deucher * Test if we can successfully write to the context register 523aaa36a97SAlex Deucher */ 524aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 525aaa36a97SAlex Deucher { 526aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 527aaa36a97SAlex Deucher uint32_t tmp = 0; 528aaa36a97SAlex Deucher unsigned i; 529aaa36a97SAlex Deucher int r; 530aaa36a97SAlex Deucher 531aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 532a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 533aaa36a97SAlex Deucher if (r) { 534aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 535aaa36a97SAlex Deucher ring->idx, r); 536aaa36a97SAlex Deucher return r; 537aaa36a97SAlex Deucher } 538aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 539aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 540a27de35cSChristian König amdgpu_ring_commit(ring); 541aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 542aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 543aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 544aaa36a97SAlex Deucher break; 545aaa36a97SAlex Deucher DRM_UDELAY(1); 546aaa36a97SAlex Deucher } 547aaa36a97SAlex Deucher 548aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 549aaa36a97SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 550aaa36a97SAlex Deucher ring->idx, i); 551aaa36a97SAlex Deucher } else { 552aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 553aaa36a97SAlex Deucher ring->idx, tmp); 554aaa36a97SAlex Deucher r = -EINVAL; 555aaa36a97SAlex Deucher } 556aaa36a97SAlex Deucher return r; 557aaa36a97SAlex Deucher } 558aaa36a97SAlex Deucher 559aaa36a97SAlex Deucher /** 560aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 561aaa36a97SAlex Deucher * 562aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 563aaa36a97SAlex Deucher * @ib: indirect buffer to execute 564aaa36a97SAlex Deucher * 565aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 566aaa36a97SAlex Deucher */ 567aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 568d88bf583SChristian König struct amdgpu_ib *ib, 569d88bf583SChristian König unsigned vm_id, bool ctx_switch) 570aaa36a97SAlex Deucher { 571aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 572aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 573aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 574aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 575aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 576aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 577aaa36a97SAlex Deucher } 578aaa36a97SAlex Deucher 5795fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 580aaa36a97SAlex Deucher { 5815fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5825fc3aeebSyanyang1 583aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 584aaa36a97SAlex Deucher } 585aaa36a97SAlex Deucher 5865fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 587aaa36a97SAlex Deucher { 588aaa36a97SAlex Deucher unsigned i; 5895fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 590aaa36a97SAlex Deucher 591aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 592aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 593aaa36a97SAlex Deucher return 0; 594aaa36a97SAlex Deucher } 595aaa36a97SAlex Deucher return -ETIMEDOUT; 596aaa36a97SAlex Deucher } 597aaa36a97SAlex Deucher 5985fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 599aaa36a97SAlex Deucher { 6005fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6015fc3aeebSyanyang1 602aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 603aaa36a97SAlex Deucher 604aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 605aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 606aaa36a97SAlex Deucher mdelay(5); 607aaa36a97SAlex Deucher 608aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 609aaa36a97SAlex Deucher } 610aaa36a97SAlex Deucher 611aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 612aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 613aaa36a97SAlex Deucher unsigned type, 614aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 615aaa36a97SAlex Deucher { 616aaa36a97SAlex Deucher // TODO 617aaa36a97SAlex Deucher return 0; 618aaa36a97SAlex Deucher } 619aaa36a97SAlex Deucher 620aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 621aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 622aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 623aaa36a97SAlex Deucher { 624aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 625aaa36a97SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 626aaa36a97SAlex Deucher return 0; 627aaa36a97SAlex Deucher } 628aaa36a97SAlex Deucher 629809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 630be3ecca7STom St Denis { 631809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 632be3ecca7STom St Denis 633be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 634809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 635be3ecca7STom St Denis 636be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 637be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 638be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 639be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 640be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 641be3ecca7STom St Denis 642809a6a62SRex Zhu if (enable) { 643809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 644809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 645809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 646809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 647809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 648809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 649809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 650809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 651809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 652809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 653809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 654809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 655809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 656809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 657809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 658809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 659809a6a62SRex Zhu UVD_CGC_GATE__VCPU_MASK | 660809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 661809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 662809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 663809a6a62SRex Zhu data1 |= suvd_flags; 664809a6a62SRex Zhu } else { 665809a6a62SRex Zhu data3 = 0; 666809a6a62SRex Zhu data1 = 0; 667809a6a62SRex Zhu } 668809a6a62SRex Zhu 669809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 670809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 671809a6a62SRex Zhu } 672809a6a62SRex Zhu 673809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 674809a6a62SRex Zhu { 675809a6a62SRex Zhu uint32_t data, data2; 676809a6a62SRex Zhu 677809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 678809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 679809a6a62SRex Zhu 680809a6a62SRex Zhu 681809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 682809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 683809a6a62SRex Zhu 684809a6a62SRex Zhu 685be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 686be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 687be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 688be3ecca7STom St Denis 689be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 690be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 691be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 692be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 693be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 694be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 695be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 696be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 697be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 698be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 699be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 700be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 701be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 702be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 703be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 704be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 705be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 706be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 707be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 708be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 709be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 710be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 711be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 712be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 713be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 714be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 715be3ecca7STom St Denis 716be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 717be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 718be3ecca7STom St Denis } 719be3ecca7STom St Denis 720be3ecca7STom St Denis #if 0 721be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 722be3ecca7STom St Denis { 723be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 724be3ecca7STom St Denis 725be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 726be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 727be3ecca7STom St Denis 728be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 729be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 730be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 731be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 732be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 733be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 734be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 735be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 736be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 737be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 738be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 739be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 740be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 741be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 742be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 743be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 744be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 745be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 746be3ecca7STom St Denis 747be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 748be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 749be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 750be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 751be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 752be3ecca7STom St Denis 753be3ecca7STom St Denis data |= cgc_flags; 754be3ecca7STom St Denis data1 |= suvd_flags; 755be3ecca7STom St Denis 756be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 757be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 758be3ecca7STom St Denis } 759be3ecca7STom St Denis #endif 760be3ecca7STom St Denis 761809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 762809a6a62SRex Zhu bool enable) 763809a6a62SRex Zhu { 764809a6a62SRex Zhu u32 orig, data; 765809a6a62SRex Zhu 766809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 767809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 768809a6a62SRex Zhu data |= 0xfff; 769809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 770809a6a62SRex Zhu 771809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 772809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 773809a6a62SRex Zhu if (orig != data) 774809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 775809a6a62SRex Zhu } else { 776809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 777809a6a62SRex Zhu data &= ~0xfff; 778809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 779809a6a62SRex Zhu 780809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 781809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 782809a6a62SRex Zhu if (orig != data) 783809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 784809a6a62SRex Zhu } 785809a6a62SRex Zhu } 7864be5097cSRex Zhu 7875fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7885fc3aeebSyanyang1 enum amd_clockgating_state state) 789aaa36a97SAlex Deucher { 79035e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 791be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 792be3ecca7STom St Denis static int curstate = -1; 79335e5912dSAlex Deucher 794e3b04bc7SAlex Deucher if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 79535e5912dSAlex Deucher return 0; 79635e5912dSAlex Deucher 797be3ecca7STom St Denis if (curstate == state) 798be3ecca7STom St Denis return 0; 799be3ecca7STom St Denis 800be3ecca7STom St Denis curstate = state; 801be3ecca7STom St Denis if (enable) { 802be3ecca7STom St Denis /* wait for STATUS to clear */ 803be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 804be3ecca7STom St Denis return -EBUSY; 805809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 806be3ecca7STom St Denis 807be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 808be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 809809a6a62SRex Zhu } else { 810809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 811be3ecca7STom St Denis } 812be3ecca7STom St Denis 813809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 814aaa36a97SAlex Deucher return 0; 815aaa36a97SAlex Deucher } 816aaa36a97SAlex Deucher 8175fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 8185fc3aeebSyanyang1 enum amd_powergating_state state) 819aaa36a97SAlex Deucher { 820aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 821aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 822aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 823aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 824aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 825aaa36a97SAlex Deucher * the smc and the hw blocks 826aaa36a97SAlex Deucher */ 8275fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8285fc3aeebSyanyang1 829e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 830b6df77fcSAlex Deucher return 0; 831b6df77fcSAlex Deucher 8325fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 833aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 834aaa36a97SAlex Deucher return 0; 835aaa36a97SAlex Deucher } else { 836aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 837aaa36a97SAlex Deucher } 838aaa36a97SAlex Deucher } 839aaa36a97SAlex Deucher 840a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 84188a907d6STom St Denis .name = "uvd_v5_0", 842aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 843aaa36a97SAlex Deucher .late_init = NULL, 844aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 845aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 846aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 847aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 848aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 849aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 850aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 851aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 852aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 853aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 854aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 855aaa36a97SAlex Deucher }; 856aaa36a97SAlex Deucher 857aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 85821cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 85979887142SChristian König .align_mask = 0xf, 86079887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 861aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 862aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 863aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 864aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 865e12f3d7aSChristian König .emit_frame_size = 866e12f3d7aSChristian König 2 + /* uvd_v5_0_ring_emit_hdp_flush */ 867e12f3d7aSChristian König 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ 868e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 869e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 870aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 871aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 872d5b4e25dSChristian König .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, 873d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate, 874aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8758de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 876edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 8779e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 878c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 879c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 880aaa36a97SAlex Deucher }; 881aaa36a97SAlex Deucher 882aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 883aaa36a97SAlex Deucher { 884aaa36a97SAlex Deucher adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; 885aaa36a97SAlex Deucher } 886aaa36a97SAlex Deucher 887aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 888aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 889aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 890aaa36a97SAlex Deucher }; 891aaa36a97SAlex Deucher 892aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 893aaa36a97SAlex Deucher { 894aaa36a97SAlex Deucher adev->uvd.irq.num_types = 1; 895aaa36a97SAlex Deucher adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 896aaa36a97SAlex Deucher } 897a1255107SAlex Deucher 898a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 899a1255107SAlex Deucher { 900a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 901a1255107SAlex Deucher .major = 5, 902a1255107SAlex Deucher .minor = 0, 903a1255107SAlex Deucher .rev = 0, 904a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 905a1255107SAlex Deucher }; 906