1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34aaa36a97SAlex Deucher 35aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 36aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 37aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 38aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 39aaa36a97SAlex Deucher 40aaa36a97SAlex Deucher /** 41aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 42aaa36a97SAlex Deucher * 43aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 44aaa36a97SAlex Deucher * 45aaa36a97SAlex Deucher * Returns the current hardware read pointer 46aaa36a97SAlex Deucher */ 47aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 48aaa36a97SAlex Deucher { 49aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 50aaa36a97SAlex Deucher 51aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 52aaa36a97SAlex Deucher } 53aaa36a97SAlex Deucher 54aaa36a97SAlex Deucher /** 55aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 56aaa36a97SAlex Deucher * 57aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 58aaa36a97SAlex Deucher * 59aaa36a97SAlex Deucher * Returns the current hardware write pointer 60aaa36a97SAlex Deucher */ 61aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 62aaa36a97SAlex Deucher { 63aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 64aaa36a97SAlex Deucher 65aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 66aaa36a97SAlex Deucher } 67aaa36a97SAlex Deucher 68aaa36a97SAlex Deucher /** 69aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 70aaa36a97SAlex Deucher * 71aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 72aaa36a97SAlex Deucher * 73aaa36a97SAlex Deucher * Commits the write pointer to the hardware 74aaa36a97SAlex Deucher */ 75aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 76aaa36a97SAlex Deucher { 77aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 78aaa36a97SAlex Deucher 79aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 80aaa36a97SAlex Deucher } 81aaa36a97SAlex Deucher 825fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 83aaa36a97SAlex Deucher { 845fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 855fc3aeebSyanyang1 86aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 87aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 88aaa36a97SAlex Deucher 89aaa36a97SAlex Deucher return 0; 90aaa36a97SAlex Deucher } 91aaa36a97SAlex Deucher 925fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 93aaa36a97SAlex Deucher { 94aaa36a97SAlex Deucher struct amdgpu_ring *ring; 955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96aaa36a97SAlex Deucher int r; 97aaa36a97SAlex Deucher 98aaa36a97SAlex Deucher /* UVD TRAP */ 99aaa36a97SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 100aaa36a97SAlex Deucher if (r) 101aaa36a97SAlex Deucher return r; 102aaa36a97SAlex Deucher 103aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 104aaa36a97SAlex Deucher if (r) 105aaa36a97SAlex Deucher return r; 106aaa36a97SAlex Deucher 107aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 108aaa36a97SAlex Deucher if (r) 109aaa36a97SAlex Deucher return r; 110aaa36a97SAlex Deucher 111aaa36a97SAlex Deucher ring = &adev->uvd.ring; 112aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 113aaa36a97SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 114aaa36a97SAlex Deucher &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 115aaa36a97SAlex Deucher 116aaa36a97SAlex Deucher return r; 117aaa36a97SAlex Deucher } 118aaa36a97SAlex Deucher 1195fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 120aaa36a97SAlex Deucher { 121aaa36a97SAlex Deucher int r; 1225fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 123aaa36a97SAlex Deucher 124aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 125aaa36a97SAlex Deucher if (r) 126aaa36a97SAlex Deucher return r; 127aaa36a97SAlex Deucher 128aaa36a97SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 129aaa36a97SAlex Deucher if (r) 130aaa36a97SAlex Deucher return r; 131aaa36a97SAlex Deucher 132aaa36a97SAlex Deucher return r; 133aaa36a97SAlex Deucher } 134aaa36a97SAlex Deucher 135aaa36a97SAlex Deucher /** 136aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 137aaa36a97SAlex Deucher * 138aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 139aaa36a97SAlex Deucher * 140aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 141aaa36a97SAlex Deucher */ 1425fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 143aaa36a97SAlex Deucher { 1445fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 145aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 146aaa36a97SAlex Deucher uint32_t tmp; 147aaa36a97SAlex Deucher int r; 148aaa36a97SAlex Deucher 149aaa36a97SAlex Deucher /* raise clocks while booting up the VCPU */ 150aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 151aaa36a97SAlex Deucher 152aaa36a97SAlex Deucher r = uvd_v5_0_start(adev); 153aaa36a97SAlex Deucher if (r) 154aaa36a97SAlex Deucher goto done; 155aaa36a97SAlex Deucher 156aaa36a97SAlex Deucher ring->ready = true; 157aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 158aaa36a97SAlex Deucher if (r) { 159aaa36a97SAlex Deucher ring->ready = false; 160aaa36a97SAlex Deucher goto done; 161aaa36a97SAlex Deucher } 162aaa36a97SAlex Deucher 163a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 164aaa36a97SAlex Deucher if (r) { 165aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 166aaa36a97SAlex Deucher goto done; 167aaa36a97SAlex Deucher } 168aaa36a97SAlex Deucher 169aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 170aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 171aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 172aaa36a97SAlex Deucher 173aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176aaa36a97SAlex Deucher 177aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180aaa36a97SAlex Deucher 181aaa36a97SAlex Deucher /* Clear timeout status bits */ 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 184aaa36a97SAlex Deucher 185aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 187aaa36a97SAlex Deucher 188a27de35cSChristian König amdgpu_ring_commit(ring); 189aaa36a97SAlex Deucher 190aaa36a97SAlex Deucher done: 191aaa36a97SAlex Deucher /* lower clocks again */ 192aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 193aaa36a97SAlex Deucher 194aaa36a97SAlex Deucher if (!r) 195aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 196aaa36a97SAlex Deucher 197aaa36a97SAlex Deucher return r; 198aaa36a97SAlex Deucher } 199aaa36a97SAlex Deucher 200aaa36a97SAlex Deucher /** 201aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 202aaa36a97SAlex Deucher * 203aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 204aaa36a97SAlex Deucher * 205aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 206aaa36a97SAlex Deucher */ 2075fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 208aaa36a97SAlex Deucher { 2095fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 210aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 211aaa36a97SAlex Deucher 212aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 213aaa36a97SAlex Deucher ring->ready = false; 214aaa36a97SAlex Deucher 215aaa36a97SAlex Deucher return 0; 216aaa36a97SAlex Deucher } 217aaa36a97SAlex Deucher 2185fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 219aaa36a97SAlex Deucher { 220aaa36a97SAlex Deucher int r; 2215fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 222aaa36a97SAlex Deucher 2232bd188d0SLeo Liu r = amdgpu_uvd_suspend(adev); 224aaa36a97SAlex Deucher if (r) 225aaa36a97SAlex Deucher return r; 226aaa36a97SAlex Deucher 2272bd188d0SLeo Liu r = uvd_v5_0_hw_fini(adev); 228aaa36a97SAlex Deucher if (r) 229aaa36a97SAlex Deucher return r; 230aaa36a97SAlex Deucher 231aaa36a97SAlex Deucher return r; 232aaa36a97SAlex Deucher } 233aaa36a97SAlex Deucher 2345fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 235aaa36a97SAlex Deucher { 236aaa36a97SAlex Deucher int r; 2375fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238aaa36a97SAlex Deucher 239aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 240aaa36a97SAlex Deucher if (r) 241aaa36a97SAlex Deucher return r; 242aaa36a97SAlex Deucher 243aaa36a97SAlex Deucher r = uvd_v5_0_hw_init(adev); 244aaa36a97SAlex Deucher if (r) 245aaa36a97SAlex Deucher return r; 246aaa36a97SAlex Deucher 247aaa36a97SAlex Deucher return r; 248aaa36a97SAlex Deucher } 249aaa36a97SAlex Deucher 250aaa36a97SAlex Deucher /** 251aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 252aaa36a97SAlex Deucher * 253aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 254aaa36a97SAlex Deucher * 255aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 256aaa36a97SAlex Deucher */ 257aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 258aaa36a97SAlex Deucher { 259aaa36a97SAlex Deucher uint64_t offset; 260aaa36a97SAlex Deucher uint32_t size; 261aaa36a97SAlex Deucher 262aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 263aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 264aaa36a97SAlex Deucher lower_32_bits(adev->uvd.gpu_addr)); 265aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 266aaa36a97SAlex Deucher upper_32_bits(adev->uvd.gpu_addr)); 267aaa36a97SAlex Deucher 268aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 269aaa36a97SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 270aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 271aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 272aaa36a97SAlex Deucher 273aaa36a97SAlex Deucher offset += size; 274aaa36a97SAlex Deucher size = AMDGPU_UVD_STACK_SIZE; 275aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 276aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 277aaa36a97SAlex Deucher 278aaa36a97SAlex Deucher offset += size; 279aaa36a97SAlex Deucher size = AMDGPU_UVD_HEAP_SIZE; 280aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 281aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 282549300ceSAlex Deucher 283549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 284549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 285549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 286aaa36a97SAlex Deucher } 287aaa36a97SAlex Deucher 288aaa36a97SAlex Deucher /** 289aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 290aaa36a97SAlex Deucher * 291aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 292aaa36a97SAlex Deucher * 293aaa36a97SAlex Deucher * Setup and start the UVD block 294aaa36a97SAlex Deucher */ 295aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 296aaa36a97SAlex Deucher { 297aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 298aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 299aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 300aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 301aaa36a97SAlex Deucher int i, j, r; 302aaa36a97SAlex Deucher 303aaa36a97SAlex Deucher /*disable DPG */ 304aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 305aaa36a97SAlex Deucher 306aaa36a97SAlex Deucher /* disable byte swapping */ 307aaa36a97SAlex Deucher lmi_swap_cntl = 0; 308aaa36a97SAlex Deucher mp_swap_cntl = 0; 309aaa36a97SAlex Deucher 310aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 311aaa36a97SAlex Deucher 312aaa36a97SAlex Deucher /* disable clock gating */ 313aaa36a97SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 314aaa36a97SAlex Deucher 315aaa36a97SAlex Deucher /* disable interupt */ 316aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 317aaa36a97SAlex Deucher 318aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 319aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 320aaa36a97SAlex Deucher mdelay(1); 321aaa36a97SAlex Deucher 322aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 323aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 324aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 325aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 326aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 327aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 328aaa36a97SAlex Deucher mdelay(5); 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher /* take UVD block out of reset */ 331aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 332aaa36a97SAlex Deucher mdelay(5); 333aaa36a97SAlex Deucher 334aaa36a97SAlex Deucher /* initialize UVD memory controller */ 335aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 336aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 337aaa36a97SAlex Deucher 338aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 339aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 340aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 341aaa36a97SAlex Deucher mp_swap_cntl = 0; 342aaa36a97SAlex Deucher #endif 343aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 344aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 345aaa36a97SAlex Deucher 346aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 347aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 348aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 349aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 350aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 351aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 352aaa36a97SAlex Deucher 353aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 354aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 355aaa36a97SAlex Deucher mdelay(5); 356aaa36a97SAlex Deucher 357aaa36a97SAlex Deucher /* enable VCPU clock */ 358aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 359aaa36a97SAlex Deucher 360aaa36a97SAlex Deucher /* enable UMC */ 361aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 362aaa36a97SAlex Deucher 363aaa36a97SAlex Deucher /* boot up the VCPU */ 364aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 365aaa36a97SAlex Deucher mdelay(10); 366aaa36a97SAlex Deucher 367aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 368aaa36a97SAlex Deucher uint32_t status; 369aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 370aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 371aaa36a97SAlex Deucher if (status & 2) 372aaa36a97SAlex Deucher break; 373aaa36a97SAlex Deucher mdelay(10); 374aaa36a97SAlex Deucher } 375aaa36a97SAlex Deucher r = 0; 376aaa36a97SAlex Deucher if (status & 2) 377aaa36a97SAlex Deucher break; 378aaa36a97SAlex Deucher 379aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 380aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 381aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 382aaa36a97SAlex Deucher mdelay(10); 383aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 384aaa36a97SAlex Deucher mdelay(10); 385aaa36a97SAlex Deucher r = -1; 386aaa36a97SAlex Deucher } 387aaa36a97SAlex Deucher 388aaa36a97SAlex Deucher if (r) { 389aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 390aaa36a97SAlex Deucher return r; 391aaa36a97SAlex Deucher } 392aaa36a97SAlex Deucher /* enable master interrupt */ 393aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 394aaa36a97SAlex Deucher 395aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 396aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 397aaa36a97SAlex Deucher 398aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 399aaa36a97SAlex Deucher tmp = 0; 400aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 401aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 402aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 403aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 404aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 405aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 406aaa36a97SAlex Deucher /* force RBC into idle state */ 407aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 408aaa36a97SAlex Deucher 409aaa36a97SAlex Deucher /* set the write pointer delay */ 410aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 411aaa36a97SAlex Deucher 412aaa36a97SAlex Deucher /* set the wb address */ 413aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 414aaa36a97SAlex Deucher 415aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 416aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 417aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 418aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 419aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 420aaa36a97SAlex Deucher 421aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 422aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 423aaa36a97SAlex Deucher 424aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 425aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 426aaa36a97SAlex Deucher 427aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 428aaa36a97SAlex Deucher 429aaa36a97SAlex Deucher return 0; 430aaa36a97SAlex Deucher } 431aaa36a97SAlex Deucher 432aaa36a97SAlex Deucher /** 433aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 434aaa36a97SAlex Deucher * 435aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 436aaa36a97SAlex Deucher * 437aaa36a97SAlex Deucher * stop the UVD block 438aaa36a97SAlex Deucher */ 439aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 440aaa36a97SAlex Deucher { 441aaa36a97SAlex Deucher /* force RBC into idle state */ 442aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 443aaa36a97SAlex Deucher 444aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 445aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 446aaa36a97SAlex Deucher mdelay(1); 447aaa36a97SAlex Deucher 448aaa36a97SAlex Deucher /* put VCPU into reset */ 449aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 450aaa36a97SAlex Deucher mdelay(5); 451aaa36a97SAlex Deucher 452aaa36a97SAlex Deucher /* disable VCPU clock */ 453aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 454aaa36a97SAlex Deucher 455aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 456aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 457aaa36a97SAlex Deucher } 458aaa36a97SAlex Deucher 459aaa36a97SAlex Deucher /** 460aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 461aaa36a97SAlex Deucher * 462aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 463aaa36a97SAlex Deucher * @fence: fence to emit 464aaa36a97SAlex Deucher * 465aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 466aaa36a97SAlex Deucher */ 467aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 468890ee23fSChunming Zhou unsigned flags) 469aaa36a97SAlex Deucher { 470890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 471aaa36a97SAlex Deucher 472aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 473aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 480aaa36a97SAlex Deucher 481aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 482aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 483aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 484aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 485aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 486aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 487aaa36a97SAlex Deucher } 488aaa36a97SAlex Deucher 489aaa36a97SAlex Deucher /** 490aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 491aaa36a97SAlex Deucher * 492aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 493aaa36a97SAlex Deucher * 494aaa36a97SAlex Deucher * Test if we can successfully write to the context register 495aaa36a97SAlex Deucher */ 496aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 497aaa36a97SAlex Deucher { 498aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 499aaa36a97SAlex Deucher uint32_t tmp = 0; 500aaa36a97SAlex Deucher unsigned i; 501aaa36a97SAlex Deucher int r; 502aaa36a97SAlex Deucher 503aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 504a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 505aaa36a97SAlex Deucher if (r) { 506aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 507aaa36a97SAlex Deucher ring->idx, r); 508aaa36a97SAlex Deucher return r; 509aaa36a97SAlex Deucher } 510aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 511aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 512a27de35cSChristian König amdgpu_ring_commit(ring); 513aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 514aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 515aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 516aaa36a97SAlex Deucher break; 517aaa36a97SAlex Deucher DRM_UDELAY(1); 518aaa36a97SAlex Deucher } 519aaa36a97SAlex Deucher 520aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 521aaa36a97SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 522aaa36a97SAlex Deucher ring->idx, i); 523aaa36a97SAlex Deucher } else { 524aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 525aaa36a97SAlex Deucher ring->idx, tmp); 526aaa36a97SAlex Deucher r = -EINVAL; 527aaa36a97SAlex Deucher } 528aaa36a97SAlex Deucher return r; 529aaa36a97SAlex Deucher } 530aaa36a97SAlex Deucher 531aaa36a97SAlex Deucher /** 532aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 533aaa36a97SAlex Deucher * 534aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 535aaa36a97SAlex Deucher * @ib: indirect buffer to execute 536aaa36a97SAlex Deucher * 537aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 538aaa36a97SAlex Deucher */ 539aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 540aaa36a97SAlex Deucher struct amdgpu_ib *ib) 541aaa36a97SAlex Deucher { 542aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 543aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 544aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 545aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 546aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 547aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 548aaa36a97SAlex Deucher } 549aaa36a97SAlex Deucher 550aaa36a97SAlex Deucher /** 551aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ib - test ib execution 552aaa36a97SAlex Deucher * 553aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 554aaa36a97SAlex Deucher * 555aaa36a97SAlex Deucher * Test if we can successfully execute an IB 556aaa36a97SAlex Deucher */ 557aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring) 558aaa36a97SAlex Deucher { 559aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 5600e3f154aSChunming Zhou struct fence *fence = NULL; 561aaa36a97SAlex Deucher int r; 562aaa36a97SAlex Deucher 563aaa36a97SAlex Deucher r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 564aaa36a97SAlex Deucher if (r) { 565aaa36a97SAlex Deucher DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 566aaa36a97SAlex Deucher return r; 567aaa36a97SAlex Deucher } 568aaa36a97SAlex Deucher 569aaa36a97SAlex Deucher r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 570aaa36a97SAlex Deucher if (r) { 571aaa36a97SAlex Deucher DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 572aaa36a97SAlex Deucher goto error; 573aaa36a97SAlex Deucher } 574aaa36a97SAlex Deucher 575d7af97dbSChristian König r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 576aaa36a97SAlex Deucher if (r) { 577aaa36a97SAlex Deucher DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 578aaa36a97SAlex Deucher goto error; 579aaa36a97SAlex Deucher } 580aaa36a97SAlex Deucher 5810e3f154aSChunming Zhou r = fence_wait(fence, false); 582aaa36a97SAlex Deucher if (r) { 583aaa36a97SAlex Deucher DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 584aaa36a97SAlex Deucher goto error; 585aaa36a97SAlex Deucher } 586aaa36a97SAlex Deucher DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 587aaa36a97SAlex Deucher error: 5880e3f154aSChunming Zhou fence_put(fence); 589aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 590aaa36a97SAlex Deucher return r; 591aaa36a97SAlex Deucher } 592aaa36a97SAlex Deucher 5935fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 594aaa36a97SAlex Deucher { 5955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5965fc3aeebSyanyang1 597aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 598aaa36a97SAlex Deucher } 599aaa36a97SAlex Deucher 6005fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 601aaa36a97SAlex Deucher { 602aaa36a97SAlex Deucher unsigned i; 6035fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604aaa36a97SAlex Deucher 605aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 606aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 607aaa36a97SAlex Deucher return 0; 608aaa36a97SAlex Deucher } 609aaa36a97SAlex Deucher return -ETIMEDOUT; 610aaa36a97SAlex Deucher } 611aaa36a97SAlex Deucher 6125fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 613aaa36a97SAlex Deucher { 6145fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6155fc3aeebSyanyang1 616aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 617aaa36a97SAlex Deucher 618aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 619aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 620aaa36a97SAlex Deucher mdelay(5); 621aaa36a97SAlex Deucher 622aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 623aaa36a97SAlex Deucher } 624aaa36a97SAlex Deucher 6255fc3aeebSyanyang1 static void uvd_v5_0_print_status(void *handle) 626aaa36a97SAlex Deucher { 6275fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 628aaa36a97SAlex Deucher dev_info(adev->dev, "UVD 5.0 registers\n"); 629aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 630aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_ADDR_LOW)); 631aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 632aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_ADDR_HIGH)); 633aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 634aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_CMD)); 635aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 636aaa36a97SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_CMD)); 637aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 638aaa36a97SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA0)); 639aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 640aaa36a97SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA1)); 641aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 642aaa36a97SAlex Deucher RREG32(mmUVD_ENGINE_CNTL)); 643aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 644aaa36a97SAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 645aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 646aaa36a97SAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 647aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 648aaa36a97SAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 649aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 650aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_CNTL)); 651aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 652aaa36a97SAlex Deucher RREG32(mmUVD_LMI_EXT40_ADDR)); 653aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 654aaa36a97SAlex Deucher RREG32(mmUVD_CTX_INDEX)); 655aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 656aaa36a97SAlex Deucher RREG32(mmUVD_CTX_DATA)); 657aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 658aaa36a97SAlex Deucher RREG32(mmUVD_CGC_GATE)); 659aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 660aaa36a97SAlex Deucher RREG32(mmUVD_CGC_CTRL)); 661aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 662aaa36a97SAlex Deucher RREG32(mmUVD_LMI_CTRL2)); 663aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 664aaa36a97SAlex Deucher RREG32(mmUVD_MASTINT_EN)); 665aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 666aaa36a97SAlex Deucher RREG32(mmUVD_LMI_ADDR_EXT)); 667aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 668aaa36a97SAlex Deucher RREG32(mmUVD_LMI_CTRL)); 669aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 670aaa36a97SAlex Deucher RREG32(mmUVD_LMI_SWAP_CNTL)); 671aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 672aaa36a97SAlex Deucher RREG32(mmUVD_MP_SWAP_CNTL)); 673aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 674aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA0)); 675aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 676aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA1)); 677aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 678aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB0)); 679aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 680aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB1)); 681aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 682aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_MUX)); 683aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 684aaa36a97SAlex Deucher RREG32(mmUVD_MPC_SET_ALU)); 685aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 686aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 687aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 688aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE0)); 689aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 690aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 691aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 692aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE1)); 693aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 694aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 695aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 696aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE2)); 697aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 698aaa36a97SAlex Deucher RREG32(mmUVD_VCPU_CNTL)); 699aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 700aaa36a97SAlex Deucher RREG32(mmUVD_SOFT_RESET)); 701aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n", 702aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)); 703aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n", 704aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)); 705aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 706aaa36a97SAlex Deucher RREG32(mmUVD_RBC_IB_SIZE)); 707aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n", 708aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)); 709aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n", 710aaa36a97SAlex Deucher RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)); 711aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 712aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_RPTR)); 713aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 714aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR)); 715aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 716aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 717aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 718aaa36a97SAlex Deucher RREG32(mmUVD_RBC_RB_CNTL)); 719aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 720aaa36a97SAlex Deucher RREG32(mmUVD_STATUS)); 721aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 722aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 723aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 724aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 725aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 726aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 727aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 728aaa36a97SAlex Deucher RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 729aaa36a97SAlex Deucher dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 730aaa36a97SAlex Deucher RREG32(mmUVD_CONTEXT_ID)); 731549300ceSAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 732549300ceSAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 733549300ceSAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 734549300ceSAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 735549300ceSAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 736549300ceSAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 737aaa36a97SAlex Deucher } 738aaa36a97SAlex Deucher 739aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 740aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 741aaa36a97SAlex Deucher unsigned type, 742aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 743aaa36a97SAlex Deucher { 744aaa36a97SAlex Deucher // TODO 745aaa36a97SAlex Deucher return 0; 746aaa36a97SAlex Deucher } 747aaa36a97SAlex Deucher 748aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 749aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 750aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 751aaa36a97SAlex Deucher { 752aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 753aaa36a97SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 754aaa36a97SAlex Deucher return 0; 755aaa36a97SAlex Deucher } 756aaa36a97SAlex Deucher 7575fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7585fc3aeebSyanyang1 enum amd_clockgating_state state) 759aaa36a97SAlex Deucher { 760aaa36a97SAlex Deucher return 0; 761aaa36a97SAlex Deucher } 762aaa36a97SAlex Deucher 7635fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 7645fc3aeebSyanyang1 enum amd_powergating_state state) 765aaa36a97SAlex Deucher { 766aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 767aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 768aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 769aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 770aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 771aaa36a97SAlex Deucher * the smc and the hw blocks 772aaa36a97SAlex Deucher */ 7735fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7745fc3aeebSyanyang1 7755fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 776aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 777aaa36a97SAlex Deucher return 0; 778aaa36a97SAlex Deucher } else { 779aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 780aaa36a97SAlex Deucher } 781aaa36a97SAlex Deucher } 782aaa36a97SAlex Deucher 7835fc3aeebSyanyang1 const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 784aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 785aaa36a97SAlex Deucher .late_init = NULL, 786aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 787aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 788aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 789aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 790aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 791aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 792aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 793aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 794aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 795aaa36a97SAlex Deucher .print_status = uvd_v5_0_print_status, 796aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 797aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 798aaa36a97SAlex Deucher }; 799aaa36a97SAlex Deucher 800aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 801aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 802aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 803aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 804aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 805aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 806aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 807aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 808aaa36a97SAlex Deucher .test_ib = uvd_v5_0_ring_test_ib, 809edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 8109e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 811aaa36a97SAlex Deucher }; 812aaa36a97SAlex Deucher 813aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 814aaa36a97SAlex Deucher { 815aaa36a97SAlex Deucher adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; 816aaa36a97SAlex Deucher } 817aaa36a97SAlex Deucher 818aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 819aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 820aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 821aaa36a97SAlex Deucher }; 822aaa36a97SAlex Deucher 823aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 824aaa36a97SAlex Deucher { 825aaa36a97SAlex Deucher adev->uvd.irq.num_types = 1; 826aaa36a97SAlex Deucher adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 827aaa36a97SAlex Deucher } 828