1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 35be3ecca7STom St Denis #include "vi.h" 364be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 38aaa36a97SAlex Deucher 39aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 40aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 41aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 43aaa36a97SAlex Deucher 44aaa36a97SAlex Deucher /** 45aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 46aaa36a97SAlex Deucher * 47aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 48aaa36a97SAlex Deucher * 49aaa36a97SAlex Deucher * Returns the current hardware read pointer 50aaa36a97SAlex Deucher */ 51aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 52aaa36a97SAlex Deucher { 53aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 54aaa36a97SAlex Deucher 55aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 56aaa36a97SAlex Deucher } 57aaa36a97SAlex Deucher 58aaa36a97SAlex Deucher /** 59aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 60aaa36a97SAlex Deucher * 61aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 62aaa36a97SAlex Deucher * 63aaa36a97SAlex Deucher * Returns the current hardware write pointer 64aaa36a97SAlex Deucher */ 65aaa36a97SAlex Deucher static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 66aaa36a97SAlex Deucher { 67aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 68aaa36a97SAlex Deucher 69aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 70aaa36a97SAlex Deucher } 71aaa36a97SAlex Deucher 72aaa36a97SAlex Deucher /** 73aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 74aaa36a97SAlex Deucher * 75aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 76aaa36a97SAlex Deucher * 77aaa36a97SAlex Deucher * Commits the write pointer to the hardware 78aaa36a97SAlex Deucher */ 79aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 80aaa36a97SAlex Deucher { 81aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 82aaa36a97SAlex Deucher 83aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 84aaa36a97SAlex Deucher } 85aaa36a97SAlex Deucher 865fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 87aaa36a97SAlex Deucher { 885fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895fc3aeebSyanyang1 90aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 91aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 92aaa36a97SAlex Deucher 93aaa36a97SAlex Deucher return 0; 94aaa36a97SAlex Deucher } 95aaa36a97SAlex Deucher 965fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 97aaa36a97SAlex Deucher { 98aaa36a97SAlex Deucher struct amdgpu_ring *ring; 995fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 100aaa36a97SAlex Deucher int r; 101aaa36a97SAlex Deucher 102aaa36a97SAlex Deucher /* UVD TRAP */ 103aaa36a97SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 104aaa36a97SAlex Deucher if (r) 105aaa36a97SAlex Deucher return r; 106aaa36a97SAlex Deucher 107aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 108aaa36a97SAlex Deucher if (r) 109aaa36a97SAlex Deucher return r; 110aaa36a97SAlex Deucher 111aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 112aaa36a97SAlex Deucher if (r) 113aaa36a97SAlex Deucher return r; 114aaa36a97SAlex Deucher 115aaa36a97SAlex Deucher ring = &adev->uvd.ring; 116aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 11779887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 118aaa36a97SAlex Deucher 119aaa36a97SAlex Deucher return r; 120aaa36a97SAlex Deucher } 121aaa36a97SAlex Deucher 1225fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 123aaa36a97SAlex Deucher { 124aaa36a97SAlex Deucher int r; 1255fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 126aaa36a97SAlex Deucher 127aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 128aaa36a97SAlex Deucher if (r) 129aaa36a97SAlex Deucher return r; 130aaa36a97SAlex Deucher 131aaa36a97SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 132aaa36a97SAlex Deucher if (r) 133aaa36a97SAlex Deucher return r; 134aaa36a97SAlex Deucher 135aaa36a97SAlex Deucher return r; 136aaa36a97SAlex Deucher } 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher /** 139aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 140aaa36a97SAlex Deucher * 141aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 142aaa36a97SAlex Deucher * 143aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 144aaa36a97SAlex Deucher */ 1455fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 146aaa36a97SAlex Deucher { 1475fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 148aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 149aaa36a97SAlex Deucher uint32_t tmp; 150aaa36a97SAlex Deucher int r; 151aaa36a97SAlex Deucher 152aaa36a97SAlex Deucher /* raise clocks while booting up the VCPU */ 153aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 154aaa36a97SAlex Deucher 155aaa36a97SAlex Deucher r = uvd_v5_0_start(adev); 156aaa36a97SAlex Deucher if (r) 157aaa36a97SAlex Deucher goto done; 158aaa36a97SAlex Deucher 159aaa36a97SAlex Deucher ring->ready = true; 160aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 161aaa36a97SAlex Deucher if (r) { 162aaa36a97SAlex Deucher ring->ready = false; 163aaa36a97SAlex Deucher goto done; 164aaa36a97SAlex Deucher } 165aaa36a97SAlex Deucher 166a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 167aaa36a97SAlex Deucher if (r) { 168aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 169aaa36a97SAlex Deucher goto done; 170aaa36a97SAlex Deucher } 171aaa36a97SAlex Deucher 172aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 173aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 175aaa36a97SAlex Deucher 176aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 177aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 179aaa36a97SAlex Deucher 180aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 181aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 183aaa36a97SAlex Deucher 184aaa36a97SAlex Deucher /* Clear timeout status bits */ 185aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 187aaa36a97SAlex Deucher 188aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 189aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 190aaa36a97SAlex Deucher 191a27de35cSChristian König amdgpu_ring_commit(ring); 192aaa36a97SAlex Deucher 193aaa36a97SAlex Deucher done: 194aaa36a97SAlex Deucher /* lower clocks again */ 195aaa36a97SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 196aaa36a97SAlex Deucher 197aaa36a97SAlex Deucher if (!r) 198aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 199aaa36a97SAlex Deucher 200aaa36a97SAlex Deucher return r; 201aaa36a97SAlex Deucher } 202aaa36a97SAlex Deucher 203aaa36a97SAlex Deucher /** 204aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 205aaa36a97SAlex Deucher * 206aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 207aaa36a97SAlex Deucher * 208aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 209aaa36a97SAlex Deucher */ 2105fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 211aaa36a97SAlex Deucher { 2125fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 213aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 214aaa36a97SAlex Deucher 215aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 216aaa36a97SAlex Deucher ring->ready = false; 217aaa36a97SAlex Deucher 218aaa36a97SAlex Deucher return 0; 219aaa36a97SAlex Deucher } 220aaa36a97SAlex Deucher 2215fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 222aaa36a97SAlex Deucher { 223aaa36a97SAlex Deucher int r; 2245fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225aaa36a97SAlex Deucher 2263f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 227aaa36a97SAlex Deucher if (r) 228aaa36a97SAlex Deucher return r; 229aaa36a97SAlex Deucher 2303f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 231aaa36a97SAlex Deucher if (r) 232aaa36a97SAlex Deucher return r; 233aaa36a97SAlex Deucher 234aaa36a97SAlex Deucher return r; 235aaa36a97SAlex Deucher } 236aaa36a97SAlex Deucher 2375fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 238aaa36a97SAlex Deucher { 239aaa36a97SAlex Deucher int r; 2405fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 241aaa36a97SAlex Deucher 242aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 243aaa36a97SAlex Deucher if (r) 244aaa36a97SAlex Deucher return r; 245aaa36a97SAlex Deucher 246aaa36a97SAlex Deucher r = uvd_v5_0_hw_init(adev); 247aaa36a97SAlex Deucher if (r) 248aaa36a97SAlex Deucher return r; 249aaa36a97SAlex Deucher 250aaa36a97SAlex Deucher return r; 251aaa36a97SAlex Deucher } 252aaa36a97SAlex Deucher 253aaa36a97SAlex Deucher /** 254aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 255aaa36a97SAlex Deucher * 256aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 257aaa36a97SAlex Deucher * 258aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 259aaa36a97SAlex Deucher */ 260aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 261aaa36a97SAlex Deucher { 262aaa36a97SAlex Deucher uint64_t offset; 263aaa36a97SAlex Deucher uint32_t size; 264aaa36a97SAlex Deucher 265aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 266aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 267aaa36a97SAlex Deucher lower_32_bits(adev->uvd.gpu_addr)); 268aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 269aaa36a97SAlex Deucher upper_32_bits(adev->uvd.gpu_addr)); 270aaa36a97SAlex Deucher 271aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 272aaa36a97SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 273aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 274aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 275aaa36a97SAlex Deucher 276aaa36a97SAlex Deucher offset += size; 277c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 278aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 279aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 280aaa36a97SAlex Deucher 281aaa36a97SAlex Deucher offset += size; 282c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 283c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 284aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 285aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 286549300ceSAlex Deucher 287549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 288549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 289549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 290aaa36a97SAlex Deucher } 291aaa36a97SAlex Deucher 292aaa36a97SAlex Deucher /** 293aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 294aaa36a97SAlex Deucher * 295aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 296aaa36a97SAlex Deucher * 297aaa36a97SAlex Deucher * Setup and start the UVD block 298aaa36a97SAlex Deucher */ 299aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 300aaa36a97SAlex Deucher { 301aaa36a97SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 302aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 303aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 304aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 305aaa36a97SAlex Deucher int i, j, r; 306aaa36a97SAlex Deucher 307aaa36a97SAlex Deucher /*disable DPG */ 308aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 309aaa36a97SAlex Deucher 310aaa36a97SAlex Deucher /* disable byte swapping */ 311aaa36a97SAlex Deucher lmi_swap_cntl = 0; 312aaa36a97SAlex Deucher mp_swap_cntl = 0; 313aaa36a97SAlex Deucher 314aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 315aaa36a97SAlex Deucher 316aaa36a97SAlex Deucher /* disable clock gating */ 317aaa36a97SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 318aaa36a97SAlex Deucher 319aaa36a97SAlex Deucher /* disable interupt */ 320aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 321aaa36a97SAlex Deucher 322aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 323aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 324aaa36a97SAlex Deucher mdelay(1); 325aaa36a97SAlex Deucher 326aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 327aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 328aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 329aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 330aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 331aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 332aaa36a97SAlex Deucher mdelay(5); 333aaa36a97SAlex Deucher 334aaa36a97SAlex Deucher /* take UVD block out of reset */ 335aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 336aaa36a97SAlex Deucher mdelay(5); 337aaa36a97SAlex Deucher 338aaa36a97SAlex Deucher /* initialize UVD memory controller */ 339aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 340aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 341aaa36a97SAlex Deucher 342aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 343aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 344aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 345aaa36a97SAlex Deucher mp_swap_cntl = 0; 346aaa36a97SAlex Deucher #endif 347aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 348aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 349aaa36a97SAlex Deucher 350aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 351aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 352aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 353aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 354aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 355aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 356aaa36a97SAlex Deucher 357aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 358aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 359aaa36a97SAlex Deucher mdelay(5); 360aaa36a97SAlex Deucher 361aaa36a97SAlex Deucher /* enable VCPU clock */ 362aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 363aaa36a97SAlex Deucher 364aaa36a97SAlex Deucher /* enable UMC */ 365aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 366aaa36a97SAlex Deucher 367aaa36a97SAlex Deucher /* boot up the VCPU */ 368aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 369aaa36a97SAlex Deucher mdelay(10); 370aaa36a97SAlex Deucher 371aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 372aaa36a97SAlex Deucher uint32_t status; 373aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 374aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 375aaa36a97SAlex Deucher if (status & 2) 376aaa36a97SAlex Deucher break; 377aaa36a97SAlex Deucher mdelay(10); 378aaa36a97SAlex Deucher } 379aaa36a97SAlex Deucher r = 0; 380aaa36a97SAlex Deucher if (status & 2) 381aaa36a97SAlex Deucher break; 382aaa36a97SAlex Deucher 383aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 384aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 385aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 386aaa36a97SAlex Deucher mdelay(10); 387aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 388aaa36a97SAlex Deucher mdelay(10); 389aaa36a97SAlex Deucher r = -1; 390aaa36a97SAlex Deucher } 391aaa36a97SAlex Deucher 392aaa36a97SAlex Deucher if (r) { 393aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 394aaa36a97SAlex Deucher return r; 395aaa36a97SAlex Deucher } 396aaa36a97SAlex Deucher /* enable master interrupt */ 397aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 398aaa36a97SAlex Deucher 399aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 400aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 401aaa36a97SAlex Deucher 402aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 403aaa36a97SAlex Deucher tmp = 0; 404aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 405aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 406aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 407aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 408aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 409aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 410aaa36a97SAlex Deucher /* force RBC into idle state */ 411aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 412aaa36a97SAlex Deucher 413aaa36a97SAlex Deucher /* set the write pointer delay */ 414aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 415aaa36a97SAlex Deucher 416aaa36a97SAlex Deucher /* set the wb address */ 417aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 418aaa36a97SAlex Deucher 419aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 420aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 421aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 422aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 423aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 424aaa36a97SAlex Deucher 425aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 426aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 427aaa36a97SAlex Deucher 428aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 429aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 430aaa36a97SAlex Deucher 431aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 432aaa36a97SAlex Deucher 433aaa36a97SAlex Deucher return 0; 434aaa36a97SAlex Deucher } 435aaa36a97SAlex Deucher 436aaa36a97SAlex Deucher /** 437aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 438aaa36a97SAlex Deucher * 439aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 440aaa36a97SAlex Deucher * 441aaa36a97SAlex Deucher * stop the UVD block 442aaa36a97SAlex Deucher */ 443aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 444aaa36a97SAlex Deucher { 445aaa36a97SAlex Deucher /* force RBC into idle state */ 446aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 447aaa36a97SAlex Deucher 448aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 449aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 450aaa36a97SAlex Deucher mdelay(1); 451aaa36a97SAlex Deucher 452aaa36a97SAlex Deucher /* put VCPU into reset */ 453aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 454aaa36a97SAlex Deucher mdelay(5); 455aaa36a97SAlex Deucher 456aaa36a97SAlex Deucher /* disable VCPU clock */ 457aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 458aaa36a97SAlex Deucher 459aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 460aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 461aaa36a97SAlex Deucher } 462aaa36a97SAlex Deucher 463aaa36a97SAlex Deucher /** 464aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 465aaa36a97SAlex Deucher * 466aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 467aaa36a97SAlex Deucher * @fence: fence to emit 468aaa36a97SAlex Deucher * 469aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 470aaa36a97SAlex Deucher */ 471aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 472890ee23fSChunming Zhou unsigned flags) 473aaa36a97SAlex Deucher { 474890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 475aaa36a97SAlex Deucher 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 480aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 481aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 482aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 483aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 484aaa36a97SAlex Deucher 485aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 486aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 487aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 488aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 489aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 490aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 491aaa36a97SAlex Deucher } 492aaa36a97SAlex Deucher 493aaa36a97SAlex Deucher /** 494d5b4e25dSChristian König * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush 495d5b4e25dSChristian König * 496d5b4e25dSChristian König * @ring: amdgpu_ring pointer 497d5b4e25dSChristian König * 498d5b4e25dSChristian König * Emits an hdp flush. 499d5b4e25dSChristian König */ 500d5b4e25dSChristian König static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 501d5b4e25dSChristian König { 502d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 503d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 504d5b4e25dSChristian König } 505d5b4e25dSChristian König 506d5b4e25dSChristian König /** 507d5b4e25dSChristian König * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate 508d5b4e25dSChristian König * 509d5b4e25dSChristian König * @ring: amdgpu_ring pointer 510d5b4e25dSChristian König * 511d5b4e25dSChristian König * Emits an hdp invalidate. 512d5b4e25dSChristian König */ 513d5b4e25dSChristian König static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 514d5b4e25dSChristian König { 515d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 516d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 517d5b4e25dSChristian König } 518d5b4e25dSChristian König 519d5b4e25dSChristian König /** 520aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 521aaa36a97SAlex Deucher * 522aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 523aaa36a97SAlex Deucher * 524aaa36a97SAlex Deucher * Test if we can successfully write to the context register 525aaa36a97SAlex Deucher */ 526aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 527aaa36a97SAlex Deucher { 528aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 529aaa36a97SAlex Deucher uint32_t tmp = 0; 530aaa36a97SAlex Deucher unsigned i; 531aaa36a97SAlex Deucher int r; 532aaa36a97SAlex Deucher 533aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 534a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 535aaa36a97SAlex Deucher if (r) { 536aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 537aaa36a97SAlex Deucher ring->idx, r); 538aaa36a97SAlex Deucher return r; 539aaa36a97SAlex Deucher } 540aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 541aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 542a27de35cSChristian König amdgpu_ring_commit(ring); 543aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 544aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 545aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 546aaa36a97SAlex Deucher break; 547aaa36a97SAlex Deucher DRM_UDELAY(1); 548aaa36a97SAlex Deucher } 549aaa36a97SAlex Deucher 550aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 551aaa36a97SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 552aaa36a97SAlex Deucher ring->idx, i); 553aaa36a97SAlex Deucher } else { 554aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 555aaa36a97SAlex Deucher ring->idx, tmp); 556aaa36a97SAlex Deucher r = -EINVAL; 557aaa36a97SAlex Deucher } 558aaa36a97SAlex Deucher return r; 559aaa36a97SAlex Deucher } 560aaa36a97SAlex Deucher 561aaa36a97SAlex Deucher /** 562aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 563aaa36a97SAlex Deucher * 564aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 565aaa36a97SAlex Deucher * @ib: indirect buffer to execute 566aaa36a97SAlex Deucher * 567aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 568aaa36a97SAlex Deucher */ 569aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 570d88bf583SChristian König struct amdgpu_ib *ib, 571d88bf583SChristian König unsigned vm_id, bool ctx_switch) 572aaa36a97SAlex Deucher { 573aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 574aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 575aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 576aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 577aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 578aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 579aaa36a97SAlex Deucher } 580aaa36a97SAlex Deucher 5815fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 582aaa36a97SAlex Deucher { 5835fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5845fc3aeebSyanyang1 585aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 586aaa36a97SAlex Deucher } 587aaa36a97SAlex Deucher 5885fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 589aaa36a97SAlex Deucher { 590aaa36a97SAlex Deucher unsigned i; 5915fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 592aaa36a97SAlex Deucher 593aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 594aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 595aaa36a97SAlex Deucher return 0; 596aaa36a97SAlex Deucher } 597aaa36a97SAlex Deucher return -ETIMEDOUT; 598aaa36a97SAlex Deucher } 599aaa36a97SAlex Deucher 6005fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 601aaa36a97SAlex Deucher { 6025fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6035fc3aeebSyanyang1 604aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 605aaa36a97SAlex Deucher 606aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 607aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 608aaa36a97SAlex Deucher mdelay(5); 609aaa36a97SAlex Deucher 610aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 611aaa36a97SAlex Deucher } 612aaa36a97SAlex Deucher 613aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 614aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 615aaa36a97SAlex Deucher unsigned type, 616aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 617aaa36a97SAlex Deucher { 618aaa36a97SAlex Deucher // TODO 619aaa36a97SAlex Deucher return 0; 620aaa36a97SAlex Deucher } 621aaa36a97SAlex Deucher 622aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 623aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 624aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 625aaa36a97SAlex Deucher { 626aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 627aaa36a97SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 628aaa36a97SAlex Deucher return 0; 629aaa36a97SAlex Deucher } 630aaa36a97SAlex Deucher 631be3ecca7STom St Denis static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 632be3ecca7STom St Denis { 633be3ecca7STom St Denis uint32_t data, data1, data2, suvd_flags; 634be3ecca7STom St Denis 635be3ecca7STom St Denis data = RREG32(mmUVD_CGC_CTRL); 636be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 637be3ecca7STom St Denis data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 638be3ecca7STom St Denis 639be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 640be3ecca7STom St Denis UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 641be3ecca7STom St Denis 642be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 643be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 644be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 645be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 646be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 647be3ecca7STom St Denis 648be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 649be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 650be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 651be3ecca7STom St Denis 652be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 653be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 654be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 655be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 656be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 657be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 658be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 659be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 660be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 661be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 662be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 663be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 664be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 665be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 666be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 667be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 668be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 669be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 670be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 671be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 672be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 673be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 674be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 675be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 676be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 677be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 678be3ecca7STom St Denis data1 |= suvd_flags; 679be3ecca7STom St Denis 680be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 681be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, 0); 682be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 683be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 684be3ecca7STom St Denis } 685be3ecca7STom St Denis 686be3ecca7STom St Denis #if 0 687be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 688be3ecca7STom St Denis { 689be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 690be3ecca7STom St Denis 691be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 692be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 693be3ecca7STom St Denis 694be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 695be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 696be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 697be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 698be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 699be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 700be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 701be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 702be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 703be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 704be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 705be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 706be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 707be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 708be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 709be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 710be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 711be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 712be3ecca7STom St Denis 713be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 714be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 715be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 716be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 717be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 718be3ecca7STom St Denis 719be3ecca7STom St Denis data |= cgc_flags; 720be3ecca7STom St Denis data1 |= suvd_flags; 721be3ecca7STom St Denis 722be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 723be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 724be3ecca7STom St Denis } 725be3ecca7STom St Denis #endif 726be3ecca7STom St Denis 7274be5097cSRex Zhu static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 7284be5097cSRex Zhu { 7294be5097cSRex Zhu u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 7304be5097cSRex Zhu 7314be5097cSRex Zhu if (enable) 7324be5097cSRex Zhu tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 7334be5097cSRex Zhu GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 7344be5097cSRex Zhu else 7354be5097cSRex Zhu tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 7364be5097cSRex Zhu GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 7374be5097cSRex Zhu 7384be5097cSRex Zhu WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 7394be5097cSRex Zhu } 7404be5097cSRex Zhu 7415fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7425fc3aeebSyanyang1 enum amd_clockgating_state state) 743aaa36a97SAlex Deucher { 74435e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 745be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 746be3ecca7STom St Denis static int curstate = -1; 74735e5912dSAlex Deucher 7484be5097cSRex Zhu uvd_v5_0_set_bypass_mode(adev, enable); 7494be5097cSRex Zhu 750e3b04bc7SAlex Deucher if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 75135e5912dSAlex Deucher return 0; 75235e5912dSAlex Deucher 753be3ecca7STom St Denis if (curstate == state) 754be3ecca7STom St Denis return 0; 755be3ecca7STom St Denis 756be3ecca7STom St Denis curstate = state; 757be3ecca7STom St Denis if (enable) { 758be3ecca7STom St Denis /* disable HW gating and enable Sw gating */ 759be3ecca7STom St Denis uvd_v5_0_set_sw_clock_gating(adev); 760be3ecca7STom St Denis } else { 761be3ecca7STom St Denis /* wait for STATUS to clear */ 762be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 763be3ecca7STom St Denis return -EBUSY; 764be3ecca7STom St Denis 765be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 766be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 767be3ecca7STom St Denis } 768be3ecca7STom St Denis 769aaa36a97SAlex Deucher return 0; 770aaa36a97SAlex Deucher } 771aaa36a97SAlex Deucher 7725fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 7735fc3aeebSyanyang1 enum amd_powergating_state state) 774aaa36a97SAlex Deucher { 775aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 776aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 777aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 778aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 779aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 780aaa36a97SAlex Deucher * the smc and the hw blocks 781aaa36a97SAlex Deucher */ 7825fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7835fc3aeebSyanyang1 784e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 785b6df77fcSAlex Deucher return 0; 786b6df77fcSAlex Deucher 7875fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 788aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 789aaa36a97SAlex Deucher return 0; 790aaa36a97SAlex Deucher } else { 791aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 792aaa36a97SAlex Deucher } 793aaa36a97SAlex Deucher } 794aaa36a97SAlex Deucher 795a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 79688a907d6STom St Denis .name = "uvd_v5_0", 797aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 798aaa36a97SAlex Deucher .late_init = NULL, 799aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 800aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 801aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 802aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 803aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 804aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 805aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 806aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 807aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 808aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 809aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 810aaa36a97SAlex Deucher }; 811aaa36a97SAlex Deucher 812aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 81321cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 81479887142SChristian König .align_mask = 0xf, 81579887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 816aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 817aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 818aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 819aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 820e12f3d7aSChristian König .emit_frame_size = 821e12f3d7aSChristian König 2 + /* uvd_v5_0_ring_emit_hdp_flush */ 822e12f3d7aSChristian König 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ 823e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 824e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 825aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 826aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 827d5b4e25dSChristian König .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, 828d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate, 829aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8308de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 831edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 8329e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 833c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 834c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 835aaa36a97SAlex Deucher }; 836aaa36a97SAlex Deucher 837aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 838aaa36a97SAlex Deucher { 839aaa36a97SAlex Deucher adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; 840aaa36a97SAlex Deucher } 841aaa36a97SAlex Deucher 842aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 843aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 844aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 845aaa36a97SAlex Deucher }; 846aaa36a97SAlex Deucher 847aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 848aaa36a97SAlex Deucher { 849aaa36a97SAlex Deucher adev->uvd.irq.num_types = 1; 850aaa36a97SAlex Deucher adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 851aaa36a97SAlex Deucher } 852a1255107SAlex Deucher 853a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 854a1255107SAlex Deucher { 855a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 856a1255107SAlex Deucher .major = 5, 857a1255107SAlex Deucher .minor = 0, 858a1255107SAlex Deucher .rev = 0, 859a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 860a1255107SAlex Deucher }; 861