1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 35be3ecca7STom St Denis #include "vi.h" 364be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 38091aec0bSAndrey Grodzovsky #include "ivsrcid/ivsrcid_vislands30.h" 39aaa36a97SAlex Deucher 40aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 41aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 43aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 44809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 45809a6a62SRex Zhu enum amd_clockgating_state state); 46809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 47809a6a62SRex Zhu bool enable); 48aaa36a97SAlex Deucher /** 49aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 50aaa36a97SAlex Deucher * 51aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 52aaa36a97SAlex Deucher * 53aaa36a97SAlex Deucher * Returns the current hardware read pointer 54aaa36a97SAlex Deucher */ 55536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 56aaa36a97SAlex Deucher { 57aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 58aaa36a97SAlex Deucher 59aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 60aaa36a97SAlex Deucher } 61aaa36a97SAlex Deucher 62aaa36a97SAlex Deucher /** 63aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 64aaa36a97SAlex Deucher * 65aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 66aaa36a97SAlex Deucher * 67aaa36a97SAlex Deucher * Returns the current hardware write pointer 68aaa36a97SAlex Deucher */ 69536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 70aaa36a97SAlex Deucher { 71aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 72aaa36a97SAlex Deucher 73aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 74aaa36a97SAlex Deucher } 75aaa36a97SAlex Deucher 76aaa36a97SAlex Deucher /** 77aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 78aaa36a97SAlex Deucher * 79aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 80aaa36a97SAlex Deucher * 81aaa36a97SAlex Deucher * Commits the write pointer to the hardware 82aaa36a97SAlex Deucher */ 83aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 84aaa36a97SAlex Deucher { 85aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 86aaa36a97SAlex Deucher 87536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 88aaa36a97SAlex Deucher } 89aaa36a97SAlex Deucher 905fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 91aaa36a97SAlex Deucher { 925fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 932bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 945fc3aeebSyanyang1 95aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 96aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 97aaa36a97SAlex Deucher 98aaa36a97SAlex Deucher return 0; 99aaa36a97SAlex Deucher } 100aaa36a97SAlex Deucher 1015fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 102aaa36a97SAlex Deucher { 103aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1045fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 105aaa36a97SAlex Deucher int r; 106aaa36a97SAlex Deucher 107aaa36a97SAlex Deucher /* UVD TRAP */ 108091aec0bSAndrey Grodzovsky r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 109aaa36a97SAlex Deucher if (r) 110aaa36a97SAlex Deucher return r; 111aaa36a97SAlex Deucher 112aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 113aaa36a97SAlex Deucher if (r) 114aaa36a97SAlex Deucher return r; 115aaa36a97SAlex Deucher 116aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 117aaa36a97SAlex Deucher if (r) 118aaa36a97SAlex Deucher return r; 119aaa36a97SAlex Deucher 1202bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 121aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 1222bb795f5SJames Zhu r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 12333d5bd07SEmily Deng if (r) 12433d5bd07SEmily Deng return r; 12533d5bd07SEmily Deng 12633d5bd07SEmily Deng r = amdgpu_uvd_entity_init(adev); 127aaa36a97SAlex Deucher 128aaa36a97SAlex Deucher return r; 129aaa36a97SAlex Deucher } 130aaa36a97SAlex Deucher 1315fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 132aaa36a97SAlex Deucher { 133aaa36a97SAlex Deucher int r; 1345fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 135aaa36a97SAlex Deucher 136aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 137aaa36a97SAlex Deucher if (r) 138aaa36a97SAlex Deucher return r; 139aaa36a97SAlex Deucher 14050237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 141aaa36a97SAlex Deucher } 142aaa36a97SAlex Deucher 143aaa36a97SAlex Deucher /** 144aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 145aaa36a97SAlex Deucher * 146aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 147aaa36a97SAlex Deucher * 148aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 149aaa36a97SAlex Deucher */ 1505fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 151aaa36a97SAlex Deucher { 1525fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1532bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 154aaa36a97SAlex Deucher uint32_t tmp; 155aaa36a97SAlex Deucher int r; 156aaa36a97SAlex Deucher 157e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 158e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 159e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 160aaa36a97SAlex Deucher 161aaa36a97SAlex Deucher ring->ready = true; 162aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 163aaa36a97SAlex Deucher if (r) { 164aaa36a97SAlex Deucher ring->ready = false; 165aaa36a97SAlex Deucher goto done; 166aaa36a97SAlex Deucher } 167aaa36a97SAlex Deucher 168a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 169aaa36a97SAlex Deucher if (r) { 170aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 171aaa36a97SAlex Deucher goto done; 172aaa36a97SAlex Deucher } 173aaa36a97SAlex Deucher 174aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 176aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 177aaa36a97SAlex Deucher 178aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 180aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 181aaa36a97SAlex Deucher 182aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 184aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 185aaa36a97SAlex Deucher 186aaa36a97SAlex Deucher /* Clear timeout status bits */ 187aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 188aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 189aaa36a97SAlex Deucher 190aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 191aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 192aaa36a97SAlex Deucher 193a27de35cSChristian König amdgpu_ring_commit(ring); 194e3e672e6SRex Zhu 195aaa36a97SAlex Deucher done: 196aaa36a97SAlex Deucher if (!r) 197aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 198aaa36a97SAlex Deucher 199aaa36a97SAlex Deucher return r; 200e3e672e6SRex Zhu 201aaa36a97SAlex Deucher } 202aaa36a97SAlex Deucher 203aaa36a97SAlex Deucher /** 204aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 205aaa36a97SAlex Deucher * 206aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 207aaa36a97SAlex Deucher * 208aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 209aaa36a97SAlex Deucher */ 2105fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 211aaa36a97SAlex Deucher { 2125fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2132bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 214aaa36a97SAlex Deucher 215e3e672e6SRex Zhu if (RREG32(mmUVD_STATUS) != 0) 216aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 217e3e672e6SRex Zhu 218aaa36a97SAlex Deucher ring->ready = false; 219aaa36a97SAlex Deucher 220aaa36a97SAlex Deucher return 0; 221aaa36a97SAlex Deucher } 222aaa36a97SAlex Deucher 2235fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 224aaa36a97SAlex Deucher { 225aaa36a97SAlex Deucher int r; 2265fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 227aaa36a97SAlex Deucher 2283f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 229aaa36a97SAlex Deucher if (r) 230aaa36a97SAlex Deucher return r; 231809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 232aaa36a97SAlex Deucher 23350237287SRex Zhu return amdgpu_uvd_suspend(adev); 234aaa36a97SAlex Deucher } 235aaa36a97SAlex Deucher 2365fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 237aaa36a97SAlex Deucher { 238aaa36a97SAlex Deucher int r; 2395fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 240aaa36a97SAlex Deucher 241aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 242aaa36a97SAlex Deucher if (r) 243aaa36a97SAlex Deucher return r; 244aaa36a97SAlex Deucher 24550237287SRex Zhu return uvd_v5_0_hw_init(adev); 246aaa36a97SAlex Deucher } 247aaa36a97SAlex Deucher 248aaa36a97SAlex Deucher /** 249aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 250aaa36a97SAlex Deucher * 251aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 252aaa36a97SAlex Deucher * 253aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 254aaa36a97SAlex Deucher */ 255aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 256aaa36a97SAlex Deucher { 257aaa36a97SAlex Deucher uint64_t offset; 258aaa36a97SAlex Deucher uint32_t size; 259aaa36a97SAlex Deucher 260aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 261aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 2622bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr)); 263aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 2642bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr)); 265aaa36a97SAlex Deucher 266aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 267c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 268aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 269aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 270aaa36a97SAlex Deucher 271aaa36a97SAlex Deucher offset += size; 272c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 273aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 274aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 275aaa36a97SAlex Deucher 276aaa36a97SAlex Deucher offset += size; 277c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 278c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 279aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 280aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 281549300ceSAlex Deucher 282549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 283549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 284549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 285aaa36a97SAlex Deucher } 286aaa36a97SAlex Deucher 287aaa36a97SAlex Deucher /** 288aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 289aaa36a97SAlex Deucher * 290aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 291aaa36a97SAlex Deucher * 292aaa36a97SAlex Deucher * Setup and start the UVD block 293aaa36a97SAlex Deucher */ 294aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 295aaa36a97SAlex Deucher { 2962bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 297aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 298aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 299aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 300aaa36a97SAlex Deucher int i, j, r; 301aaa36a97SAlex Deucher 302aaa36a97SAlex Deucher /*disable DPG */ 303aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 304aaa36a97SAlex Deucher 305aaa36a97SAlex Deucher /* disable byte swapping */ 306aaa36a97SAlex Deucher lmi_swap_cntl = 0; 307aaa36a97SAlex Deucher mp_swap_cntl = 0; 308aaa36a97SAlex Deucher 309aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 310aaa36a97SAlex Deucher 311aaa36a97SAlex Deucher /* disable interupt */ 312aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 313aaa36a97SAlex Deucher 314aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 315aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 316aaa36a97SAlex Deucher mdelay(1); 317aaa36a97SAlex Deucher 318aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 319aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 320aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 321aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 322aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 323aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 324aaa36a97SAlex Deucher mdelay(5); 325aaa36a97SAlex Deucher 326aaa36a97SAlex Deucher /* take UVD block out of reset */ 327aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 328aaa36a97SAlex Deucher mdelay(5); 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher /* initialize UVD memory controller */ 331aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 332aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 333aaa36a97SAlex Deucher 334aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 335aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 336aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 337aaa36a97SAlex Deucher mp_swap_cntl = 0; 338aaa36a97SAlex Deucher #endif 339aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 340aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 341aaa36a97SAlex Deucher 342aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 343aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 344aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 345aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 346aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 347aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 348aaa36a97SAlex Deucher 349aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 350aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 351aaa36a97SAlex Deucher mdelay(5); 352aaa36a97SAlex Deucher 353aaa36a97SAlex Deucher /* enable VCPU clock */ 354aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 355aaa36a97SAlex Deucher 356aaa36a97SAlex Deucher /* enable UMC */ 357aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 358aaa36a97SAlex Deucher 359aaa36a97SAlex Deucher /* boot up the VCPU */ 360aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 361aaa36a97SAlex Deucher mdelay(10); 362aaa36a97SAlex Deucher 363aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 364aaa36a97SAlex Deucher uint32_t status; 365aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 366aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 367aaa36a97SAlex Deucher if (status & 2) 368aaa36a97SAlex Deucher break; 369aaa36a97SAlex Deucher mdelay(10); 370aaa36a97SAlex Deucher } 371aaa36a97SAlex Deucher r = 0; 372aaa36a97SAlex Deucher if (status & 2) 373aaa36a97SAlex Deucher break; 374aaa36a97SAlex Deucher 375aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 376aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 377aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 378aaa36a97SAlex Deucher mdelay(10); 379aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 380aaa36a97SAlex Deucher mdelay(10); 381aaa36a97SAlex Deucher r = -1; 382aaa36a97SAlex Deucher } 383aaa36a97SAlex Deucher 384aaa36a97SAlex Deucher if (r) { 385aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 386aaa36a97SAlex Deucher return r; 387aaa36a97SAlex Deucher } 388aaa36a97SAlex Deucher /* enable master interrupt */ 389aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 390aaa36a97SAlex Deucher 391aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 392aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 393aaa36a97SAlex Deucher 394aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 395aaa36a97SAlex Deucher tmp = 0; 396aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 397aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 398aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 399aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 400aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 401aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 402aaa36a97SAlex Deucher /* force RBC into idle state */ 403aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 404aaa36a97SAlex Deucher 405aaa36a97SAlex Deucher /* set the write pointer delay */ 406aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 407aaa36a97SAlex Deucher 408aaa36a97SAlex Deucher /* set the wb address */ 409aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 410aaa36a97SAlex Deucher 411aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 412aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 413aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 414aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 415aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 416aaa36a97SAlex Deucher 417aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 418aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 419aaa36a97SAlex Deucher 420aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 421536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 422aaa36a97SAlex Deucher 423aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 424aaa36a97SAlex Deucher 425aaa36a97SAlex Deucher return 0; 426aaa36a97SAlex Deucher } 427aaa36a97SAlex Deucher 428aaa36a97SAlex Deucher /** 429aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 430aaa36a97SAlex Deucher * 431aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 432aaa36a97SAlex Deucher * 433aaa36a97SAlex Deucher * stop the UVD block 434aaa36a97SAlex Deucher */ 435aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 436aaa36a97SAlex Deucher { 437aaa36a97SAlex Deucher /* force RBC into idle state */ 438aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 439aaa36a97SAlex Deucher 440aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 441aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 442aaa36a97SAlex Deucher mdelay(1); 443aaa36a97SAlex Deucher 444aaa36a97SAlex Deucher /* put VCPU into reset */ 445aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 446aaa36a97SAlex Deucher mdelay(5); 447aaa36a97SAlex Deucher 448aaa36a97SAlex Deucher /* disable VCPU clock */ 449aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 450aaa36a97SAlex Deucher 451aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 452aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 453e3e672e6SRex Zhu 454e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 455aaa36a97SAlex Deucher } 456aaa36a97SAlex Deucher 457aaa36a97SAlex Deucher /** 458aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 459aaa36a97SAlex Deucher * 460aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 461aaa36a97SAlex Deucher * @fence: fence to emit 462aaa36a97SAlex Deucher * 463aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 464aaa36a97SAlex Deucher */ 465aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 466890ee23fSChunming Zhou unsigned flags) 467aaa36a97SAlex Deucher { 468890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 469aaa36a97SAlex Deucher 470aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 471aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 472aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 473aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 478aaa36a97SAlex Deucher 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 480aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 481aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 482aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 483aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 484aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 485aaa36a97SAlex Deucher } 486aaa36a97SAlex Deucher 487aaa36a97SAlex Deucher /** 488aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 489aaa36a97SAlex Deucher * 490aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 491aaa36a97SAlex Deucher * 492aaa36a97SAlex Deucher * Test if we can successfully write to the context register 493aaa36a97SAlex Deucher */ 494aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 495aaa36a97SAlex Deucher { 496aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 497aaa36a97SAlex Deucher uint32_t tmp = 0; 498aaa36a97SAlex Deucher unsigned i; 499aaa36a97SAlex Deucher int r; 500aaa36a97SAlex Deucher 501aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 502a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 503aaa36a97SAlex Deucher if (r) { 504aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 505aaa36a97SAlex Deucher ring->idx, r); 506aaa36a97SAlex Deucher return r; 507aaa36a97SAlex Deucher } 508aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 509aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 510a27de35cSChristian König amdgpu_ring_commit(ring); 511aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 512aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 513aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 514aaa36a97SAlex Deucher break; 515aaa36a97SAlex Deucher DRM_UDELAY(1); 516aaa36a97SAlex Deucher } 517aaa36a97SAlex Deucher 518aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 5199953b72fSpding DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 520aaa36a97SAlex Deucher ring->idx, i); 521aaa36a97SAlex Deucher } else { 522aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 523aaa36a97SAlex Deucher ring->idx, tmp); 524aaa36a97SAlex Deucher r = -EINVAL; 525aaa36a97SAlex Deucher } 526aaa36a97SAlex Deucher return r; 527aaa36a97SAlex Deucher } 528aaa36a97SAlex Deucher 529aaa36a97SAlex Deucher /** 530aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 531aaa36a97SAlex Deucher * 532aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 533aaa36a97SAlex Deucher * @ib: indirect buffer to execute 534aaa36a97SAlex Deucher * 535aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 536aaa36a97SAlex Deucher */ 537aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 538d88bf583SChristian König struct amdgpu_ib *ib, 539c4f46f22SChristian König unsigned vmid, bool ctx_switch) 540aaa36a97SAlex Deucher { 541aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 542aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 543aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 544aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 545aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 546aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 547aaa36a97SAlex Deucher } 548aaa36a97SAlex Deucher 5490232e306SLeo Liu static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 5500232e306SLeo Liu { 5510232e306SLeo Liu int i; 5520232e306SLeo Liu 5530232e306SLeo Liu WARN_ON(ring->wptr % 2 || count % 2); 5540232e306SLeo Liu 5550232e306SLeo Liu for (i = 0; i < count / 2; i++) { 5560232e306SLeo Liu amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 5570232e306SLeo Liu amdgpu_ring_write(ring, 0); 5580232e306SLeo Liu } 5590232e306SLeo Liu } 5600232e306SLeo Liu 5615fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 562aaa36a97SAlex Deucher { 5635fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5645fc3aeebSyanyang1 565aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 566aaa36a97SAlex Deucher } 567aaa36a97SAlex Deucher 5685fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 569aaa36a97SAlex Deucher { 570aaa36a97SAlex Deucher unsigned i; 5715fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 572aaa36a97SAlex Deucher 573aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 574aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 575aaa36a97SAlex Deucher return 0; 576aaa36a97SAlex Deucher } 577aaa36a97SAlex Deucher return -ETIMEDOUT; 578aaa36a97SAlex Deucher } 579aaa36a97SAlex Deucher 5805fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 581aaa36a97SAlex Deucher { 5825fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5835fc3aeebSyanyang1 584aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 585aaa36a97SAlex Deucher 586aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 587aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 588aaa36a97SAlex Deucher mdelay(5); 589aaa36a97SAlex Deucher 590aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 591aaa36a97SAlex Deucher } 592aaa36a97SAlex Deucher 593aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 594aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 595aaa36a97SAlex Deucher unsigned type, 596aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 597aaa36a97SAlex Deucher { 598aaa36a97SAlex Deucher // TODO 599aaa36a97SAlex Deucher return 0; 600aaa36a97SAlex Deucher } 601aaa36a97SAlex Deucher 602aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 603aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 604aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 605aaa36a97SAlex Deucher { 606aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 6072bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 608aaa36a97SAlex Deucher return 0; 609aaa36a97SAlex Deucher } 610aaa36a97SAlex Deucher 611809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 612be3ecca7STom St Denis { 613809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 614be3ecca7STom St Denis 615be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 616809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 617be3ecca7STom St Denis 618be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 619be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 620be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 621be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 622be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 623be3ecca7STom St Denis 624809a6a62SRex Zhu if (enable) { 625809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 626809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 627809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 628809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 629809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 630809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 631809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 632809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 633809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 634809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 635809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 636809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 637809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 638809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 639809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 640809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 641809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 642809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6433c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6443c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6453c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 646809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 647809a6a62SRex Zhu data1 |= suvd_flags; 648809a6a62SRex Zhu } else { 649809a6a62SRex Zhu data3 = 0; 650809a6a62SRex Zhu data1 = 0; 651809a6a62SRex Zhu } 652809a6a62SRex Zhu 653809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 654809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 655809a6a62SRex Zhu } 656809a6a62SRex Zhu 657809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 658809a6a62SRex Zhu { 659809a6a62SRex Zhu uint32_t data, data2; 660809a6a62SRex Zhu 661809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 662809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 663809a6a62SRex Zhu 664809a6a62SRex Zhu 665809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 666809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 667809a6a62SRex Zhu 668809a6a62SRex Zhu 669be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 670be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 671be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 672be3ecca7STom St Denis 673be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 674be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 675be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 676be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 677be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 678be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 679be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 680be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 681be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 682be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 683be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 684be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 685be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 686be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 687be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 688be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 689be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 690be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 691be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 692be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 693be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 694be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 695be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 696be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 697be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 698be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 699be3ecca7STom St Denis 700be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 701be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 702be3ecca7STom St Denis } 703be3ecca7STom St Denis 704be3ecca7STom St Denis #if 0 705be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 706be3ecca7STom St Denis { 707be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 708be3ecca7STom St Denis 709be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 710be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 711be3ecca7STom St Denis 712be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 713be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 714be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 715be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 716be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 717be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 718be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 719be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 720be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 721be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 722be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 723be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 724be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 725be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 726be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 727be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 728be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 729be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 730be3ecca7STom St Denis 731be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 732be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 733be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 734be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 735be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 736be3ecca7STom St Denis 737be3ecca7STom St Denis data |= cgc_flags; 738be3ecca7STom St Denis data1 |= suvd_flags; 739be3ecca7STom St Denis 740be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 741be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 742be3ecca7STom St Denis } 743be3ecca7STom St Denis #endif 744be3ecca7STom St Denis 745809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 746809a6a62SRex Zhu bool enable) 747809a6a62SRex Zhu { 748809a6a62SRex Zhu u32 orig, data; 749809a6a62SRex Zhu 750809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 751809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 752809a6a62SRex Zhu data |= 0xfff; 753809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 754809a6a62SRex Zhu 755809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 756809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 757809a6a62SRex Zhu if (orig != data) 758809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 759809a6a62SRex Zhu } else { 760809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 761809a6a62SRex Zhu data &= ~0xfff; 762809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 763809a6a62SRex Zhu 764809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 765809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 766809a6a62SRex Zhu if (orig != data) 767809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 768809a6a62SRex Zhu } 769809a6a62SRex Zhu } 7704be5097cSRex Zhu 7715fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7725fc3aeebSyanyang1 enum amd_clockgating_state state) 773aaa36a97SAlex Deucher { 77435e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 775be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 77635e5912dSAlex Deucher 777be3ecca7STom St Denis if (enable) { 778be3ecca7STom St Denis /* wait for STATUS to clear */ 779be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 780be3ecca7STom St Denis return -EBUSY; 781809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 782be3ecca7STom St Denis 783be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 784be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 785809a6a62SRex Zhu } else { 786809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 787be3ecca7STom St Denis } 788be3ecca7STom St Denis 789809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 790aaa36a97SAlex Deucher return 0; 791aaa36a97SAlex Deucher } 792aaa36a97SAlex Deucher 7935fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 7945fc3aeebSyanyang1 enum amd_powergating_state state) 795aaa36a97SAlex Deucher { 796aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 797aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 798aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 799aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 800aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 801aaa36a97SAlex Deucher * the smc and the hw blocks 802aaa36a97SAlex Deucher */ 8035fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 804c8781f56SHuang Rui int ret = 0; 8055fc3aeebSyanyang1 8065fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 807aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 808aaa36a97SAlex Deucher } else { 809c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 810c8781f56SHuang Rui if (ret) 811c8781f56SHuang Rui goto out; 812aaa36a97SAlex Deucher } 813c8781f56SHuang Rui 814c8781f56SHuang Rui out: 815c8781f56SHuang Rui return ret; 816c8781f56SHuang Rui } 817c8781f56SHuang Rui 818c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 819c8781f56SHuang Rui { 820c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 821c8781f56SHuang Rui int data; 822c8781f56SHuang Rui 823c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 824c8781f56SHuang Rui 825254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 826254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 827c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 828c8781f56SHuang Rui goto out; 829c8781f56SHuang Rui } 830c8781f56SHuang Rui 831c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 832c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 833c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 834c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 835c8781f56SHuang Rui 836c8781f56SHuang Rui out: 837c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 838aaa36a97SAlex Deucher } 839aaa36a97SAlex Deucher 840a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 84188a907d6STom St Denis .name = "uvd_v5_0", 842aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 843aaa36a97SAlex Deucher .late_init = NULL, 844aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 845aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 846aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 847aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 848aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 849aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 850aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 851aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 852aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 853aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 854aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 855c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 856aaa36a97SAlex Deucher }; 857aaa36a97SAlex Deucher 858aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 85921cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 86079887142SChristian König .align_mask = 0xf, 861536fbf94SKen Wang .support_64bit_ptrs = false, 862aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 863aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 864aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 865aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 866e12f3d7aSChristian König .emit_frame_size = 867e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 868e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 869aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 870aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 871aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8728de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 8730232e306SLeo Liu .insert_nop = uvd_v5_0_ring_insert_nop, 8749e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 875c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 876c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 877aaa36a97SAlex Deucher }; 878aaa36a97SAlex Deucher 879aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 880aaa36a97SAlex Deucher { 8812bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 882aaa36a97SAlex Deucher } 883aaa36a97SAlex Deucher 884aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 885aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 886aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 887aaa36a97SAlex Deucher }; 888aaa36a97SAlex Deucher 889aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 890aaa36a97SAlex Deucher { 8912bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 8922bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 893aaa36a97SAlex Deucher } 894a1255107SAlex Deucher 895a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 896a1255107SAlex Deucher { 897a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 898a1255107SAlex Deucher .major = 5, 899a1255107SAlex Deucher .minor = 0, 900a1255107SAlex Deucher .rev = 0, 901a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 902a1255107SAlex Deucher }; 903