1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25aaa36a97SAlex Deucher #include <linux/firmware.h> 26aaa36a97SAlex Deucher #include <drm/drmP.h> 27aaa36a97SAlex Deucher #include "amdgpu.h" 28aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 29aaa36a97SAlex Deucher #include "vid.h" 30aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 32aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 34d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 35be3ecca7STom St Denis #include "vi.h" 364be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 38aaa36a97SAlex Deucher 39aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 40aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 41aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 43809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 44809a6a62SRex Zhu enum amd_clockgating_state state); 45809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 46809a6a62SRex Zhu bool enable); 47aaa36a97SAlex Deucher /** 48aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 49aaa36a97SAlex Deucher * 50aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 51aaa36a97SAlex Deucher * 52aaa36a97SAlex Deucher * Returns the current hardware read pointer 53aaa36a97SAlex Deucher */ 54536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 55aaa36a97SAlex Deucher { 56aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 57aaa36a97SAlex Deucher 58aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 59aaa36a97SAlex Deucher } 60aaa36a97SAlex Deucher 61aaa36a97SAlex Deucher /** 62aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 63aaa36a97SAlex Deucher * 64aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 65aaa36a97SAlex Deucher * 66aaa36a97SAlex Deucher * Returns the current hardware write pointer 67aaa36a97SAlex Deucher */ 68536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 69aaa36a97SAlex Deucher { 70aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 71aaa36a97SAlex Deucher 72aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 73aaa36a97SAlex Deucher } 74aaa36a97SAlex Deucher 75aaa36a97SAlex Deucher /** 76aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 77aaa36a97SAlex Deucher * 78aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 79aaa36a97SAlex Deucher * 80aaa36a97SAlex Deucher * Commits the write pointer to the hardware 81aaa36a97SAlex Deucher */ 82aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 83aaa36a97SAlex Deucher { 84aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 85aaa36a97SAlex Deucher 86536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 87aaa36a97SAlex Deucher } 88aaa36a97SAlex Deucher 895fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 90aaa36a97SAlex Deucher { 915fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 922bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 935fc3aeebSyanyang1 94aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 95aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 96aaa36a97SAlex Deucher 97aaa36a97SAlex Deucher return 0; 98aaa36a97SAlex Deucher } 99aaa36a97SAlex Deucher 1005fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 101aaa36a97SAlex Deucher { 102aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1035fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 104aaa36a97SAlex Deucher int r; 105aaa36a97SAlex Deucher 106aaa36a97SAlex Deucher /* UVD TRAP */ 1072bb795f5SJames Zhu r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 108aaa36a97SAlex Deucher if (r) 109aaa36a97SAlex Deucher return r; 110aaa36a97SAlex Deucher 111aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 112aaa36a97SAlex Deucher if (r) 113aaa36a97SAlex Deucher return r; 114aaa36a97SAlex Deucher 115aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 116aaa36a97SAlex Deucher if (r) 117aaa36a97SAlex Deucher return r; 118aaa36a97SAlex Deucher 1192bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 120aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 1212bb795f5SJames Zhu r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 122aaa36a97SAlex Deucher 123aaa36a97SAlex Deucher return r; 124aaa36a97SAlex Deucher } 125aaa36a97SAlex Deucher 1265fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 127aaa36a97SAlex Deucher { 128aaa36a97SAlex Deucher int r; 1295fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 130aaa36a97SAlex Deucher 131aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 132aaa36a97SAlex Deucher if (r) 133aaa36a97SAlex Deucher return r; 134aaa36a97SAlex Deucher 13550237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 136aaa36a97SAlex Deucher } 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher /** 139aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 140aaa36a97SAlex Deucher * 141aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 142aaa36a97SAlex Deucher * 143aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 144aaa36a97SAlex Deucher */ 1455fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 146aaa36a97SAlex Deucher { 1475fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1482bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 149aaa36a97SAlex Deucher uint32_t tmp; 150aaa36a97SAlex Deucher int r; 151aaa36a97SAlex Deucher 152e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 153e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 154e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 155aaa36a97SAlex Deucher 156aaa36a97SAlex Deucher ring->ready = true; 157aaa36a97SAlex Deucher r = amdgpu_ring_test_ring(ring); 158aaa36a97SAlex Deucher if (r) { 159aaa36a97SAlex Deucher ring->ready = false; 160aaa36a97SAlex Deucher goto done; 161aaa36a97SAlex Deucher } 162aaa36a97SAlex Deucher 163a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 164aaa36a97SAlex Deucher if (r) { 165aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 166aaa36a97SAlex Deucher goto done; 167aaa36a97SAlex Deucher } 168aaa36a97SAlex Deucher 169aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 170aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 171aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 172aaa36a97SAlex Deucher 173aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176aaa36a97SAlex Deucher 177aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180aaa36a97SAlex Deucher 181aaa36a97SAlex Deucher /* Clear timeout status bits */ 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 184aaa36a97SAlex Deucher 185aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 187aaa36a97SAlex Deucher 188a27de35cSChristian König amdgpu_ring_commit(ring); 189e3e672e6SRex Zhu 190aaa36a97SAlex Deucher done: 191aaa36a97SAlex Deucher if (!r) 192aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 193aaa36a97SAlex Deucher 194aaa36a97SAlex Deucher return r; 195e3e672e6SRex Zhu 196aaa36a97SAlex Deucher } 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher /** 199aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 200aaa36a97SAlex Deucher * 201aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 202aaa36a97SAlex Deucher * 203aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 204aaa36a97SAlex Deucher */ 2055fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 206aaa36a97SAlex Deucher { 2075fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2082bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 209aaa36a97SAlex Deucher 210e3e672e6SRex Zhu if (RREG32(mmUVD_STATUS) != 0) 211aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 212e3e672e6SRex Zhu 213aaa36a97SAlex Deucher ring->ready = false; 214aaa36a97SAlex Deucher 215aaa36a97SAlex Deucher return 0; 216aaa36a97SAlex Deucher } 217aaa36a97SAlex Deucher 2185fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 219aaa36a97SAlex Deucher { 220aaa36a97SAlex Deucher int r; 2215fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 222aaa36a97SAlex Deucher 2233f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 224aaa36a97SAlex Deucher if (r) 225aaa36a97SAlex Deucher return r; 226809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 227aaa36a97SAlex Deucher 22850237287SRex Zhu return amdgpu_uvd_suspend(adev); 229aaa36a97SAlex Deucher } 230aaa36a97SAlex Deucher 2315fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 232aaa36a97SAlex Deucher { 233aaa36a97SAlex Deucher int r; 2345fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 235aaa36a97SAlex Deucher 236aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 237aaa36a97SAlex Deucher if (r) 238aaa36a97SAlex Deucher return r; 239aaa36a97SAlex Deucher 24050237287SRex Zhu return uvd_v5_0_hw_init(adev); 241aaa36a97SAlex Deucher } 242aaa36a97SAlex Deucher 243aaa36a97SAlex Deucher /** 244aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 245aaa36a97SAlex Deucher * 246aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 247aaa36a97SAlex Deucher * 248aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 249aaa36a97SAlex Deucher */ 250aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 251aaa36a97SAlex Deucher { 252aaa36a97SAlex Deucher uint64_t offset; 253aaa36a97SAlex Deucher uint32_t size; 254aaa36a97SAlex Deucher 255aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 256aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 2572bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr)); 258aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 2592bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr)); 260aaa36a97SAlex Deucher 261aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 262c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 263aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 264aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 265aaa36a97SAlex Deucher 266aaa36a97SAlex Deucher offset += size; 267c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 268aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 269aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 270aaa36a97SAlex Deucher 271aaa36a97SAlex Deucher offset += size; 272c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 273c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 274aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 275aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 276549300ceSAlex Deucher 277549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 278549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 279549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 280aaa36a97SAlex Deucher } 281aaa36a97SAlex Deucher 282aaa36a97SAlex Deucher /** 283aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 284aaa36a97SAlex Deucher * 285aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 286aaa36a97SAlex Deucher * 287aaa36a97SAlex Deucher * Setup and start the UVD block 288aaa36a97SAlex Deucher */ 289aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 290aaa36a97SAlex Deucher { 2912bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 292aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 293aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 294aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 295aaa36a97SAlex Deucher int i, j, r; 296aaa36a97SAlex Deucher 297aaa36a97SAlex Deucher /*disable DPG */ 298aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 299aaa36a97SAlex Deucher 300aaa36a97SAlex Deucher /* disable byte swapping */ 301aaa36a97SAlex Deucher lmi_swap_cntl = 0; 302aaa36a97SAlex Deucher mp_swap_cntl = 0; 303aaa36a97SAlex Deucher 304aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 305aaa36a97SAlex Deucher 306aaa36a97SAlex Deucher /* disable interupt */ 307aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 308aaa36a97SAlex Deucher 309aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 310aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 311aaa36a97SAlex Deucher mdelay(1); 312aaa36a97SAlex Deucher 313aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 314aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 315aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 316aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 317aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 318aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 319aaa36a97SAlex Deucher mdelay(5); 320aaa36a97SAlex Deucher 321aaa36a97SAlex Deucher /* take UVD block out of reset */ 322aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 323aaa36a97SAlex Deucher mdelay(5); 324aaa36a97SAlex Deucher 325aaa36a97SAlex Deucher /* initialize UVD memory controller */ 326aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 327aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 328aaa36a97SAlex Deucher 329aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 330aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 331aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 332aaa36a97SAlex Deucher mp_swap_cntl = 0; 333aaa36a97SAlex Deucher #endif 334aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 335aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 336aaa36a97SAlex Deucher 337aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 338aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 339aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 340aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 341aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 342aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 343aaa36a97SAlex Deucher 344aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 345aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 346aaa36a97SAlex Deucher mdelay(5); 347aaa36a97SAlex Deucher 348aaa36a97SAlex Deucher /* enable VCPU clock */ 349aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 350aaa36a97SAlex Deucher 351aaa36a97SAlex Deucher /* enable UMC */ 352aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 353aaa36a97SAlex Deucher 354aaa36a97SAlex Deucher /* boot up the VCPU */ 355aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 356aaa36a97SAlex Deucher mdelay(10); 357aaa36a97SAlex Deucher 358aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 359aaa36a97SAlex Deucher uint32_t status; 360aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 361aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 362aaa36a97SAlex Deucher if (status & 2) 363aaa36a97SAlex Deucher break; 364aaa36a97SAlex Deucher mdelay(10); 365aaa36a97SAlex Deucher } 366aaa36a97SAlex Deucher r = 0; 367aaa36a97SAlex Deucher if (status & 2) 368aaa36a97SAlex Deucher break; 369aaa36a97SAlex Deucher 370aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 371aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 372aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 373aaa36a97SAlex Deucher mdelay(10); 374aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 375aaa36a97SAlex Deucher mdelay(10); 376aaa36a97SAlex Deucher r = -1; 377aaa36a97SAlex Deucher } 378aaa36a97SAlex Deucher 379aaa36a97SAlex Deucher if (r) { 380aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 381aaa36a97SAlex Deucher return r; 382aaa36a97SAlex Deucher } 383aaa36a97SAlex Deucher /* enable master interrupt */ 384aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 385aaa36a97SAlex Deucher 386aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 387aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 388aaa36a97SAlex Deucher 389aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 390aaa36a97SAlex Deucher tmp = 0; 391aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 392aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 393aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 394aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 395aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 396aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 397aaa36a97SAlex Deucher /* force RBC into idle state */ 398aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 399aaa36a97SAlex Deucher 400aaa36a97SAlex Deucher /* set the write pointer delay */ 401aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 402aaa36a97SAlex Deucher 403aaa36a97SAlex Deucher /* set the wb address */ 404aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 405aaa36a97SAlex Deucher 406aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 407aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 408aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 409aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 410aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 411aaa36a97SAlex Deucher 412aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 413aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 414aaa36a97SAlex Deucher 415aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 416536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 417aaa36a97SAlex Deucher 418aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 419aaa36a97SAlex Deucher 420aaa36a97SAlex Deucher return 0; 421aaa36a97SAlex Deucher } 422aaa36a97SAlex Deucher 423aaa36a97SAlex Deucher /** 424aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 425aaa36a97SAlex Deucher * 426aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 427aaa36a97SAlex Deucher * 428aaa36a97SAlex Deucher * stop the UVD block 429aaa36a97SAlex Deucher */ 430aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 431aaa36a97SAlex Deucher { 432aaa36a97SAlex Deucher /* force RBC into idle state */ 433aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 434aaa36a97SAlex Deucher 435aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 436aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 437aaa36a97SAlex Deucher mdelay(1); 438aaa36a97SAlex Deucher 439aaa36a97SAlex Deucher /* put VCPU into reset */ 440aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 441aaa36a97SAlex Deucher mdelay(5); 442aaa36a97SAlex Deucher 443aaa36a97SAlex Deucher /* disable VCPU clock */ 444aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 445aaa36a97SAlex Deucher 446aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 447aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 448e3e672e6SRex Zhu 449e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 450aaa36a97SAlex Deucher } 451aaa36a97SAlex Deucher 452aaa36a97SAlex Deucher /** 453aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 454aaa36a97SAlex Deucher * 455aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 456aaa36a97SAlex Deucher * @fence: fence to emit 457aaa36a97SAlex Deucher * 458aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 459aaa36a97SAlex Deucher */ 460aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 461890ee23fSChunming Zhou unsigned flags) 462aaa36a97SAlex Deucher { 463890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 464aaa36a97SAlex Deucher 465aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 466aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 467aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 468aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 469aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 470aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 471aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 472aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 473aaa36a97SAlex Deucher 474aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 480aaa36a97SAlex Deucher } 481aaa36a97SAlex Deucher 482aaa36a97SAlex Deucher /** 483aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 484aaa36a97SAlex Deucher * 485aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 486aaa36a97SAlex Deucher * 487aaa36a97SAlex Deucher * Test if we can successfully write to the context register 488aaa36a97SAlex Deucher */ 489aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 490aaa36a97SAlex Deucher { 491aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 492aaa36a97SAlex Deucher uint32_t tmp = 0; 493aaa36a97SAlex Deucher unsigned i; 494aaa36a97SAlex Deucher int r; 495aaa36a97SAlex Deucher 496aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 497a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 498aaa36a97SAlex Deucher if (r) { 499aaa36a97SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 500aaa36a97SAlex Deucher ring->idx, r); 501aaa36a97SAlex Deucher return r; 502aaa36a97SAlex Deucher } 503aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 504aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 505a27de35cSChristian König amdgpu_ring_commit(ring); 506aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 507aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 508aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 509aaa36a97SAlex Deucher break; 510aaa36a97SAlex Deucher DRM_UDELAY(1); 511aaa36a97SAlex Deucher } 512aaa36a97SAlex Deucher 513aaa36a97SAlex Deucher if (i < adev->usec_timeout) { 5149953b72fSpding DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 515aaa36a97SAlex Deucher ring->idx, i); 516aaa36a97SAlex Deucher } else { 517aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 518aaa36a97SAlex Deucher ring->idx, tmp); 519aaa36a97SAlex Deucher r = -EINVAL; 520aaa36a97SAlex Deucher } 521aaa36a97SAlex Deucher return r; 522aaa36a97SAlex Deucher } 523aaa36a97SAlex Deucher 524aaa36a97SAlex Deucher /** 525aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 526aaa36a97SAlex Deucher * 527aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 528aaa36a97SAlex Deucher * @ib: indirect buffer to execute 529aaa36a97SAlex Deucher * 530aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 531aaa36a97SAlex Deucher */ 532aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 533d88bf583SChristian König struct amdgpu_ib *ib, 534c4f46f22SChristian König unsigned vmid, bool ctx_switch) 535aaa36a97SAlex Deucher { 536aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 537aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 538aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 539aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 540aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 541aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 542aaa36a97SAlex Deucher } 543aaa36a97SAlex Deucher 5445fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 545aaa36a97SAlex Deucher { 5465fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5475fc3aeebSyanyang1 548aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 549aaa36a97SAlex Deucher } 550aaa36a97SAlex Deucher 5515fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 552aaa36a97SAlex Deucher { 553aaa36a97SAlex Deucher unsigned i; 5545fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 555aaa36a97SAlex Deucher 556aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 557aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 558aaa36a97SAlex Deucher return 0; 559aaa36a97SAlex Deucher } 560aaa36a97SAlex Deucher return -ETIMEDOUT; 561aaa36a97SAlex Deucher } 562aaa36a97SAlex Deucher 5635fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 564aaa36a97SAlex Deucher { 5655fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5665fc3aeebSyanyang1 567aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 568aaa36a97SAlex Deucher 569aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 570aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 571aaa36a97SAlex Deucher mdelay(5); 572aaa36a97SAlex Deucher 573aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 574aaa36a97SAlex Deucher } 575aaa36a97SAlex Deucher 576aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 577aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 578aaa36a97SAlex Deucher unsigned type, 579aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 580aaa36a97SAlex Deucher { 581aaa36a97SAlex Deucher // TODO 582aaa36a97SAlex Deucher return 0; 583aaa36a97SAlex Deucher } 584aaa36a97SAlex Deucher 585aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 586aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 587aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 588aaa36a97SAlex Deucher { 589aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 5902bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 591aaa36a97SAlex Deucher return 0; 592aaa36a97SAlex Deucher } 593aaa36a97SAlex Deucher 594809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 595be3ecca7STom St Denis { 596809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 597be3ecca7STom St Denis 598be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 599809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 600be3ecca7STom St Denis 601be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 602be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 603be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 604be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 605be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 606be3ecca7STom St Denis 607809a6a62SRex Zhu if (enable) { 608809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 609809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 610809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 611809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 612809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 613809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 614809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 615809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 616809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 617809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 618809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 619809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 620809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 621809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 622809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 623809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 624809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 625809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6263c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6273c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6283c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 629809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 630809a6a62SRex Zhu data1 |= suvd_flags; 631809a6a62SRex Zhu } else { 632809a6a62SRex Zhu data3 = 0; 633809a6a62SRex Zhu data1 = 0; 634809a6a62SRex Zhu } 635809a6a62SRex Zhu 636809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 637809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 638809a6a62SRex Zhu } 639809a6a62SRex Zhu 640809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 641809a6a62SRex Zhu { 642809a6a62SRex Zhu uint32_t data, data2; 643809a6a62SRex Zhu 644809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 645809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 646809a6a62SRex Zhu 647809a6a62SRex Zhu 648809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 649809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 650809a6a62SRex Zhu 651809a6a62SRex Zhu 652be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 653be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 654be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 655be3ecca7STom St Denis 656be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 657be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 658be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 659be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 660be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 661be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 662be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 663be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 664be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 665be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 666be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 667be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 668be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 669be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 670be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 671be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 672be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 673be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 674be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 675be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 676be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 677be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 678be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 679be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 680be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 681be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 682be3ecca7STom St Denis 683be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 684be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 685be3ecca7STom St Denis } 686be3ecca7STom St Denis 687be3ecca7STom St Denis #if 0 688be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 689be3ecca7STom St Denis { 690be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 691be3ecca7STom St Denis 692be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 693be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 694be3ecca7STom St Denis 695be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 696be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 697be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 698be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 699be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 700be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 701be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 702be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 703be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 704be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 705be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 706be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 707be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 708be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 709be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 710be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 711be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 712be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 713be3ecca7STom St Denis 714be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 715be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 716be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 717be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 718be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 719be3ecca7STom St Denis 720be3ecca7STom St Denis data |= cgc_flags; 721be3ecca7STom St Denis data1 |= suvd_flags; 722be3ecca7STom St Denis 723be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 724be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 725be3ecca7STom St Denis } 726be3ecca7STom St Denis #endif 727be3ecca7STom St Denis 728809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 729809a6a62SRex Zhu bool enable) 730809a6a62SRex Zhu { 731809a6a62SRex Zhu u32 orig, data; 732809a6a62SRex Zhu 733809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 734809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 735809a6a62SRex Zhu data |= 0xfff; 736809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 737809a6a62SRex Zhu 738809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 739809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 740809a6a62SRex Zhu if (orig != data) 741809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 742809a6a62SRex Zhu } else { 743809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 744809a6a62SRex Zhu data &= ~0xfff; 745809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 746809a6a62SRex Zhu 747809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 748809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 749809a6a62SRex Zhu if (orig != data) 750809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 751809a6a62SRex Zhu } 752809a6a62SRex Zhu } 7534be5097cSRex Zhu 7545fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7555fc3aeebSyanyang1 enum amd_clockgating_state state) 756aaa36a97SAlex Deucher { 75735e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 758be3ecca7STom St Denis bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 75935e5912dSAlex Deucher 760be3ecca7STom St Denis if (enable) { 761be3ecca7STom St Denis /* wait for STATUS to clear */ 762be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 763be3ecca7STom St Denis return -EBUSY; 764809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 765be3ecca7STom St Denis 766be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 767be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 768809a6a62SRex Zhu } else { 769809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 770be3ecca7STom St Denis } 771be3ecca7STom St Denis 772809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 773aaa36a97SAlex Deucher return 0; 774aaa36a97SAlex Deucher } 775aaa36a97SAlex Deucher 7765fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 7775fc3aeebSyanyang1 enum amd_powergating_state state) 778aaa36a97SAlex Deucher { 779aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 780aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 781aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 782aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 783aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 784aaa36a97SAlex Deucher * the smc and the hw blocks 785aaa36a97SAlex Deucher */ 7865fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 787c8781f56SHuang Rui int ret = 0; 7885fc3aeebSyanyang1 7895fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 790aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 791aaa36a97SAlex Deucher } else { 792c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 793c8781f56SHuang Rui if (ret) 794c8781f56SHuang Rui goto out; 795aaa36a97SAlex Deucher } 796c8781f56SHuang Rui 797c8781f56SHuang Rui out: 798c8781f56SHuang Rui return ret; 799c8781f56SHuang Rui } 800c8781f56SHuang Rui 801c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 802c8781f56SHuang Rui { 803c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 804c8781f56SHuang Rui int data; 805c8781f56SHuang Rui 806c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 807c8781f56SHuang Rui 808254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 809254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 810c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 811c8781f56SHuang Rui goto out; 812c8781f56SHuang Rui } 813c8781f56SHuang Rui 814c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 815c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 816c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 817c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 818c8781f56SHuang Rui 819c8781f56SHuang Rui out: 820c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 821aaa36a97SAlex Deucher } 822aaa36a97SAlex Deucher 823a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 82488a907d6STom St Denis .name = "uvd_v5_0", 825aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 826aaa36a97SAlex Deucher .late_init = NULL, 827aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 828aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 829aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 830aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 831aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 832aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 833aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 834aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 835aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 836aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 837aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 838c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 839aaa36a97SAlex Deucher }; 840aaa36a97SAlex Deucher 841aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 84221cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 84379887142SChristian König .align_mask = 0xf, 84479887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 845536fbf94SKen Wang .support_64bit_ptrs = false, 846aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 847aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 848aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 849aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 850e12f3d7aSChristian König .emit_frame_size = 851e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 852e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 853aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 854aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 855aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8568de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 857edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 8589e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 859c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 860c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 861aaa36a97SAlex Deucher }; 862aaa36a97SAlex Deucher 863aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 864aaa36a97SAlex Deucher { 8652bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 866aaa36a97SAlex Deucher } 867aaa36a97SAlex Deucher 868aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 869aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 870aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 871aaa36a97SAlex Deucher }; 872aaa36a97SAlex Deucher 873aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 874aaa36a97SAlex Deucher { 8752bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 8762bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 877aaa36a97SAlex Deucher } 878a1255107SAlex Deucher 879a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 880a1255107SAlex Deucher { 881a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 882a1255107SAlex Deucher .major = 5, 883a1255107SAlex Deucher .minor = 0, 884a1255107SAlex Deucher .rev = 0, 885a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 886a1255107SAlex Deucher }; 887