1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in 12aaa36a97SAlex Deucher * all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21aaa36a97SAlex Deucher * 22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23aaa36a97SAlex Deucher */ 24aaa36a97SAlex Deucher 25c366be54SSam Ravnborg #include <linux/delay.h> 26aaa36a97SAlex Deucher #include <linux/firmware.h> 27c366be54SSam Ravnborg 28aaa36a97SAlex Deucher #include "amdgpu.h" 29aaa36a97SAlex Deucher #include "amdgpu_uvd.h" 30aaa36a97SAlex Deucher #include "vid.h" 31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h" 32aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h" 33aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h" 34aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 35d5b4e25dSChristian König #include "bif/bif_5_0_d.h" 36be3ecca7STom St Denis #include "vi.h" 374be5097cSRex Zhu #include "smu/smu_7_1_2_d.h" 384be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h" 39091aec0bSAndrey Grodzovsky #include "ivsrcid/ivsrcid_vislands30.h" 40aaa36a97SAlex Deucher 41aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 42aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 43aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev); 44aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev); 45809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle, 46809a6a62SRex Zhu enum amd_clockgating_state state); 47809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 48809a6a62SRex Zhu bool enable); 49aaa36a97SAlex Deucher /** 50aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer 51aaa36a97SAlex Deucher * 52aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 53aaa36a97SAlex Deucher * 54aaa36a97SAlex Deucher * Returns the current hardware read pointer 55aaa36a97SAlex Deucher */ 56536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 57aaa36a97SAlex Deucher { 58aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 59aaa36a97SAlex Deucher 60aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 61aaa36a97SAlex Deucher } 62aaa36a97SAlex Deucher 63aaa36a97SAlex Deucher /** 64aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer 65aaa36a97SAlex Deucher * 66aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 67aaa36a97SAlex Deucher * 68aaa36a97SAlex Deucher * Returns the current hardware write pointer 69aaa36a97SAlex Deucher */ 70536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 71aaa36a97SAlex Deucher { 72aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 73aaa36a97SAlex Deucher 74aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 75aaa36a97SAlex Deucher } 76aaa36a97SAlex Deucher 77aaa36a97SAlex Deucher /** 78aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer 79aaa36a97SAlex Deucher * 80aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 81aaa36a97SAlex Deucher * 82aaa36a97SAlex Deucher * Commits the write pointer to the hardware 83aaa36a97SAlex Deucher */ 84aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 85aaa36a97SAlex Deucher { 86aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 87aaa36a97SAlex Deucher 88536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 89aaa36a97SAlex Deucher } 90aaa36a97SAlex Deucher 915fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle) 92aaa36a97SAlex Deucher { 935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 942bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 955fc3aeebSyanyang1 96aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev); 97aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev); 98aaa36a97SAlex Deucher 99aaa36a97SAlex Deucher return 0; 100aaa36a97SAlex Deucher } 101aaa36a97SAlex Deucher 1025fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle) 103aaa36a97SAlex Deucher { 104aaa36a97SAlex Deucher struct amdgpu_ring *ring; 1055fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 106aaa36a97SAlex Deucher int r; 107aaa36a97SAlex Deucher 108aaa36a97SAlex Deucher /* UVD TRAP */ 1091ffdeca6SChristian König r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 110aaa36a97SAlex Deucher if (r) 111aaa36a97SAlex Deucher return r; 112aaa36a97SAlex Deucher 113aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev); 114aaa36a97SAlex Deucher if (r) 115aaa36a97SAlex Deucher return r; 116aaa36a97SAlex Deucher 1172bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 118aaa36a97SAlex Deucher sprintf(ring->name, "uvd"); 1191c6d567bSNirmoy Das r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 1201c6d567bSNirmoy Das AMDGPU_RING_PRIO_DEFAULT); 12133d5bd07SEmily Deng if (r) 12233d5bd07SEmily Deng return r; 12333d5bd07SEmily Deng 1243b34c14fSChris Wilson r = amdgpu_uvd_resume(adev); 1253b34c14fSChris Wilson if (r) 1263b34c14fSChris Wilson return r; 1273b34c14fSChris Wilson 12833d5bd07SEmily Deng r = amdgpu_uvd_entity_init(adev); 129aaa36a97SAlex Deucher 130aaa36a97SAlex Deucher return r; 131aaa36a97SAlex Deucher } 132aaa36a97SAlex Deucher 1335fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle) 134aaa36a97SAlex Deucher { 135aaa36a97SAlex Deucher int r; 1365fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137aaa36a97SAlex Deucher 138aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev); 139aaa36a97SAlex Deucher if (r) 140aaa36a97SAlex Deucher return r; 141aaa36a97SAlex Deucher 14250237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 143aaa36a97SAlex Deucher } 144aaa36a97SAlex Deucher 145aaa36a97SAlex Deucher /** 146aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block 147aaa36a97SAlex Deucher * 148aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 149aaa36a97SAlex Deucher * 150aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 151aaa36a97SAlex Deucher */ 1525fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle) 153aaa36a97SAlex Deucher { 1545fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 156aaa36a97SAlex Deucher uint32_t tmp; 157aaa36a97SAlex Deucher int r; 158aaa36a97SAlex Deucher 159e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 161e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true); 162aaa36a97SAlex Deucher 163c66ed765SAndrey Grodzovsky r = amdgpu_ring_test_helper(ring); 164c66ed765SAndrey Grodzovsky if (r) 165aaa36a97SAlex Deucher goto done; 166aaa36a97SAlex Deucher 167a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 168aaa36a97SAlex Deucher if (r) { 169aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170aaa36a97SAlex Deucher goto done; 171aaa36a97SAlex Deucher } 172aaa36a97SAlex Deucher 173aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 175aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176aaa36a97SAlex Deucher 177aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 179aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180aaa36a97SAlex Deucher 181aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp); 183aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184aaa36a97SAlex Deucher 185aaa36a97SAlex Deucher /* Clear timeout status bits */ 186aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8); 188aaa36a97SAlex Deucher 189aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3); 191aaa36a97SAlex Deucher 192a27de35cSChristian König amdgpu_ring_commit(ring); 193e3e672e6SRex Zhu 194aaa36a97SAlex Deucher done: 195aaa36a97SAlex Deucher if (!r) 196aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher return r; 199e3e672e6SRex Zhu 200aaa36a97SAlex Deucher } 201aaa36a97SAlex Deucher 202aaa36a97SAlex Deucher /** 203aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block 204aaa36a97SAlex Deucher * 205aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 206aaa36a97SAlex Deucher * 207aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more 208aaa36a97SAlex Deucher */ 2095fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle) 210aaa36a97SAlex Deucher { 2115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212aaa36a97SAlex Deucher 213e3e672e6SRex Zhu if (RREG32(mmUVD_STATUS) != 0) 214aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 215e3e672e6SRex Zhu 216aaa36a97SAlex Deucher return 0; 217aaa36a97SAlex Deucher } 218aaa36a97SAlex Deucher 2195fc3aeebSyanyang1 static int uvd_v5_0_suspend(void *handle) 220aaa36a97SAlex Deucher { 221aaa36a97SAlex Deucher int r; 2225fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 223aaa36a97SAlex Deucher 2243f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev); 225aaa36a97SAlex Deucher if (r) 226aaa36a97SAlex Deucher return r; 227809a6a62SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 228aaa36a97SAlex Deucher 22950237287SRex Zhu return amdgpu_uvd_suspend(adev); 230aaa36a97SAlex Deucher } 231aaa36a97SAlex Deucher 2325fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle) 233aaa36a97SAlex Deucher { 234aaa36a97SAlex Deucher int r; 2355fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 236aaa36a97SAlex Deucher 237aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev); 238aaa36a97SAlex Deucher if (r) 239aaa36a97SAlex Deucher return r; 240aaa36a97SAlex Deucher 24150237287SRex Zhu return uvd_v5_0_hw_init(adev); 242aaa36a97SAlex Deucher } 243aaa36a97SAlex Deucher 244aaa36a97SAlex Deucher /** 245aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming 246aaa36a97SAlex Deucher * 247aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 248aaa36a97SAlex Deucher * 249aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets 250aaa36a97SAlex Deucher */ 251aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 252aaa36a97SAlex Deucher { 253aaa36a97SAlex Deucher uint64_t offset; 254aaa36a97SAlex Deucher uint32_t size; 255aaa36a97SAlex Deucher 256aaa36a97SAlex Deucher /* programm memory controller bits 0-27 */ 257aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 2582bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr)); 259aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 2602bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr)); 261aaa36a97SAlex Deucher 262aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET; 263c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 264aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 265aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 266aaa36a97SAlex Deucher 267aaa36a97SAlex Deucher offset += size; 268c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE; 269aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 270aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 271aaa36a97SAlex Deucher 272aaa36a97SAlex Deucher offset += size; 273c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE + 274c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 275aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 276aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 277549300ceSAlex Deucher 278549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 279549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 280549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 281aaa36a97SAlex Deucher } 282aaa36a97SAlex Deucher 283aaa36a97SAlex Deucher /** 284aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block 285aaa36a97SAlex Deucher * 286aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 287aaa36a97SAlex Deucher * 288aaa36a97SAlex Deucher * Setup and start the UVD block 289aaa36a97SAlex Deucher */ 290aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev) 291aaa36a97SAlex Deucher { 2922bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 293aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp; 294aaa36a97SAlex Deucher uint32_t lmi_swap_cntl; 295aaa36a97SAlex Deucher uint32_t mp_swap_cntl; 296aaa36a97SAlex Deucher int i, j, r; 297aaa36a97SAlex Deucher 298aaa36a97SAlex Deucher /*disable DPG */ 299aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 300aaa36a97SAlex Deucher 301aaa36a97SAlex Deucher /* disable byte swapping */ 302aaa36a97SAlex Deucher lmi_swap_cntl = 0; 303aaa36a97SAlex Deucher mp_swap_cntl = 0; 304aaa36a97SAlex Deucher 305aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev); 306aaa36a97SAlex Deucher 307aaa36a97SAlex Deucher /* disable interupt */ 308aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 309aaa36a97SAlex Deucher 310aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */ 311aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 312aaa36a97SAlex Deucher mdelay(1); 313aaa36a97SAlex Deucher 314aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 315aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 316aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 317aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 318aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 319aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 320aaa36a97SAlex Deucher mdelay(5); 321aaa36a97SAlex Deucher 322aaa36a97SAlex Deucher /* take UVD block out of reset */ 323aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 324aaa36a97SAlex Deucher mdelay(5); 325aaa36a97SAlex Deucher 326aaa36a97SAlex Deucher /* initialize UVD memory controller */ 327aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 328aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 329aaa36a97SAlex Deucher 330aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN 331aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */ 332aaa36a97SAlex Deucher lmi_swap_cntl = 0xa; 333aaa36a97SAlex Deucher mp_swap_cntl = 0; 334aaa36a97SAlex Deucher #endif 335aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 336aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 337aaa36a97SAlex Deucher 338aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 339aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 340aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 341aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 342aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 343aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 344aaa36a97SAlex Deucher 345aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */ 346aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 347aaa36a97SAlex Deucher mdelay(5); 348aaa36a97SAlex Deucher 349aaa36a97SAlex Deucher /* enable VCPU clock */ 350aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 351aaa36a97SAlex Deucher 352aaa36a97SAlex Deucher /* enable UMC */ 353aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 354aaa36a97SAlex Deucher 355aaa36a97SAlex Deucher /* boot up the VCPU */ 356aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 357aaa36a97SAlex Deucher mdelay(10); 358aaa36a97SAlex Deucher 359aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) { 360aaa36a97SAlex Deucher uint32_t status; 361aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) { 362aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS); 363aaa36a97SAlex Deucher if (status & 2) 364aaa36a97SAlex Deucher break; 365aaa36a97SAlex Deucher mdelay(10); 366aaa36a97SAlex Deucher } 367aaa36a97SAlex Deucher r = 0; 368aaa36a97SAlex Deucher if (status & 2) 369aaa36a97SAlex Deucher break; 370aaa36a97SAlex Deucher 371aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 372aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 373aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 374aaa36a97SAlex Deucher mdelay(10); 375aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 376aaa36a97SAlex Deucher mdelay(10); 377aaa36a97SAlex Deucher r = -1; 378aaa36a97SAlex Deucher } 379aaa36a97SAlex Deucher 380aaa36a97SAlex Deucher if (r) { 381aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 382aaa36a97SAlex Deucher return r; 383aaa36a97SAlex Deucher } 384aaa36a97SAlex Deucher /* enable master interrupt */ 385aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 386aaa36a97SAlex Deucher 387aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */ 388aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 389aaa36a97SAlex Deucher 390aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 391aaa36a97SAlex Deucher tmp = 0; 392aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 393aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 394aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 395aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 396aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 397aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 398aaa36a97SAlex Deucher /* force RBC into idle state */ 399aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp); 400aaa36a97SAlex Deucher 401aaa36a97SAlex Deucher /* set the write pointer delay */ 402aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 403aaa36a97SAlex Deucher 404aaa36a97SAlex Deucher /* set the wb address */ 405aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 406aaa36a97SAlex Deucher 407aaa36a97SAlex Deucher /* programm the RB_BASE for ring buffer */ 408aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 409aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr)); 410aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 411aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr)); 412aaa36a97SAlex Deucher 413aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 414aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0); 415aaa36a97SAlex Deucher 416aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 417536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 418aaa36a97SAlex Deucher 419aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 420aaa36a97SAlex Deucher 421aaa36a97SAlex Deucher return 0; 422aaa36a97SAlex Deucher } 423aaa36a97SAlex Deucher 424aaa36a97SAlex Deucher /** 425aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block 426aaa36a97SAlex Deucher * 427aaa36a97SAlex Deucher * @adev: amdgpu_device pointer 428aaa36a97SAlex Deucher * 429aaa36a97SAlex Deucher * stop the UVD block 430aaa36a97SAlex Deucher */ 431aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev) 432aaa36a97SAlex Deucher { 433aaa36a97SAlex Deucher /* force RBC into idle state */ 434aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 435aaa36a97SAlex Deucher 436aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 437aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 438aaa36a97SAlex Deucher mdelay(1); 439aaa36a97SAlex Deucher 440aaa36a97SAlex Deucher /* put VCPU into reset */ 441aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 442aaa36a97SAlex Deucher mdelay(5); 443aaa36a97SAlex Deucher 444aaa36a97SAlex Deucher /* disable VCPU clock */ 445aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 446aaa36a97SAlex Deucher 447aaa36a97SAlex Deucher /* Unstall UMC and register bus */ 448aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 449e3e672e6SRex Zhu 450e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0); 451aaa36a97SAlex Deucher } 452aaa36a97SAlex Deucher 453aaa36a97SAlex Deucher /** 454aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command 455aaa36a97SAlex Deucher * 456aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 457aaa36a97SAlex Deucher * @fence: fence to emit 458aaa36a97SAlex Deucher * 459aaa36a97SAlex Deucher * Write a fence and a trap command to the ring. 460aaa36a97SAlex Deucher */ 461aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 462890ee23fSChunming Zhou unsigned flags) 463aaa36a97SAlex Deucher { 464890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 465aaa36a97SAlex Deucher 466aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 467aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq); 468aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 469aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 470aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 471aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 472aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 473aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 474aaa36a97SAlex Deucher 475aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 476aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 477aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 478aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0); 479aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 480aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2); 481aaa36a97SAlex Deucher } 482aaa36a97SAlex Deucher 483aaa36a97SAlex Deucher /** 484aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test 485aaa36a97SAlex Deucher * 486aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 487aaa36a97SAlex Deucher * 488aaa36a97SAlex Deucher * Test if we can successfully write to the context register 489aaa36a97SAlex Deucher */ 490aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 491aaa36a97SAlex Deucher { 492aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev; 493aaa36a97SAlex Deucher uint32_t tmp = 0; 494aaa36a97SAlex Deucher unsigned i; 495aaa36a97SAlex Deucher int r; 496aaa36a97SAlex Deucher 497aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 498a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 499dc9eeff8SChristian König if (r) 500aaa36a97SAlex Deucher return r; 501aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 502aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 503a27de35cSChristian König amdgpu_ring_commit(ring); 504aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 505aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 506aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF) 507aaa36a97SAlex Deucher break; 508c366be54SSam Ravnborg udelay(1); 509aaa36a97SAlex Deucher } 510aaa36a97SAlex Deucher 511dc9eeff8SChristian König if (i >= adev->usec_timeout) 512dc9eeff8SChristian König r = -ETIMEDOUT; 513dc9eeff8SChristian König 514aaa36a97SAlex Deucher return r; 515aaa36a97SAlex Deucher } 516aaa36a97SAlex Deucher 517aaa36a97SAlex Deucher /** 518aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer 519aaa36a97SAlex Deucher * 520aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer 521aaa36a97SAlex Deucher * @ib: indirect buffer to execute 522aaa36a97SAlex Deucher * 523aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer 524aaa36a97SAlex Deucher */ 525aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 52634955e03SRex Zhu struct amdgpu_job *job, 527d88bf583SChristian König struct amdgpu_ib *ib, 528c4c905ecSJack Xiao uint32_t flags) 529aaa36a97SAlex Deucher { 530aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 531aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 532aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 533aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 534aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 535aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 536aaa36a97SAlex Deucher } 537aaa36a97SAlex Deucher 5380232e306SLeo Liu static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 5390232e306SLeo Liu { 5400232e306SLeo Liu int i; 5410232e306SLeo Liu 5420232e306SLeo Liu WARN_ON(ring->wptr % 2 || count % 2); 5430232e306SLeo Liu 5440232e306SLeo Liu for (i = 0; i < count / 2; i++) { 5450232e306SLeo Liu amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 5460232e306SLeo Liu amdgpu_ring_write(ring, 0); 5470232e306SLeo Liu } 5480232e306SLeo Liu } 5490232e306SLeo Liu 5505fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle) 551aaa36a97SAlex Deucher { 5525fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5535fc3aeebSyanyang1 554aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 555aaa36a97SAlex Deucher } 556aaa36a97SAlex Deucher 5575fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle) 558aaa36a97SAlex Deucher { 559aaa36a97SAlex Deucher unsigned i; 5605fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 561aaa36a97SAlex Deucher 562aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 563aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 564aaa36a97SAlex Deucher return 0; 565aaa36a97SAlex Deucher } 566aaa36a97SAlex Deucher return -ETIMEDOUT; 567aaa36a97SAlex Deucher } 568aaa36a97SAlex Deucher 5695fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle) 570aaa36a97SAlex Deucher { 5715fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5725fc3aeebSyanyang1 573aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 574aaa36a97SAlex Deucher 575aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 576aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 577aaa36a97SAlex Deucher mdelay(5); 578aaa36a97SAlex Deucher 579aaa36a97SAlex Deucher return uvd_v5_0_start(adev); 580aaa36a97SAlex Deucher } 581aaa36a97SAlex Deucher 582aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 583aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 584aaa36a97SAlex Deucher unsigned type, 585aaa36a97SAlex Deucher enum amdgpu_interrupt_state state) 586aaa36a97SAlex Deucher { 587aaa36a97SAlex Deucher // TODO 588aaa36a97SAlex Deucher return 0; 589aaa36a97SAlex Deucher } 590aaa36a97SAlex Deucher 591aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 592aaa36a97SAlex Deucher struct amdgpu_irq_src *source, 593aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry) 594aaa36a97SAlex Deucher { 595aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 5962bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 597aaa36a97SAlex Deucher return 0; 598aaa36a97SAlex Deucher } 599aaa36a97SAlex Deucher 600809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 601be3ecca7STom St Denis { 602809a6a62SRex Zhu uint32_t data1, data3, suvd_flags; 603be3ecca7STom St Denis 604be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 605809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE); 606be3ecca7STom St Denis 607be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 608be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 609be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 610be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 611be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 612be3ecca7STom St Denis 613809a6a62SRex Zhu if (enable) { 614809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK | 615809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK | 616809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK | 617809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK | 618809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK | 619809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK | 620809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK | 621809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK | 622809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK | 623809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK | 624809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK | 625809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK | 626809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK | 627809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK | 628809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK | 629809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK | 630809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK | 631809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK); 6323c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/ 6333c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 6343c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK; 635809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK; 636809a6a62SRex Zhu data1 |= suvd_flags; 637809a6a62SRex Zhu } else { 638809a6a62SRex Zhu data3 = 0; 639809a6a62SRex Zhu data1 = 0; 640809a6a62SRex Zhu } 641809a6a62SRex Zhu 642809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1); 643809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3); 644809a6a62SRex Zhu } 645809a6a62SRex Zhu 646809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 647809a6a62SRex Zhu { 648809a6a62SRex Zhu uint32_t data, data2; 649809a6a62SRex Zhu 650809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL); 651809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 652809a6a62SRex Zhu 653809a6a62SRex Zhu 654809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 655809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 656809a6a62SRex Zhu 657809a6a62SRex Zhu 658be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 659be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 660be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 661be3ecca7STom St Denis 662be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 663be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 664be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 665be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 666be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 667be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK | 668be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK | 669be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK | 670be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK | 671be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK | 672be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK | 673be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 674be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK | 675be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK | 676be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK | 677be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK | 678be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK | 679be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK | 680be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK | 681be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK | 682be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK); 683be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 684be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 685be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 686be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 687be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 688be3ecca7STom St Denis 689be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data); 690be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2); 691be3ecca7STom St Denis } 692be3ecca7STom St Denis 693be3ecca7STom St Denis #if 0 694be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 695be3ecca7STom St Denis { 696be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags; 697be3ecca7STom St Denis 698be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE); 699be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE); 700be3ecca7STom St Denis 701be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK | 702be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK | 703be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK | 704be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK | 705be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK | 706be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK | 707be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK | 708be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK | 709be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK | 710be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK | 711be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK | 712be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK | 713be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK | 714be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK | 715be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK | 716be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK | 717be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK | 718be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK; 719be3ecca7STom St Denis 720be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 721be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK | 722be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK | 723be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK | 724be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK; 725be3ecca7STom St Denis 726be3ecca7STom St Denis data |= cgc_flags; 727be3ecca7STom St Denis data1 |= suvd_flags; 728be3ecca7STom St Denis 729be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data); 730be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1); 731be3ecca7STom St Denis } 732be3ecca7STom St Denis #endif 733be3ecca7STom St Denis 734809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 735809a6a62SRex Zhu bool enable) 736809a6a62SRex Zhu { 737809a6a62SRex Zhu u32 orig, data; 738809a6a62SRex Zhu 739809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 740809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 741809a6a62SRex Zhu data |= 0xfff; 742809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 743809a6a62SRex Zhu 744809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 745809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 746809a6a62SRex Zhu if (orig != data) 747809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 748809a6a62SRex Zhu } else { 749809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 750809a6a62SRex Zhu data &= ~0xfff; 751809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 752809a6a62SRex Zhu 753809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL); 754809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 755809a6a62SRex Zhu if (orig != data) 756809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data); 757809a6a62SRex Zhu } 758809a6a62SRex Zhu } 7594be5097cSRex Zhu 7605fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle, 7615fc3aeebSyanyang1 enum amd_clockgating_state state) 762aaa36a97SAlex Deucher { 76335e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle; 764a9d4fe2fSNirmoy Das bool enable = (state == AMD_CG_STATE_GATE); 76535e5912dSAlex Deucher 766be3ecca7STom St Denis if (enable) { 767be3ecca7STom St Denis /* wait for STATUS to clear */ 768be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle)) 769be3ecca7STom St Denis return -EBUSY; 770809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true); 771be3ecca7STom St Denis 772be3ecca7STom St Denis /* enable HW gates because UVD is idle */ 773be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */ 774809a6a62SRex Zhu } else { 775809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false); 776be3ecca7STom St Denis } 777be3ecca7STom St Denis 778809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev); 779aaa36a97SAlex Deucher return 0; 780aaa36a97SAlex Deucher } 781aaa36a97SAlex Deucher 7825fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle, 7835fc3aeebSyanyang1 enum amd_powergating_state state) 784aaa36a97SAlex Deucher { 785aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block. 786aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This 787aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual 788aaa36a97SAlex Deucher * gating still happens in the dpm code. We should 789aaa36a97SAlex Deucher * revisit this when there is a cleaner line between 790aaa36a97SAlex Deucher * the smc and the hw blocks 791aaa36a97SAlex Deucher */ 7925fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 793c8781f56SHuang Rui int ret = 0; 7945fc3aeebSyanyang1 7955fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 796aaa36a97SAlex Deucher uvd_v5_0_stop(adev); 797aaa36a97SAlex Deucher } else { 798c8781f56SHuang Rui ret = uvd_v5_0_start(adev); 799c8781f56SHuang Rui if (ret) 800c8781f56SHuang Rui goto out; 801aaa36a97SAlex Deucher } 802c8781f56SHuang Rui 803c8781f56SHuang Rui out: 804c8781f56SHuang Rui return ret; 805c8781f56SHuang Rui } 806c8781f56SHuang Rui 807c8781f56SHuang Rui static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 808c8781f56SHuang Rui { 809c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle; 810c8781f56SHuang Rui int data; 811c8781f56SHuang Rui 812c8781f56SHuang Rui mutex_lock(&adev->pm.mutex); 813c8781f56SHuang Rui 814254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 815254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 816c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 817c8781f56SHuang Rui goto out; 818c8781f56SHuang Rui } 819c8781f56SHuang Rui 820c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */ 821c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL); 822c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 823c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG; 824c8781f56SHuang Rui 825c8781f56SHuang Rui out: 826c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex); 827aaa36a97SAlex Deucher } 828aaa36a97SAlex Deucher 829a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 83088a907d6STom St Denis .name = "uvd_v5_0", 831aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init, 832aaa36a97SAlex Deucher .late_init = NULL, 833aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init, 834aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini, 835aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init, 836aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini, 837aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend, 838aaa36a97SAlex Deucher .resume = uvd_v5_0_resume, 839aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle, 840aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle, 841aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset, 842aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state, 843aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state, 844c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state, 845aaa36a97SAlex Deucher }; 846aaa36a97SAlex Deucher 847aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 84821cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 84979887142SChristian König .align_mask = 0xf, 850536fbf94SKen Wang .support_64bit_ptrs = false, 8517ee250b1SLeo Liu .no_user_fence = true, 852aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr, 853aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr, 854aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr, 855aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 856e12f3d7aSChristian König .emit_frame_size = 857e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 858e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 859aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib, 860aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence, 861aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring, 8628de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 8630232e306SLeo Liu .insert_nop = uvd_v5_0_ring_insert_nop, 8649e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 865c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 866c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 867aaa36a97SAlex Deucher }; 868aaa36a97SAlex Deucher 869aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 870aaa36a97SAlex Deucher { 8712bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 872aaa36a97SAlex Deucher } 873aaa36a97SAlex Deucher 874aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 875aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state, 876aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt, 877aaa36a97SAlex Deucher }; 878aaa36a97SAlex Deucher 879aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 880aaa36a97SAlex Deucher { 8812bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 8822bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 883aaa36a97SAlex Deucher } 884a1255107SAlex Deucher 885a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 886a1255107SAlex Deucher { 887a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 888a1255107SAlex Deucher .major = 5, 889a1255107SAlex Deucher .minor = 0, 890a1255107SAlex Deucher .rev = 0, 891a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs, 892a1255107SAlex Deucher }; 893