1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "cikd.h" 30 31 #include "uvd/uvd_4_2_d.h" 32 #include "uvd/uvd_4_2_sh_mask.h" 33 34 #include "oss/oss_2_0_d.h" 35 #include "oss/oss_2_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 39 #include "smu/smu_7_0_1_d.h" 40 #include "smu/smu_7_0_1_sh_mask.h" 41 42 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 44 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45 static int uvd_v4_2_start(struct amdgpu_device *adev); 46 static void uvd_v4_2_stop(struct amdgpu_device *adev); 47 static int uvd_v4_2_set_clockgating_state(void *handle, 48 enum amd_clockgating_state state); 49 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 50 bool sw_mode); 51 /** 52 * uvd_v4_2_ring_get_rptr - get read pointer 53 * 54 * @ring: amdgpu_ring pointer 55 * 56 * Returns the current hardware read pointer 57 */ 58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 59 { 60 struct amdgpu_device *adev = ring->adev; 61 62 return RREG32(mmUVD_RBC_RB_RPTR); 63 } 64 65 /** 66 * uvd_v4_2_ring_get_wptr - get write pointer 67 * 68 * @ring: amdgpu_ring pointer 69 * 70 * Returns the current hardware write pointer 71 */ 72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 73 { 74 struct amdgpu_device *adev = ring->adev; 75 76 return RREG32(mmUVD_RBC_RB_WPTR); 77 } 78 79 /** 80 * uvd_v4_2_ring_set_wptr - set write pointer 81 * 82 * @ring: amdgpu_ring pointer 83 * 84 * Commits the write pointer to the hardware 85 */ 86 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 87 { 88 struct amdgpu_device *adev = ring->adev; 89 90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 91 } 92 93 static int uvd_v4_2_early_init(void *handle) 94 { 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 adev->uvd.num_uvd_inst = 1; 97 98 uvd_v4_2_set_ring_funcs(adev); 99 uvd_v4_2_set_irq_funcs(adev); 100 101 return 0; 102 } 103 104 static int uvd_v4_2_sw_init(void *handle) 105 { 106 struct amdgpu_ring *ring; 107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 108 int r; 109 110 /* UVD TRAP */ 111 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 112 if (r) 113 return r; 114 115 r = amdgpu_uvd_sw_init(adev); 116 if (r) 117 return r; 118 119 r = amdgpu_uvd_resume(adev); 120 if (r) 121 return r; 122 123 ring = &adev->uvd.inst->ring; 124 sprintf(ring->name, "uvd"); 125 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 126 127 return r; 128 } 129 130 static int uvd_v4_2_sw_fini(void *handle) 131 { 132 int r; 133 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 134 135 r = amdgpu_uvd_suspend(adev); 136 if (r) 137 return r; 138 139 return amdgpu_uvd_sw_fini(adev); 140 } 141 142 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 143 bool enable); 144 /** 145 * uvd_v4_2_hw_init - start and test UVD block 146 * 147 * @adev: amdgpu_device pointer 148 * 149 * Initialize the hardware, boot up the VCPU and do some testing 150 */ 151 static int uvd_v4_2_hw_init(void *handle) 152 { 153 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 154 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 155 uint32_t tmp; 156 int r; 157 158 uvd_v4_2_enable_mgcg(adev, true); 159 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160 161 ring->ready = true; 162 r = amdgpu_ring_test_ring(ring); 163 if (r) { 164 ring->ready = false; 165 goto done; 166 } 167 168 r = amdgpu_ring_alloc(ring, 10); 169 if (r) { 170 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 171 goto done; 172 } 173 174 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 175 amdgpu_ring_write(ring, tmp); 176 amdgpu_ring_write(ring, 0xFFFFF); 177 178 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 179 amdgpu_ring_write(ring, tmp); 180 amdgpu_ring_write(ring, 0xFFFFF); 181 182 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 183 amdgpu_ring_write(ring, tmp); 184 amdgpu_ring_write(ring, 0xFFFFF); 185 186 /* Clear timeout status bits */ 187 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 188 amdgpu_ring_write(ring, 0x8); 189 190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 191 amdgpu_ring_write(ring, 3); 192 193 amdgpu_ring_commit(ring); 194 195 done: 196 if (!r) 197 DRM_INFO("UVD initialized successfully.\n"); 198 199 return r; 200 } 201 202 /** 203 * uvd_v4_2_hw_fini - stop the hardware block 204 * 205 * @adev: amdgpu_device pointer 206 * 207 * Stop the UVD block, mark ring as not ready any more 208 */ 209 static int uvd_v4_2_hw_fini(void *handle) 210 { 211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 213 214 if (RREG32(mmUVD_STATUS) != 0) 215 uvd_v4_2_stop(adev); 216 217 ring->ready = false; 218 219 return 0; 220 } 221 222 static int uvd_v4_2_suspend(void *handle) 223 { 224 int r; 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226 227 r = uvd_v4_2_hw_fini(adev); 228 if (r) 229 return r; 230 231 return amdgpu_uvd_suspend(adev); 232 } 233 234 static int uvd_v4_2_resume(void *handle) 235 { 236 int r; 237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238 239 r = amdgpu_uvd_resume(adev); 240 if (r) 241 return r; 242 243 return uvd_v4_2_hw_init(adev); 244 } 245 246 /** 247 * uvd_v4_2_start - start UVD block 248 * 249 * @adev: amdgpu_device pointer 250 * 251 * Setup and start the UVD block 252 */ 253 static int uvd_v4_2_start(struct amdgpu_device *adev) 254 { 255 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 256 uint32_t rb_bufsz; 257 int i, j, r; 258 u32 tmp; 259 /* disable byte swapping */ 260 u32 lmi_swap_cntl = 0; 261 u32 mp_swap_cntl = 0; 262 263 /* set uvd busy */ 264 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); 265 266 uvd_v4_2_set_dcm(adev, true); 267 WREG32(mmUVD_CGC_GATE, 0); 268 269 /* take UVD block out of reset */ 270 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 271 mdelay(5); 272 273 /* enable VCPU clock */ 274 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 275 276 /* disable interupt */ 277 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 278 279 #ifdef __BIG_ENDIAN 280 /* swap (8 in 32) RB and IB */ 281 lmi_swap_cntl = 0xa; 282 mp_swap_cntl = 0; 283 #endif 284 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 285 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 286 /* initialize UVD memory controller */ 287 WREG32(mmUVD_LMI_CTRL, 0x203108); 288 289 tmp = RREG32(mmUVD_MPC_CNTL); 290 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); 291 292 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 293 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 294 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 295 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 296 WREG32(mmUVD_MPC_SET_ALU, 0); 297 WREG32(mmUVD_MPC_SET_MUX, 0x88); 298 299 uvd_v4_2_mc_resume(adev); 300 301 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); 302 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); 303 304 /* enable UMC */ 305 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 306 307 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 308 309 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 310 311 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 312 313 mdelay(10); 314 315 for (i = 0; i < 10; ++i) { 316 uint32_t status; 317 for (j = 0; j < 100; ++j) { 318 status = RREG32(mmUVD_STATUS); 319 if (status & 2) 320 break; 321 mdelay(10); 322 } 323 r = 0; 324 if (status & 2) 325 break; 326 327 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 328 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 329 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 330 mdelay(10); 331 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 332 mdelay(10); 333 r = -1; 334 } 335 336 if (r) { 337 DRM_ERROR("UVD not responding, giving up!!!\n"); 338 return r; 339 } 340 341 /* enable interupt */ 342 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 343 344 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); 345 346 /* force RBC into idle state */ 347 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 348 349 /* Set the write pointer delay */ 350 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 351 352 /* programm the 4GB memory segment for rptr and ring buffer */ 353 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 354 (0x7 << 16) | (0x1 << 31)); 355 356 /* Initialize the ring buffer's read and write pointers */ 357 WREG32(mmUVD_RBC_RB_RPTR, 0x0); 358 359 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 360 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 361 362 /* set the ring address */ 363 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 364 365 /* Set ring buffer size */ 366 rb_bufsz = order_base_2(ring->ring_size); 367 rb_bufsz = (0x1 << 8) | rb_bufsz; 368 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 369 370 return 0; 371 } 372 373 /** 374 * uvd_v4_2_stop - stop UVD block 375 * 376 * @adev: amdgpu_device pointer 377 * 378 * stop the UVD block 379 */ 380 static void uvd_v4_2_stop(struct amdgpu_device *adev) 381 { 382 uint32_t i, j; 383 uint32_t status; 384 385 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 386 387 for (i = 0; i < 10; ++i) { 388 for (j = 0; j < 100; ++j) { 389 status = RREG32(mmUVD_STATUS); 390 if (status & 2) 391 break; 392 mdelay(1); 393 } 394 if (status & 2) 395 break; 396 } 397 398 for (i = 0; i < 10; ++i) { 399 for (j = 0; j < 100; ++j) { 400 status = RREG32(mmUVD_LMI_STATUS); 401 if (status & 0xf) 402 break; 403 mdelay(1); 404 } 405 if (status & 0xf) 406 break; 407 } 408 409 /* Stall UMC and register bus before resetting VCPU */ 410 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 411 412 for (i = 0; i < 10; ++i) { 413 for (j = 0; j < 100; ++j) { 414 status = RREG32(mmUVD_LMI_STATUS); 415 if (status & 0x240) 416 break; 417 mdelay(1); 418 } 419 if (status & 0x240) 420 break; 421 } 422 423 WREG32_P(0x3D49, 0, ~(1 << 2)); 424 425 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); 426 427 /* put LMI, VCPU, RBC etc... into reset */ 428 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 429 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 430 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 431 432 WREG32(mmUVD_STATUS, 0); 433 434 uvd_v4_2_set_dcm(adev, false); 435 } 436 437 /** 438 * uvd_v4_2_ring_emit_fence - emit an fence & trap command 439 * 440 * @ring: amdgpu_ring pointer 441 * @fence: fence to emit 442 * 443 * Write a fence and a trap command to the ring. 444 */ 445 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 446 unsigned flags) 447 { 448 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 449 450 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 451 amdgpu_ring_write(ring, seq); 452 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 453 amdgpu_ring_write(ring, addr & 0xffffffff); 454 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 455 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 456 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 457 amdgpu_ring_write(ring, 0); 458 459 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 460 amdgpu_ring_write(ring, 0); 461 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 462 amdgpu_ring_write(ring, 0); 463 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 464 amdgpu_ring_write(ring, 2); 465 } 466 467 /** 468 * uvd_v4_2_ring_test_ring - register write test 469 * 470 * @ring: amdgpu_ring pointer 471 * 472 * Test if we can successfully write to the context register 473 */ 474 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 475 { 476 struct amdgpu_device *adev = ring->adev; 477 uint32_t tmp = 0; 478 unsigned i; 479 int r; 480 481 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 482 r = amdgpu_ring_alloc(ring, 3); 483 if (r) { 484 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 485 ring->idx, r); 486 return r; 487 } 488 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 489 amdgpu_ring_write(ring, 0xDEADBEEF); 490 amdgpu_ring_commit(ring); 491 for (i = 0; i < adev->usec_timeout; i++) { 492 tmp = RREG32(mmUVD_CONTEXT_ID); 493 if (tmp == 0xDEADBEEF) 494 break; 495 DRM_UDELAY(1); 496 } 497 498 if (i < adev->usec_timeout) { 499 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 500 ring->idx, i); 501 } else { 502 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 503 ring->idx, tmp); 504 r = -EINVAL; 505 } 506 return r; 507 } 508 509 /** 510 * uvd_v4_2_ring_emit_ib - execute indirect buffer 511 * 512 * @ring: amdgpu_ring pointer 513 * @ib: indirect buffer to execute 514 * 515 * Write ring commands to execute the indirect buffer 516 */ 517 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 518 struct amdgpu_ib *ib, 519 unsigned vmid, bool ctx_switch) 520 { 521 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 522 amdgpu_ring_write(ring, ib->gpu_addr); 523 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 524 amdgpu_ring_write(ring, ib->length_dw); 525 } 526 527 static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 528 { 529 int i; 530 531 WARN_ON(ring->wptr % 2 || count % 2); 532 533 for (i = 0; i < count / 2; i++) { 534 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 535 amdgpu_ring_write(ring, 0); 536 } 537 } 538 539 /** 540 * uvd_v4_2_mc_resume - memory controller programming 541 * 542 * @adev: amdgpu_device pointer 543 * 544 * Let the UVD memory controller know it's offsets 545 */ 546 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 547 { 548 uint64_t addr; 549 uint32_t size; 550 551 /* programm the VCPU memory controller bits 0-27 */ 552 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 553 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; 554 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 555 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 556 557 addr += size; 558 size = AMDGPU_UVD_HEAP_SIZE >> 3; 559 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 560 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 561 562 addr += size; 563 size = (AMDGPU_UVD_STACK_SIZE + 564 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 565 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 566 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 567 568 /* bits 28-31 */ 569 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; 570 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 571 572 /* bits 32-39 */ 573 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; 574 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 575 576 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 577 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 578 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 579 } 580 581 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 582 bool enable) 583 { 584 u32 orig, data; 585 586 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 587 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 588 data |= 0xfff; 589 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 590 591 orig = data = RREG32(mmUVD_CGC_CTRL); 592 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 593 if (orig != data) 594 WREG32(mmUVD_CGC_CTRL, data); 595 } else { 596 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 597 data &= ~0xfff; 598 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 599 600 orig = data = RREG32(mmUVD_CGC_CTRL); 601 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 602 if (orig != data) 603 WREG32(mmUVD_CGC_CTRL, data); 604 } 605 } 606 607 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 608 bool sw_mode) 609 { 610 u32 tmp, tmp2; 611 612 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 613 614 tmp = RREG32(mmUVD_CGC_CTRL); 615 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 616 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 617 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 618 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 619 620 if (sw_mode) { 621 tmp &= ~0x7ffff800; 622 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 623 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 624 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 625 } else { 626 tmp |= 0x7ffff800; 627 tmp2 = 0; 628 } 629 630 WREG32(mmUVD_CGC_CTRL, tmp); 631 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 632 } 633 634 static bool uvd_v4_2_is_idle(void *handle) 635 { 636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 637 638 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 639 } 640 641 static int uvd_v4_2_wait_for_idle(void *handle) 642 { 643 unsigned i; 644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 645 646 for (i = 0; i < adev->usec_timeout; i++) { 647 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 648 return 0; 649 } 650 return -ETIMEDOUT; 651 } 652 653 static int uvd_v4_2_soft_reset(void *handle) 654 { 655 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 656 657 uvd_v4_2_stop(adev); 658 659 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 660 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 661 mdelay(5); 662 663 return uvd_v4_2_start(adev); 664 } 665 666 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 667 struct amdgpu_irq_src *source, 668 unsigned type, 669 enum amdgpu_interrupt_state state) 670 { 671 // TODO 672 return 0; 673 } 674 675 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 676 struct amdgpu_irq_src *source, 677 struct amdgpu_iv_entry *entry) 678 { 679 DRM_DEBUG("IH: UVD TRAP\n"); 680 amdgpu_fence_process(&adev->uvd.inst->ring); 681 return 0; 682 } 683 684 static int uvd_v4_2_set_clockgating_state(void *handle, 685 enum amd_clockgating_state state) 686 { 687 return 0; 688 } 689 690 static int uvd_v4_2_set_powergating_state(void *handle, 691 enum amd_powergating_state state) 692 { 693 /* This doesn't actually powergate the UVD block. 694 * That's done in the dpm code via the SMC. This 695 * just re-inits the block as necessary. The actual 696 * gating still happens in the dpm code. We should 697 * revisit this when there is a cleaner line between 698 * the smc and the hw blocks 699 */ 700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 701 702 if (state == AMD_PG_STATE_GATE) { 703 uvd_v4_2_stop(adev); 704 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 705 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 706 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) { 707 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 708 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 709 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 710 mdelay(20); 711 } 712 } 713 return 0; 714 } else { 715 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 716 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 717 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 718 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 719 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 720 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 721 mdelay(30); 722 } 723 } 724 return uvd_v4_2_start(adev); 725 } 726 } 727 728 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 729 .name = "uvd_v4_2", 730 .early_init = uvd_v4_2_early_init, 731 .late_init = NULL, 732 .sw_init = uvd_v4_2_sw_init, 733 .sw_fini = uvd_v4_2_sw_fini, 734 .hw_init = uvd_v4_2_hw_init, 735 .hw_fini = uvd_v4_2_hw_fini, 736 .suspend = uvd_v4_2_suspend, 737 .resume = uvd_v4_2_resume, 738 .is_idle = uvd_v4_2_is_idle, 739 .wait_for_idle = uvd_v4_2_wait_for_idle, 740 .soft_reset = uvd_v4_2_soft_reset, 741 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 742 .set_powergating_state = uvd_v4_2_set_powergating_state, 743 }; 744 745 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 746 .type = AMDGPU_RING_TYPE_UVD, 747 .align_mask = 0xf, 748 .support_64bit_ptrs = false, 749 .get_rptr = uvd_v4_2_ring_get_rptr, 750 .get_wptr = uvd_v4_2_ring_get_wptr, 751 .set_wptr = uvd_v4_2_ring_set_wptr, 752 .parse_cs = amdgpu_uvd_ring_parse_cs, 753 .emit_frame_size = 754 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 755 .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 756 .emit_ib = uvd_v4_2_ring_emit_ib, 757 .emit_fence = uvd_v4_2_ring_emit_fence, 758 .test_ring = uvd_v4_2_ring_test_ring, 759 .test_ib = amdgpu_uvd_ring_test_ib, 760 .insert_nop = uvd_v4_2_ring_insert_nop, 761 .pad_ib = amdgpu_ring_generic_pad_ib, 762 .begin_use = amdgpu_uvd_ring_begin_use, 763 .end_use = amdgpu_uvd_ring_end_use, 764 }; 765 766 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 767 { 768 adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; 769 } 770 771 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 772 .set = uvd_v4_2_set_interrupt_state, 773 .process = uvd_v4_2_process_interrupt, 774 }; 775 776 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 777 { 778 adev->uvd.inst->irq.num_types = 1; 779 adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; 780 } 781 782 const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 783 { 784 .type = AMD_IP_BLOCK_TYPE_UVD, 785 .major = 4, 786 .minor = 2, 787 .rev = 0, 788 .funcs = &uvd_v4_2_ip_funcs, 789 }; 790