1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "cikd.h" 30 31 #include "uvd/uvd_4_2_d.h" 32 #include "uvd/uvd_4_2_sh_mask.h" 33 34 #include "oss/oss_2_0_d.h" 35 #include "oss/oss_2_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 39 #include "smu/smu_7_0_1_d.h" 40 #include "smu/smu_7_0_1_sh_mask.h" 41 42 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 44 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45 static int uvd_v4_2_start(struct amdgpu_device *adev); 46 static void uvd_v4_2_stop(struct amdgpu_device *adev); 47 static int uvd_v4_2_set_clockgating_state(void *handle, 48 enum amd_clockgating_state state); 49 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 50 bool sw_mode); 51 /** 52 * uvd_v4_2_ring_get_rptr - get read pointer 53 * 54 * @ring: amdgpu_ring pointer 55 * 56 * Returns the current hardware read pointer 57 */ 58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 59 { 60 struct amdgpu_device *adev = ring->adev; 61 62 return RREG32(mmUVD_RBC_RB_RPTR); 63 } 64 65 /** 66 * uvd_v4_2_ring_get_wptr - get write pointer 67 * 68 * @ring: amdgpu_ring pointer 69 * 70 * Returns the current hardware write pointer 71 */ 72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 73 { 74 struct amdgpu_device *adev = ring->adev; 75 76 return RREG32(mmUVD_RBC_RB_WPTR); 77 } 78 79 /** 80 * uvd_v4_2_ring_set_wptr - set write pointer 81 * 82 * @ring: amdgpu_ring pointer 83 * 84 * Commits the write pointer to the hardware 85 */ 86 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 87 { 88 struct amdgpu_device *adev = ring->adev; 89 90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 91 } 92 93 static int uvd_v4_2_early_init(void *handle) 94 { 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 adev->uvd.num_uvd_inst = 1; 97 98 uvd_v4_2_set_ring_funcs(adev); 99 uvd_v4_2_set_irq_funcs(adev); 100 101 return 0; 102 } 103 104 static int uvd_v4_2_sw_init(void *handle) 105 { 106 struct amdgpu_ring *ring; 107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 108 int r; 109 110 /* UVD TRAP */ 111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 112 if (r) 113 return r; 114 115 r = amdgpu_uvd_sw_init(adev); 116 if (r) 117 return r; 118 119 ring = &adev->uvd.inst->ring; 120 sprintf(ring->name, "uvd"); 121 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 122 AMDGPU_RING_PRIO_DEFAULT); 123 if (r) 124 return r; 125 126 r = amdgpu_uvd_resume(adev); 127 if (r) 128 return r; 129 130 r = amdgpu_uvd_entity_init(adev); 131 132 return r; 133 } 134 135 static int uvd_v4_2_sw_fini(void *handle) 136 { 137 int r; 138 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 139 140 r = amdgpu_uvd_suspend(adev); 141 if (r) 142 return r; 143 144 return amdgpu_uvd_sw_fini(adev); 145 } 146 147 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 148 bool enable); 149 /** 150 * uvd_v4_2_hw_init - start and test UVD block 151 * 152 * @handle: handle used to pass amdgpu_device pointer 153 * 154 * Initialize the hardware, boot up the VCPU and do some testing 155 */ 156 static int uvd_v4_2_hw_init(void *handle) 157 { 158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 159 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 160 uint32_t tmp; 161 int r; 162 163 uvd_v4_2_enable_mgcg(adev, true); 164 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 165 166 r = amdgpu_ring_test_helper(ring); 167 if (r) 168 goto done; 169 170 r = amdgpu_ring_alloc(ring, 10); 171 if (r) { 172 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 173 goto done; 174 } 175 176 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 177 amdgpu_ring_write(ring, tmp); 178 amdgpu_ring_write(ring, 0xFFFFF); 179 180 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 181 amdgpu_ring_write(ring, tmp); 182 amdgpu_ring_write(ring, 0xFFFFF); 183 184 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 185 amdgpu_ring_write(ring, tmp); 186 amdgpu_ring_write(ring, 0xFFFFF); 187 188 /* Clear timeout status bits */ 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 190 amdgpu_ring_write(ring, 0x8); 191 192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 193 amdgpu_ring_write(ring, 3); 194 195 amdgpu_ring_commit(ring); 196 197 done: 198 if (!r) 199 DRM_INFO("UVD initialized successfully.\n"); 200 201 return r; 202 } 203 204 /** 205 * uvd_v4_2_hw_fini - stop the hardware block 206 * 207 * @handle: handle used to pass amdgpu_device pointer 208 * 209 * Stop the UVD block, mark ring as not ready any more 210 */ 211 static int uvd_v4_2_hw_fini(void *handle) 212 { 213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 214 215 if (RREG32(mmUVD_STATUS) != 0) 216 uvd_v4_2_stop(adev); 217 218 return 0; 219 } 220 221 static int uvd_v4_2_suspend(void *handle) 222 { 223 int r; 224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225 226 r = uvd_v4_2_hw_fini(adev); 227 if (r) 228 return r; 229 230 return amdgpu_uvd_suspend(adev); 231 } 232 233 static int uvd_v4_2_resume(void *handle) 234 { 235 int r; 236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 237 238 r = amdgpu_uvd_resume(adev); 239 if (r) 240 return r; 241 242 return uvd_v4_2_hw_init(adev); 243 } 244 245 /** 246 * uvd_v4_2_start - start UVD block 247 * 248 * @adev: amdgpu_device pointer 249 * 250 * Setup and start the UVD block 251 */ 252 static int uvd_v4_2_start(struct amdgpu_device *adev) 253 { 254 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 255 uint32_t rb_bufsz; 256 int i, j, r; 257 u32 tmp; 258 /* disable byte swapping */ 259 u32 lmi_swap_cntl = 0; 260 u32 mp_swap_cntl = 0; 261 262 /* set uvd busy */ 263 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); 264 265 uvd_v4_2_set_dcm(adev, true); 266 WREG32(mmUVD_CGC_GATE, 0); 267 268 /* take UVD block out of reset */ 269 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 270 mdelay(5); 271 272 /* enable VCPU clock */ 273 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 274 275 /* disable interupt */ 276 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 277 278 #ifdef __BIG_ENDIAN 279 /* swap (8 in 32) RB and IB */ 280 lmi_swap_cntl = 0xa; 281 mp_swap_cntl = 0; 282 #endif 283 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 284 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 285 /* initialize UVD memory controller */ 286 WREG32(mmUVD_LMI_CTRL, 0x203108); 287 288 tmp = RREG32(mmUVD_MPC_CNTL); 289 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); 290 291 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 292 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 293 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 294 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 295 WREG32(mmUVD_MPC_SET_ALU, 0); 296 WREG32(mmUVD_MPC_SET_MUX, 0x88); 297 298 uvd_v4_2_mc_resume(adev); 299 300 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); 301 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); 302 303 /* enable UMC */ 304 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 305 306 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 307 308 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 309 310 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 311 312 mdelay(10); 313 314 for (i = 0; i < 10; ++i) { 315 uint32_t status; 316 for (j = 0; j < 100; ++j) { 317 status = RREG32(mmUVD_STATUS); 318 if (status & 2) 319 break; 320 mdelay(10); 321 } 322 r = 0; 323 if (status & 2) 324 break; 325 326 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 327 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 328 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 329 mdelay(10); 330 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 331 mdelay(10); 332 r = -1; 333 } 334 335 if (r) { 336 DRM_ERROR("UVD not responding, giving up!!!\n"); 337 return r; 338 } 339 340 /* enable interupt */ 341 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 342 343 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); 344 345 /* force RBC into idle state */ 346 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 347 348 /* Set the write pointer delay */ 349 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 350 351 /* program the 4GB memory segment for rptr and ring buffer */ 352 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 353 (0x7 << 16) | (0x1 << 31)); 354 355 /* Initialize the ring buffer's read and write pointers */ 356 WREG32(mmUVD_RBC_RB_RPTR, 0x0); 357 358 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 359 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 360 361 /* set the ring address */ 362 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 363 364 /* Set ring buffer size */ 365 rb_bufsz = order_base_2(ring->ring_size); 366 rb_bufsz = (0x1 << 8) | rb_bufsz; 367 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 368 369 return 0; 370 } 371 372 /** 373 * uvd_v4_2_stop - stop UVD block 374 * 375 * @adev: amdgpu_device pointer 376 * 377 * stop the UVD block 378 */ 379 static void uvd_v4_2_stop(struct amdgpu_device *adev) 380 { 381 uint32_t i, j; 382 uint32_t status; 383 384 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 385 386 for (i = 0; i < 10; ++i) { 387 for (j = 0; j < 100; ++j) { 388 status = RREG32(mmUVD_STATUS); 389 if (status & 2) 390 break; 391 mdelay(1); 392 } 393 if (status & 2) 394 break; 395 } 396 397 for (i = 0; i < 10; ++i) { 398 for (j = 0; j < 100; ++j) { 399 status = RREG32(mmUVD_LMI_STATUS); 400 if (status & 0xf) 401 break; 402 mdelay(1); 403 } 404 if (status & 0xf) 405 break; 406 } 407 408 /* Stall UMC and register bus before resetting VCPU */ 409 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 410 411 for (i = 0; i < 10; ++i) { 412 for (j = 0; j < 100; ++j) { 413 status = RREG32(mmUVD_LMI_STATUS); 414 if (status & 0x240) 415 break; 416 mdelay(1); 417 } 418 if (status & 0x240) 419 break; 420 } 421 422 WREG32_P(0x3D49, 0, ~(1 << 2)); 423 424 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); 425 426 /* put LMI, VCPU, RBC etc... into reset */ 427 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 428 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 429 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 430 431 WREG32(mmUVD_STATUS, 0); 432 433 uvd_v4_2_set_dcm(adev, false); 434 } 435 436 /** 437 * uvd_v4_2_ring_emit_fence - emit an fence & trap command 438 * 439 * @ring: amdgpu_ring pointer 440 * @addr: address 441 * @seq: sequence number 442 * @fence: fence to emit 443 * 444 * Write a fence and a trap command to the ring. 445 */ 446 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 447 unsigned flags) 448 { 449 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 450 451 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 452 amdgpu_ring_write(ring, seq); 453 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 454 amdgpu_ring_write(ring, addr & 0xffffffff); 455 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 456 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 457 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 458 amdgpu_ring_write(ring, 0); 459 460 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 461 amdgpu_ring_write(ring, 0); 462 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 463 amdgpu_ring_write(ring, 0); 464 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 465 amdgpu_ring_write(ring, 2); 466 } 467 468 /** 469 * uvd_v4_2_ring_test_ring - register write test 470 * 471 * @ring: amdgpu_ring pointer 472 * 473 * Test if we can successfully write to the context register 474 */ 475 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 476 { 477 struct amdgpu_device *adev = ring->adev; 478 uint32_t tmp = 0; 479 unsigned i; 480 int r; 481 482 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 483 r = amdgpu_ring_alloc(ring, 3); 484 if (r) 485 return r; 486 487 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 488 amdgpu_ring_write(ring, 0xDEADBEEF); 489 amdgpu_ring_commit(ring); 490 for (i = 0; i < adev->usec_timeout; i++) { 491 tmp = RREG32(mmUVD_CONTEXT_ID); 492 if (tmp == 0xDEADBEEF) 493 break; 494 udelay(1); 495 } 496 497 if (i >= adev->usec_timeout) 498 r = -ETIMEDOUT; 499 500 return r; 501 } 502 503 /** 504 * uvd_v4_2_ring_emit_ib - execute indirect buffer 505 * 506 * @ring: amdgpu_ring pointer 507 * @job: iob associated with the indirect buffer 508 * @ib: indirect buffer to execute 509 * @flags: flags associated with the indirect buffer 510 * 511 * Write ring commands to execute the indirect buffer 512 */ 513 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 514 struct amdgpu_job *job, 515 struct amdgpu_ib *ib, 516 uint32_t flags) 517 { 518 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 519 amdgpu_ring_write(ring, ib->gpu_addr); 520 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 521 amdgpu_ring_write(ring, ib->length_dw); 522 } 523 524 static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 525 { 526 int i; 527 528 WARN_ON(ring->wptr % 2 || count % 2); 529 530 for (i = 0; i < count / 2; i++) { 531 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 532 amdgpu_ring_write(ring, 0); 533 } 534 } 535 536 /** 537 * uvd_v4_2_mc_resume - memory controller programming 538 * 539 * @adev: amdgpu_device pointer 540 * 541 * Let the UVD memory controller know it's offsets 542 */ 543 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 544 { 545 uint64_t addr; 546 uint32_t size; 547 548 /* program the VCPU memory controller bits 0-27 */ 549 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 550 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; 551 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 552 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 553 554 addr += size; 555 size = AMDGPU_UVD_HEAP_SIZE >> 3; 556 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 557 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 558 559 addr += size; 560 size = (AMDGPU_UVD_STACK_SIZE + 561 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 562 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 563 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 564 565 /* bits 28-31 */ 566 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; 567 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 568 569 /* bits 32-39 */ 570 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; 571 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 572 573 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 574 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 575 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 576 } 577 578 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 579 bool enable) 580 { 581 u32 orig, data; 582 583 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 584 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 585 data |= 0xfff; 586 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 587 588 orig = data = RREG32(mmUVD_CGC_CTRL); 589 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 590 if (orig != data) 591 WREG32(mmUVD_CGC_CTRL, data); 592 } else { 593 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 594 data &= ~0xfff; 595 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 596 597 orig = data = RREG32(mmUVD_CGC_CTRL); 598 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 599 if (orig != data) 600 WREG32(mmUVD_CGC_CTRL, data); 601 } 602 } 603 604 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 605 bool sw_mode) 606 { 607 u32 tmp, tmp2; 608 609 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 610 611 tmp = RREG32(mmUVD_CGC_CTRL); 612 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 613 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 614 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 615 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 616 617 if (sw_mode) { 618 tmp &= ~0x7ffff800; 619 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 620 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 621 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 622 } else { 623 tmp |= 0x7ffff800; 624 tmp2 = 0; 625 } 626 627 WREG32(mmUVD_CGC_CTRL, tmp); 628 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 629 } 630 631 static bool uvd_v4_2_is_idle(void *handle) 632 { 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 634 635 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 636 } 637 638 static int uvd_v4_2_wait_for_idle(void *handle) 639 { 640 unsigned i; 641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642 643 for (i = 0; i < adev->usec_timeout; i++) { 644 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 645 return 0; 646 } 647 return -ETIMEDOUT; 648 } 649 650 static int uvd_v4_2_soft_reset(void *handle) 651 { 652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653 654 uvd_v4_2_stop(adev); 655 656 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 657 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 658 mdelay(5); 659 660 return uvd_v4_2_start(adev); 661 } 662 663 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 664 struct amdgpu_irq_src *source, 665 unsigned type, 666 enum amdgpu_interrupt_state state) 667 { 668 // TODO 669 return 0; 670 } 671 672 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 673 struct amdgpu_irq_src *source, 674 struct amdgpu_iv_entry *entry) 675 { 676 DRM_DEBUG("IH: UVD TRAP\n"); 677 amdgpu_fence_process(&adev->uvd.inst->ring); 678 return 0; 679 } 680 681 static int uvd_v4_2_set_clockgating_state(void *handle, 682 enum amd_clockgating_state state) 683 { 684 return 0; 685 } 686 687 static int uvd_v4_2_set_powergating_state(void *handle, 688 enum amd_powergating_state state) 689 { 690 /* This doesn't actually powergate the UVD block. 691 * That's done in the dpm code via the SMC. This 692 * just re-inits the block as necessary. The actual 693 * gating still happens in the dpm code. We should 694 * revisit this when there is a cleaner line between 695 * the smc and the hw blocks 696 */ 697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 698 699 if (state == AMD_PG_STATE_GATE) { 700 uvd_v4_2_stop(adev); 701 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 702 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 703 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) { 704 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 705 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 706 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 707 mdelay(20); 708 } 709 } 710 return 0; 711 } else { 712 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 713 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 714 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 715 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 716 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 717 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 718 mdelay(30); 719 } 720 } 721 return uvd_v4_2_start(adev); 722 } 723 } 724 725 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 726 .name = "uvd_v4_2", 727 .early_init = uvd_v4_2_early_init, 728 .late_init = NULL, 729 .sw_init = uvd_v4_2_sw_init, 730 .sw_fini = uvd_v4_2_sw_fini, 731 .hw_init = uvd_v4_2_hw_init, 732 .hw_fini = uvd_v4_2_hw_fini, 733 .suspend = uvd_v4_2_suspend, 734 .resume = uvd_v4_2_resume, 735 .is_idle = uvd_v4_2_is_idle, 736 .wait_for_idle = uvd_v4_2_wait_for_idle, 737 .soft_reset = uvd_v4_2_soft_reset, 738 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 739 .set_powergating_state = uvd_v4_2_set_powergating_state, 740 }; 741 742 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 743 .type = AMDGPU_RING_TYPE_UVD, 744 .align_mask = 0xf, 745 .support_64bit_ptrs = false, 746 .no_user_fence = true, 747 .get_rptr = uvd_v4_2_ring_get_rptr, 748 .get_wptr = uvd_v4_2_ring_get_wptr, 749 .set_wptr = uvd_v4_2_ring_set_wptr, 750 .parse_cs = amdgpu_uvd_ring_parse_cs, 751 .emit_frame_size = 752 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 753 .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 754 .emit_ib = uvd_v4_2_ring_emit_ib, 755 .emit_fence = uvd_v4_2_ring_emit_fence, 756 .test_ring = uvd_v4_2_ring_test_ring, 757 .test_ib = amdgpu_uvd_ring_test_ib, 758 .insert_nop = uvd_v4_2_ring_insert_nop, 759 .pad_ib = amdgpu_ring_generic_pad_ib, 760 .begin_use = amdgpu_uvd_ring_begin_use, 761 .end_use = amdgpu_uvd_ring_end_use, 762 }; 763 764 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 765 { 766 adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; 767 } 768 769 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 770 .set = uvd_v4_2_set_interrupt_state, 771 .process = uvd_v4_2_process_interrupt, 772 }; 773 774 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 775 { 776 adev->uvd.inst->irq.num_types = 1; 777 adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; 778 } 779 780 const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 781 { 782 .type = AMD_IP_BLOCK_TYPE_UVD, 783 .major = 4, 784 .minor = 2, 785 .rev = 0, 786 .funcs = &uvd_v4_2_ip_funcs, 787 }; 788