1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "cikd.h" 30 31 #include "uvd/uvd_4_2_d.h" 32 #include "uvd/uvd_4_2_sh_mask.h" 33 34 #include "oss/oss_2_0_d.h" 35 #include "oss/oss_2_0_sh_mask.h" 36 37 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 38 static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 39 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 40 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 41 static int uvd_v4_2_start(struct amdgpu_device *adev); 42 static void uvd_v4_2_stop(struct amdgpu_device *adev); 43 44 /** 45 * uvd_v4_2_ring_get_rptr - get read pointer 46 * 47 * @ring: amdgpu_ring pointer 48 * 49 * Returns the current hardware read pointer 50 */ 51 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 52 { 53 struct amdgpu_device *adev = ring->adev; 54 55 return RREG32(mmUVD_RBC_RB_RPTR); 56 } 57 58 /** 59 * uvd_v4_2_ring_get_wptr - get write pointer 60 * 61 * @ring: amdgpu_ring pointer 62 * 63 * Returns the current hardware write pointer 64 */ 65 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 66 { 67 struct amdgpu_device *adev = ring->adev; 68 69 return RREG32(mmUVD_RBC_RB_WPTR); 70 } 71 72 /** 73 * uvd_v4_2_ring_set_wptr - set write pointer 74 * 75 * @ring: amdgpu_ring pointer 76 * 77 * Commits the write pointer to the hardware 78 */ 79 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 80 { 81 struct amdgpu_device *adev = ring->adev; 82 83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 84 } 85 86 static int uvd_v4_2_early_init(void *handle) 87 { 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 90 uvd_v4_2_set_ring_funcs(adev); 91 uvd_v4_2_set_irq_funcs(adev); 92 93 return 0; 94 } 95 96 static int uvd_v4_2_sw_init(void *handle) 97 { 98 struct amdgpu_ring *ring; 99 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 100 int r; 101 102 /* UVD TRAP */ 103 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 104 if (r) 105 return r; 106 107 r = amdgpu_uvd_sw_init(adev); 108 if (r) 109 return r; 110 111 r = amdgpu_uvd_resume(adev); 112 if (r) 113 return r; 114 115 ring = &adev->uvd.ring; 116 sprintf(ring->name, "uvd"); 117 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 118 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 119 120 return r; 121 } 122 123 static int uvd_v4_2_sw_fini(void *handle) 124 { 125 int r; 126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 127 128 r = amdgpu_uvd_suspend(adev); 129 if (r) 130 return r; 131 132 r = amdgpu_uvd_sw_fini(adev); 133 if (r) 134 return r; 135 136 return r; 137 } 138 139 /** 140 * uvd_v4_2_hw_init - start and test UVD block 141 * 142 * @adev: amdgpu_device pointer 143 * 144 * Initialize the hardware, boot up the VCPU and do some testing 145 */ 146 static int uvd_v4_2_hw_init(void *handle) 147 { 148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 149 struct amdgpu_ring *ring = &adev->uvd.ring; 150 uint32_t tmp; 151 int r; 152 153 /* raise clocks while booting up the VCPU */ 154 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 155 156 r = uvd_v4_2_start(adev); 157 if (r) 158 goto done; 159 160 ring->ready = true; 161 r = amdgpu_ring_test_ring(ring); 162 if (r) { 163 ring->ready = false; 164 goto done; 165 } 166 167 r = amdgpu_ring_alloc(ring, 10); 168 if (r) { 169 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170 goto done; 171 } 172 173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174 amdgpu_ring_write(ring, tmp); 175 amdgpu_ring_write(ring, 0xFFFFF); 176 177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178 amdgpu_ring_write(ring, tmp); 179 amdgpu_ring_write(ring, 0xFFFFF); 180 181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182 amdgpu_ring_write(ring, tmp); 183 amdgpu_ring_write(ring, 0xFFFFF); 184 185 /* Clear timeout status bits */ 186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187 amdgpu_ring_write(ring, 0x8); 188 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190 amdgpu_ring_write(ring, 3); 191 192 amdgpu_ring_commit(ring); 193 194 done: 195 /* lower clocks again */ 196 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 197 198 if (!r) 199 DRM_INFO("UVD initialized successfully.\n"); 200 201 return r; 202 } 203 204 /** 205 * uvd_v4_2_hw_fini - stop the hardware block 206 * 207 * @adev: amdgpu_device pointer 208 * 209 * Stop the UVD block, mark ring as not ready any more 210 */ 211 static int uvd_v4_2_hw_fini(void *handle) 212 { 213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 214 struct amdgpu_ring *ring = &adev->uvd.ring; 215 216 uvd_v4_2_stop(adev); 217 ring->ready = false; 218 219 return 0; 220 } 221 222 static int uvd_v4_2_suspend(void *handle) 223 { 224 int r; 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226 227 r = uvd_v4_2_hw_fini(adev); 228 if (r) 229 return r; 230 231 r = amdgpu_uvd_suspend(adev); 232 if (r) 233 return r; 234 235 return r; 236 } 237 238 static int uvd_v4_2_resume(void *handle) 239 { 240 int r; 241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 242 243 r = amdgpu_uvd_resume(adev); 244 if (r) 245 return r; 246 247 r = uvd_v4_2_hw_init(adev); 248 if (r) 249 return r; 250 251 return r; 252 } 253 254 /** 255 * uvd_v4_2_start - start UVD block 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Setup and start the UVD block 260 */ 261 static int uvd_v4_2_start(struct amdgpu_device *adev) 262 { 263 struct amdgpu_ring *ring = &adev->uvd.ring; 264 uint32_t rb_bufsz; 265 int i, j, r; 266 267 /* disable byte swapping */ 268 u32 lmi_swap_cntl = 0; 269 u32 mp_swap_cntl = 0; 270 271 uvd_v4_2_mc_resume(adev); 272 273 /* disable clock gating */ 274 WREG32(mmUVD_CGC_GATE, 0); 275 276 /* disable interupt */ 277 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 278 279 /* Stall UMC and register bus before resetting VCPU */ 280 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 281 mdelay(1); 282 283 /* put LMI, VCPU, RBC etc... into reset */ 284 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 285 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 286 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 287 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 288 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 289 mdelay(5); 290 291 /* take UVD block out of reset */ 292 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 293 mdelay(5); 294 295 /* initialize UVD memory controller */ 296 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 297 (1 << 21) | (1 << 9) | (1 << 20)); 298 299 #ifdef __BIG_ENDIAN 300 /* swap (8 in 32) RB and IB */ 301 lmi_swap_cntl = 0xa; 302 mp_swap_cntl = 0; 303 #endif 304 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 305 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 306 307 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 308 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 309 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 310 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 311 WREG32(mmUVD_MPC_SET_ALU, 0); 312 WREG32(mmUVD_MPC_SET_MUX, 0x88); 313 314 /* take all subblocks out of reset, except VCPU */ 315 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 316 mdelay(5); 317 318 /* enable VCPU clock */ 319 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 320 321 /* enable UMC */ 322 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 323 324 /* boot up the VCPU */ 325 WREG32(mmUVD_SOFT_RESET, 0); 326 mdelay(10); 327 328 for (i = 0; i < 10; ++i) { 329 uint32_t status; 330 for (j = 0; j < 100; ++j) { 331 status = RREG32(mmUVD_STATUS); 332 if (status & 2) 333 break; 334 mdelay(10); 335 } 336 r = 0; 337 if (status & 2) 338 break; 339 340 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 341 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 342 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 343 mdelay(10); 344 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 345 mdelay(10); 346 r = -1; 347 } 348 349 if (r) { 350 DRM_ERROR("UVD not responding, giving up!!!\n"); 351 return r; 352 } 353 354 /* enable interupt */ 355 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 356 357 /* force RBC into idle state */ 358 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 359 360 /* Set the write pointer delay */ 361 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 362 363 /* programm the 4GB memory segment for rptr and ring buffer */ 364 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 365 (0x7 << 16) | (0x1 << 31)); 366 367 /* Initialize the ring buffer's read and write pointers */ 368 WREG32(mmUVD_RBC_RB_RPTR, 0x0); 369 370 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 371 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 372 373 /* set the ring address */ 374 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 375 376 /* Set ring buffer size */ 377 rb_bufsz = order_base_2(ring->ring_size); 378 rb_bufsz = (0x1 << 8) | rb_bufsz; 379 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 380 381 return 0; 382 } 383 384 /** 385 * uvd_v4_2_stop - stop UVD block 386 * 387 * @adev: amdgpu_device pointer 388 * 389 * stop the UVD block 390 */ 391 static void uvd_v4_2_stop(struct amdgpu_device *adev) 392 { 393 /* force RBC into idle state */ 394 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 395 396 /* Stall UMC and register bus before resetting VCPU */ 397 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 398 mdelay(1); 399 400 /* put VCPU into reset */ 401 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 402 mdelay(5); 403 404 /* disable VCPU clock */ 405 WREG32(mmUVD_VCPU_CNTL, 0x0); 406 407 /* Unstall UMC and register bus */ 408 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 409 } 410 411 /** 412 * uvd_v4_2_ring_emit_fence - emit an fence & trap command 413 * 414 * @ring: amdgpu_ring pointer 415 * @fence: fence to emit 416 * 417 * Write a fence and a trap command to the ring. 418 */ 419 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 420 unsigned flags) 421 { 422 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 423 424 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 425 amdgpu_ring_write(ring, seq); 426 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 427 amdgpu_ring_write(ring, addr & 0xffffffff); 428 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 429 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 430 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 431 amdgpu_ring_write(ring, 0); 432 433 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 434 amdgpu_ring_write(ring, 0); 435 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 436 amdgpu_ring_write(ring, 0); 437 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 438 amdgpu_ring_write(ring, 2); 439 } 440 441 /** 442 * uvd_v4_2_ring_test_ring - register write test 443 * 444 * @ring: amdgpu_ring pointer 445 * 446 * Test if we can successfully write to the context register 447 */ 448 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 449 { 450 struct amdgpu_device *adev = ring->adev; 451 uint32_t tmp = 0; 452 unsigned i; 453 int r; 454 455 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 456 r = amdgpu_ring_alloc(ring, 3); 457 if (r) { 458 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 459 ring->idx, r); 460 return r; 461 } 462 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 463 amdgpu_ring_write(ring, 0xDEADBEEF); 464 amdgpu_ring_commit(ring); 465 for (i = 0; i < adev->usec_timeout; i++) { 466 tmp = RREG32(mmUVD_CONTEXT_ID); 467 if (tmp == 0xDEADBEEF) 468 break; 469 DRM_UDELAY(1); 470 } 471 472 if (i < adev->usec_timeout) { 473 DRM_INFO("ring test on %d succeeded in %d usecs\n", 474 ring->idx, i); 475 } else { 476 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 477 ring->idx, tmp); 478 r = -EINVAL; 479 } 480 return r; 481 } 482 483 /** 484 * uvd_v4_2_ring_emit_ib - execute indirect buffer 485 * 486 * @ring: amdgpu_ring pointer 487 * @ib: indirect buffer to execute 488 * 489 * Write ring commands to execute the indirect buffer 490 */ 491 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 492 struct amdgpu_ib *ib) 493 { 494 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 495 amdgpu_ring_write(ring, ib->gpu_addr); 496 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 497 amdgpu_ring_write(ring, ib->length_dw); 498 } 499 500 /** 501 * uvd_v4_2_ring_test_ib - test ib execution 502 * 503 * @ring: amdgpu_ring pointer 504 * 505 * Test if we can successfully execute an IB 506 */ 507 static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring) 508 { 509 struct amdgpu_device *adev = ring->adev; 510 struct fence *fence = NULL; 511 int r; 512 513 r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 514 if (r) { 515 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 516 return r; 517 } 518 519 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 520 if (r) { 521 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 522 goto error; 523 } 524 525 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 526 if (r) { 527 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 528 goto error; 529 } 530 531 r = fence_wait(fence, false); 532 if (r) { 533 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 534 goto error; 535 } 536 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 537 error: 538 fence_put(fence); 539 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 540 return r; 541 } 542 543 /** 544 * uvd_v4_2_mc_resume - memory controller programming 545 * 546 * @adev: amdgpu_device pointer 547 * 548 * Let the UVD memory controller know it's offsets 549 */ 550 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 551 { 552 uint64_t addr; 553 uint32_t size; 554 555 /* programm the VCPU memory controller bits 0-27 */ 556 addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 557 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 558 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 559 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 560 561 addr += size; 562 size = AMDGPU_UVD_STACK_SIZE >> 3; 563 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 564 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 565 566 addr += size; 567 size = AMDGPU_UVD_HEAP_SIZE >> 3; 568 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 569 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 570 571 /* bits 28-31 */ 572 addr = (adev->uvd.gpu_addr >> 28) & 0xF; 573 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 574 575 /* bits 32-39 */ 576 addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 577 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 578 579 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 580 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 581 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 582 583 uvd_v4_2_init_cg(adev); 584 } 585 586 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 587 bool enable) 588 { 589 u32 orig, data; 590 591 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 592 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 593 data = 0xfff; 594 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 595 596 orig = data = RREG32(mmUVD_CGC_CTRL); 597 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 598 if (orig != data) 599 WREG32(mmUVD_CGC_CTRL, data); 600 } else { 601 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 602 data &= ~0xfff; 603 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 604 605 orig = data = RREG32(mmUVD_CGC_CTRL); 606 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 607 if (orig != data) 608 WREG32(mmUVD_CGC_CTRL, data); 609 } 610 } 611 612 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 613 bool sw_mode) 614 { 615 u32 tmp, tmp2; 616 617 tmp = RREG32(mmUVD_CGC_CTRL); 618 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 619 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 620 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 621 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 622 623 if (sw_mode) { 624 tmp &= ~0x7ffff800; 625 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 626 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 627 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 628 } else { 629 tmp |= 0x7ffff800; 630 tmp2 = 0; 631 } 632 633 WREG32(mmUVD_CGC_CTRL, tmp); 634 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 635 } 636 637 static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 638 { 639 bool hw_mode = true; 640 641 if (hw_mode) { 642 uvd_v4_2_set_dcm(adev, false); 643 } else { 644 u32 tmp = RREG32(mmUVD_CGC_CTRL); 645 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 646 WREG32(mmUVD_CGC_CTRL, tmp); 647 } 648 } 649 650 static bool uvd_v4_2_is_idle(void *handle) 651 { 652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653 654 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 655 } 656 657 static int uvd_v4_2_wait_for_idle(void *handle) 658 { 659 unsigned i; 660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 661 662 for (i = 0; i < adev->usec_timeout; i++) { 663 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 664 return 0; 665 } 666 return -ETIMEDOUT; 667 } 668 669 static int uvd_v4_2_soft_reset(void *handle) 670 { 671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 672 673 uvd_v4_2_stop(adev); 674 675 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 676 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 677 mdelay(5); 678 679 return uvd_v4_2_start(adev); 680 } 681 682 static void uvd_v4_2_print_status(void *handle) 683 { 684 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 685 dev_info(adev->dev, "UVD 4.2 registers\n"); 686 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 687 RREG32(mmUVD_SEMA_ADDR_LOW)); 688 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 689 RREG32(mmUVD_SEMA_ADDR_HIGH)); 690 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 691 RREG32(mmUVD_SEMA_CMD)); 692 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 693 RREG32(mmUVD_GPCOM_VCPU_CMD)); 694 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 695 RREG32(mmUVD_GPCOM_VCPU_DATA0)); 696 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 697 RREG32(mmUVD_GPCOM_VCPU_DATA1)); 698 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 699 RREG32(mmUVD_ENGINE_CNTL)); 700 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 701 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 702 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 703 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 704 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 705 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 706 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 707 RREG32(mmUVD_SEMA_CNTL)); 708 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 709 RREG32(mmUVD_LMI_EXT40_ADDR)); 710 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 711 RREG32(mmUVD_CTX_INDEX)); 712 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 713 RREG32(mmUVD_CTX_DATA)); 714 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 715 RREG32(mmUVD_CGC_GATE)); 716 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 717 RREG32(mmUVD_CGC_CTRL)); 718 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 719 RREG32(mmUVD_LMI_CTRL2)); 720 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 721 RREG32(mmUVD_MASTINT_EN)); 722 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 723 RREG32(mmUVD_LMI_ADDR_EXT)); 724 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 725 RREG32(mmUVD_LMI_CTRL)); 726 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 727 RREG32(mmUVD_LMI_SWAP_CNTL)); 728 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 729 RREG32(mmUVD_MP_SWAP_CNTL)); 730 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 731 RREG32(mmUVD_MPC_SET_MUXA0)); 732 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 733 RREG32(mmUVD_MPC_SET_MUXA1)); 734 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 735 RREG32(mmUVD_MPC_SET_MUXB0)); 736 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 737 RREG32(mmUVD_MPC_SET_MUXB1)); 738 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 739 RREG32(mmUVD_MPC_SET_MUX)); 740 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 741 RREG32(mmUVD_MPC_SET_ALU)); 742 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 743 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 744 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 745 RREG32(mmUVD_VCPU_CACHE_SIZE0)); 746 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 747 RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 748 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 749 RREG32(mmUVD_VCPU_CACHE_SIZE1)); 750 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 751 RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 752 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 753 RREG32(mmUVD_VCPU_CACHE_SIZE2)); 754 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 755 RREG32(mmUVD_VCPU_CNTL)); 756 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 757 RREG32(mmUVD_SOFT_RESET)); 758 dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n", 759 RREG32(mmUVD_RBC_IB_BASE)); 760 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 761 RREG32(mmUVD_RBC_IB_SIZE)); 762 dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n", 763 RREG32(mmUVD_RBC_RB_BASE)); 764 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 765 RREG32(mmUVD_RBC_RB_RPTR)); 766 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 767 RREG32(mmUVD_RBC_RB_WPTR)); 768 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 769 RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 770 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 771 RREG32(mmUVD_RBC_RB_CNTL)); 772 dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 773 RREG32(mmUVD_STATUS)); 774 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 775 RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 776 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 777 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 778 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 779 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 780 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 781 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 782 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 783 RREG32(mmUVD_CONTEXT_ID)); 784 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 785 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 786 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 787 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 788 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 789 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 790 791 } 792 793 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 794 struct amdgpu_irq_src *source, 795 unsigned type, 796 enum amdgpu_interrupt_state state) 797 { 798 // TODO 799 return 0; 800 } 801 802 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 803 struct amdgpu_irq_src *source, 804 struct amdgpu_iv_entry *entry) 805 { 806 DRM_DEBUG("IH: UVD TRAP\n"); 807 amdgpu_fence_process(&adev->uvd.ring); 808 return 0; 809 } 810 811 static int uvd_v4_2_set_clockgating_state(void *handle, 812 enum amd_clockgating_state state) 813 { 814 bool gate = false; 815 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 816 817 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 818 return 0; 819 820 if (state == AMD_CG_STATE_GATE) 821 gate = true; 822 823 uvd_v4_2_enable_mgcg(adev, gate); 824 825 return 0; 826 } 827 828 static int uvd_v4_2_set_powergating_state(void *handle, 829 enum amd_powergating_state state) 830 { 831 /* This doesn't actually powergate the UVD block. 832 * That's done in the dpm code via the SMC. This 833 * just re-inits the block as necessary. The actual 834 * gating still happens in the dpm code. We should 835 * revisit this when there is a cleaner line between 836 * the smc and the hw blocks 837 */ 838 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 839 840 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 841 return 0; 842 843 if (state == AMD_PG_STATE_GATE) { 844 uvd_v4_2_stop(adev); 845 return 0; 846 } else { 847 return uvd_v4_2_start(adev); 848 } 849 } 850 851 const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 852 .early_init = uvd_v4_2_early_init, 853 .late_init = NULL, 854 .sw_init = uvd_v4_2_sw_init, 855 .sw_fini = uvd_v4_2_sw_fini, 856 .hw_init = uvd_v4_2_hw_init, 857 .hw_fini = uvd_v4_2_hw_fini, 858 .suspend = uvd_v4_2_suspend, 859 .resume = uvd_v4_2_resume, 860 .is_idle = uvd_v4_2_is_idle, 861 .wait_for_idle = uvd_v4_2_wait_for_idle, 862 .soft_reset = uvd_v4_2_soft_reset, 863 .print_status = uvd_v4_2_print_status, 864 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 865 .set_powergating_state = uvd_v4_2_set_powergating_state, 866 }; 867 868 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 869 .get_rptr = uvd_v4_2_ring_get_rptr, 870 .get_wptr = uvd_v4_2_ring_get_wptr, 871 .set_wptr = uvd_v4_2_ring_set_wptr, 872 .parse_cs = amdgpu_uvd_ring_parse_cs, 873 .emit_ib = uvd_v4_2_ring_emit_ib, 874 .emit_fence = uvd_v4_2_ring_emit_fence, 875 .test_ring = uvd_v4_2_ring_test_ring, 876 .test_ib = uvd_v4_2_ring_test_ib, 877 .insert_nop = amdgpu_ring_insert_nop, 878 .pad_ib = amdgpu_ring_generic_pad_ib, 879 }; 880 881 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 882 { 883 adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 884 } 885 886 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 887 .set = uvd_v4_2_set_interrupt_state, 888 .process = uvd_v4_2_process_interrupt, 889 }; 890 891 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 892 { 893 adev->uvd.irq.num_types = 1; 894 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 895 } 896