1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "cikd.h" 30 31 #include "uvd/uvd_4_2_d.h" 32 #include "uvd/uvd_4_2_sh_mask.h" 33 34 #include "oss/oss_2_0_d.h" 35 #include "oss/oss_2_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 39 #include "smu/smu_7_0_1_d.h" 40 #include "smu/smu_7_0_1_sh_mask.h" 41 42 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 44 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45 static int uvd_v4_2_start(struct amdgpu_device *adev); 46 static void uvd_v4_2_stop(struct amdgpu_device *adev); 47 static int uvd_v4_2_set_clockgating_state(void *handle, 48 enum amd_clockgating_state state); 49 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 50 bool sw_mode); 51 /** 52 * uvd_v4_2_ring_get_rptr - get read pointer 53 * 54 * @ring: amdgpu_ring pointer 55 * 56 * Returns the current hardware read pointer 57 */ 58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 59 { 60 struct amdgpu_device *adev = ring->adev; 61 62 return RREG32(mmUVD_RBC_RB_RPTR); 63 } 64 65 /** 66 * uvd_v4_2_ring_get_wptr - get write pointer 67 * 68 * @ring: amdgpu_ring pointer 69 * 70 * Returns the current hardware write pointer 71 */ 72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 73 { 74 struct amdgpu_device *adev = ring->adev; 75 76 return RREG32(mmUVD_RBC_RB_WPTR); 77 } 78 79 /** 80 * uvd_v4_2_ring_set_wptr - set write pointer 81 * 82 * @ring: amdgpu_ring pointer 83 * 84 * Commits the write pointer to the hardware 85 */ 86 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 87 { 88 struct amdgpu_device *adev = ring->adev; 89 90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 91 } 92 93 static int uvd_v4_2_early_init(void *handle) 94 { 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 adev->uvd.num_uvd_inst = 1; 97 98 uvd_v4_2_set_ring_funcs(adev); 99 uvd_v4_2_set_irq_funcs(adev); 100 101 return 0; 102 } 103 104 static int uvd_v4_2_sw_init(void *handle) 105 { 106 struct amdgpu_ring *ring; 107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 108 int r; 109 110 /* UVD TRAP */ 111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 112 if (r) 113 return r; 114 115 r = amdgpu_uvd_sw_init(adev); 116 if (r) 117 return r; 118 119 r = amdgpu_uvd_resume(adev); 120 if (r) 121 return r; 122 123 ring = &adev->uvd.inst->ring; 124 sprintf(ring->name, "uvd"); 125 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 126 if (r) 127 return r; 128 129 r = amdgpu_uvd_entity_init(adev); 130 131 return r; 132 } 133 134 static int uvd_v4_2_sw_fini(void *handle) 135 { 136 int r; 137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 138 139 r = amdgpu_uvd_suspend(adev); 140 if (r) 141 return r; 142 143 return amdgpu_uvd_sw_fini(adev); 144 } 145 146 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 147 bool enable); 148 /** 149 * uvd_v4_2_hw_init - start and test UVD block 150 * 151 * @adev: amdgpu_device pointer 152 * 153 * Initialize the hardware, boot up the VCPU and do some testing 154 */ 155 static int uvd_v4_2_hw_init(void *handle) 156 { 157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 158 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 159 uint32_t tmp; 160 int r; 161 162 uvd_v4_2_enable_mgcg(adev, true); 163 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 164 165 ring->ready = true; 166 r = amdgpu_ring_test_ring(ring); 167 if (r) { 168 ring->ready = false; 169 goto done; 170 } 171 172 r = amdgpu_ring_alloc(ring, 10); 173 if (r) { 174 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 175 goto done; 176 } 177 178 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 179 amdgpu_ring_write(ring, tmp); 180 amdgpu_ring_write(ring, 0xFFFFF); 181 182 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 183 amdgpu_ring_write(ring, tmp); 184 amdgpu_ring_write(ring, 0xFFFFF); 185 186 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 187 amdgpu_ring_write(ring, tmp); 188 amdgpu_ring_write(ring, 0xFFFFF); 189 190 /* Clear timeout status bits */ 191 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 192 amdgpu_ring_write(ring, 0x8); 193 194 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 195 amdgpu_ring_write(ring, 3); 196 197 amdgpu_ring_commit(ring); 198 199 done: 200 if (!r) 201 DRM_INFO("UVD initialized successfully.\n"); 202 203 return r; 204 } 205 206 /** 207 * uvd_v4_2_hw_fini - stop the hardware block 208 * 209 * @adev: amdgpu_device pointer 210 * 211 * Stop the UVD block, mark ring as not ready any more 212 */ 213 static int uvd_v4_2_hw_fini(void *handle) 214 { 215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 216 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 217 218 if (RREG32(mmUVD_STATUS) != 0) 219 uvd_v4_2_stop(adev); 220 221 ring->ready = false; 222 223 return 0; 224 } 225 226 static int uvd_v4_2_suspend(void *handle) 227 { 228 int r; 229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 230 231 r = uvd_v4_2_hw_fini(adev); 232 if (r) 233 return r; 234 235 return amdgpu_uvd_suspend(adev); 236 } 237 238 static int uvd_v4_2_resume(void *handle) 239 { 240 int r; 241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 242 243 r = amdgpu_uvd_resume(adev); 244 if (r) 245 return r; 246 247 return uvd_v4_2_hw_init(adev); 248 } 249 250 /** 251 * uvd_v4_2_start - start UVD block 252 * 253 * @adev: amdgpu_device pointer 254 * 255 * Setup and start the UVD block 256 */ 257 static int uvd_v4_2_start(struct amdgpu_device *adev) 258 { 259 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 260 uint32_t rb_bufsz; 261 int i, j, r; 262 u32 tmp; 263 /* disable byte swapping */ 264 u32 lmi_swap_cntl = 0; 265 u32 mp_swap_cntl = 0; 266 267 /* set uvd busy */ 268 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); 269 270 uvd_v4_2_set_dcm(adev, true); 271 WREG32(mmUVD_CGC_GATE, 0); 272 273 /* take UVD block out of reset */ 274 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 275 mdelay(5); 276 277 /* enable VCPU clock */ 278 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 279 280 /* disable interupt */ 281 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 282 283 #ifdef __BIG_ENDIAN 284 /* swap (8 in 32) RB and IB */ 285 lmi_swap_cntl = 0xa; 286 mp_swap_cntl = 0; 287 #endif 288 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 289 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 290 /* initialize UVD memory controller */ 291 WREG32(mmUVD_LMI_CTRL, 0x203108); 292 293 tmp = RREG32(mmUVD_MPC_CNTL); 294 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); 295 296 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 297 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 298 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 299 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 300 WREG32(mmUVD_MPC_SET_ALU, 0); 301 WREG32(mmUVD_MPC_SET_MUX, 0x88); 302 303 uvd_v4_2_mc_resume(adev); 304 305 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); 306 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); 307 308 /* enable UMC */ 309 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 310 311 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 312 313 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 314 315 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 316 317 mdelay(10); 318 319 for (i = 0; i < 10; ++i) { 320 uint32_t status; 321 for (j = 0; j < 100; ++j) { 322 status = RREG32(mmUVD_STATUS); 323 if (status & 2) 324 break; 325 mdelay(10); 326 } 327 r = 0; 328 if (status & 2) 329 break; 330 331 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 332 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 333 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 334 mdelay(10); 335 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 336 mdelay(10); 337 r = -1; 338 } 339 340 if (r) { 341 DRM_ERROR("UVD not responding, giving up!!!\n"); 342 return r; 343 } 344 345 /* enable interupt */ 346 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 347 348 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); 349 350 /* force RBC into idle state */ 351 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 352 353 /* Set the write pointer delay */ 354 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 355 356 /* programm the 4GB memory segment for rptr and ring buffer */ 357 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 358 (0x7 << 16) | (0x1 << 31)); 359 360 /* Initialize the ring buffer's read and write pointers */ 361 WREG32(mmUVD_RBC_RB_RPTR, 0x0); 362 363 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 364 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 365 366 /* set the ring address */ 367 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 368 369 /* Set ring buffer size */ 370 rb_bufsz = order_base_2(ring->ring_size); 371 rb_bufsz = (0x1 << 8) | rb_bufsz; 372 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 373 374 return 0; 375 } 376 377 /** 378 * uvd_v4_2_stop - stop UVD block 379 * 380 * @adev: amdgpu_device pointer 381 * 382 * stop the UVD block 383 */ 384 static void uvd_v4_2_stop(struct amdgpu_device *adev) 385 { 386 uint32_t i, j; 387 uint32_t status; 388 389 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 390 391 for (i = 0; i < 10; ++i) { 392 for (j = 0; j < 100; ++j) { 393 status = RREG32(mmUVD_STATUS); 394 if (status & 2) 395 break; 396 mdelay(1); 397 } 398 if (status & 2) 399 break; 400 } 401 402 for (i = 0; i < 10; ++i) { 403 for (j = 0; j < 100; ++j) { 404 status = RREG32(mmUVD_LMI_STATUS); 405 if (status & 0xf) 406 break; 407 mdelay(1); 408 } 409 if (status & 0xf) 410 break; 411 } 412 413 /* Stall UMC and register bus before resetting VCPU */ 414 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 415 416 for (i = 0; i < 10; ++i) { 417 for (j = 0; j < 100; ++j) { 418 status = RREG32(mmUVD_LMI_STATUS); 419 if (status & 0x240) 420 break; 421 mdelay(1); 422 } 423 if (status & 0x240) 424 break; 425 } 426 427 WREG32_P(0x3D49, 0, ~(1 << 2)); 428 429 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); 430 431 /* put LMI, VCPU, RBC etc... into reset */ 432 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 433 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 434 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 435 436 WREG32(mmUVD_STATUS, 0); 437 438 uvd_v4_2_set_dcm(adev, false); 439 } 440 441 /** 442 * uvd_v4_2_ring_emit_fence - emit an fence & trap command 443 * 444 * @ring: amdgpu_ring pointer 445 * @fence: fence to emit 446 * 447 * Write a fence and a trap command to the ring. 448 */ 449 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 450 unsigned flags) 451 { 452 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 453 454 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 455 amdgpu_ring_write(ring, seq); 456 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 457 amdgpu_ring_write(ring, addr & 0xffffffff); 458 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 459 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 460 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 461 amdgpu_ring_write(ring, 0); 462 463 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 464 amdgpu_ring_write(ring, 0); 465 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 466 amdgpu_ring_write(ring, 0); 467 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 468 amdgpu_ring_write(ring, 2); 469 } 470 471 /** 472 * uvd_v4_2_ring_test_ring - register write test 473 * 474 * @ring: amdgpu_ring pointer 475 * 476 * Test if we can successfully write to the context register 477 */ 478 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 479 { 480 struct amdgpu_device *adev = ring->adev; 481 uint32_t tmp = 0; 482 unsigned i; 483 int r; 484 485 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 486 r = amdgpu_ring_alloc(ring, 3); 487 if (r) { 488 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 489 ring->idx, r); 490 return r; 491 } 492 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 493 amdgpu_ring_write(ring, 0xDEADBEEF); 494 amdgpu_ring_commit(ring); 495 for (i = 0; i < adev->usec_timeout; i++) { 496 tmp = RREG32(mmUVD_CONTEXT_ID); 497 if (tmp == 0xDEADBEEF) 498 break; 499 DRM_UDELAY(1); 500 } 501 502 if (i < adev->usec_timeout) { 503 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 504 ring->idx, i); 505 } else { 506 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 507 ring->idx, tmp); 508 r = -EINVAL; 509 } 510 return r; 511 } 512 513 /** 514 * uvd_v4_2_ring_emit_ib - execute indirect buffer 515 * 516 * @ring: amdgpu_ring pointer 517 * @ib: indirect buffer to execute 518 * 519 * Write ring commands to execute the indirect buffer 520 */ 521 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 522 struct amdgpu_ib *ib, 523 unsigned vmid, bool ctx_switch) 524 { 525 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 526 amdgpu_ring_write(ring, ib->gpu_addr); 527 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 528 amdgpu_ring_write(ring, ib->length_dw); 529 } 530 531 static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 532 { 533 int i; 534 535 WARN_ON(ring->wptr % 2 || count % 2); 536 537 for (i = 0; i < count / 2; i++) { 538 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 539 amdgpu_ring_write(ring, 0); 540 } 541 } 542 543 /** 544 * uvd_v4_2_mc_resume - memory controller programming 545 * 546 * @adev: amdgpu_device pointer 547 * 548 * Let the UVD memory controller know it's offsets 549 */ 550 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 551 { 552 uint64_t addr; 553 uint32_t size; 554 555 /* programm the VCPU memory controller bits 0-27 */ 556 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 557 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; 558 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 559 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 560 561 addr += size; 562 size = AMDGPU_UVD_HEAP_SIZE >> 3; 563 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 564 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 565 566 addr += size; 567 size = (AMDGPU_UVD_STACK_SIZE + 568 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 569 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 570 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 571 572 /* bits 28-31 */ 573 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; 574 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 575 576 /* bits 32-39 */ 577 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; 578 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 579 580 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 581 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 582 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 583 } 584 585 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 586 bool enable) 587 { 588 u32 orig, data; 589 590 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 591 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 592 data |= 0xfff; 593 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 594 595 orig = data = RREG32(mmUVD_CGC_CTRL); 596 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 597 if (orig != data) 598 WREG32(mmUVD_CGC_CTRL, data); 599 } else { 600 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 601 data &= ~0xfff; 602 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 603 604 orig = data = RREG32(mmUVD_CGC_CTRL); 605 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 606 if (orig != data) 607 WREG32(mmUVD_CGC_CTRL, data); 608 } 609 } 610 611 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 612 bool sw_mode) 613 { 614 u32 tmp, tmp2; 615 616 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 617 618 tmp = RREG32(mmUVD_CGC_CTRL); 619 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 620 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 621 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 622 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 623 624 if (sw_mode) { 625 tmp &= ~0x7ffff800; 626 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 627 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 628 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 629 } else { 630 tmp |= 0x7ffff800; 631 tmp2 = 0; 632 } 633 634 WREG32(mmUVD_CGC_CTRL, tmp); 635 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 636 } 637 638 static bool uvd_v4_2_is_idle(void *handle) 639 { 640 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 641 642 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 643 } 644 645 static int uvd_v4_2_wait_for_idle(void *handle) 646 { 647 unsigned i; 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 650 for (i = 0; i < adev->usec_timeout; i++) { 651 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 652 return 0; 653 } 654 return -ETIMEDOUT; 655 } 656 657 static int uvd_v4_2_soft_reset(void *handle) 658 { 659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660 661 uvd_v4_2_stop(adev); 662 663 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 664 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 665 mdelay(5); 666 667 return uvd_v4_2_start(adev); 668 } 669 670 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 671 struct amdgpu_irq_src *source, 672 unsigned type, 673 enum amdgpu_interrupt_state state) 674 { 675 // TODO 676 return 0; 677 } 678 679 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 680 struct amdgpu_irq_src *source, 681 struct amdgpu_iv_entry *entry) 682 { 683 DRM_DEBUG("IH: UVD TRAP\n"); 684 amdgpu_fence_process(&adev->uvd.inst->ring); 685 return 0; 686 } 687 688 static int uvd_v4_2_set_clockgating_state(void *handle, 689 enum amd_clockgating_state state) 690 { 691 return 0; 692 } 693 694 static int uvd_v4_2_set_powergating_state(void *handle, 695 enum amd_powergating_state state) 696 { 697 /* This doesn't actually powergate the UVD block. 698 * That's done in the dpm code via the SMC. This 699 * just re-inits the block as necessary. The actual 700 * gating still happens in the dpm code. We should 701 * revisit this when there is a cleaner line between 702 * the smc and the hw blocks 703 */ 704 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 705 706 if (state == AMD_PG_STATE_GATE) { 707 uvd_v4_2_stop(adev); 708 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 709 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 710 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) { 711 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 712 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 713 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 714 mdelay(20); 715 } 716 } 717 return 0; 718 } else { 719 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 720 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 721 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 722 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 723 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 724 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 725 mdelay(30); 726 } 727 } 728 return uvd_v4_2_start(adev); 729 } 730 } 731 732 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 733 .name = "uvd_v4_2", 734 .early_init = uvd_v4_2_early_init, 735 .late_init = NULL, 736 .sw_init = uvd_v4_2_sw_init, 737 .sw_fini = uvd_v4_2_sw_fini, 738 .hw_init = uvd_v4_2_hw_init, 739 .hw_fini = uvd_v4_2_hw_fini, 740 .suspend = uvd_v4_2_suspend, 741 .resume = uvd_v4_2_resume, 742 .is_idle = uvd_v4_2_is_idle, 743 .wait_for_idle = uvd_v4_2_wait_for_idle, 744 .soft_reset = uvd_v4_2_soft_reset, 745 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 746 .set_powergating_state = uvd_v4_2_set_powergating_state, 747 }; 748 749 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 750 .type = AMDGPU_RING_TYPE_UVD, 751 .align_mask = 0xf, 752 .support_64bit_ptrs = false, 753 .get_rptr = uvd_v4_2_ring_get_rptr, 754 .get_wptr = uvd_v4_2_ring_get_wptr, 755 .set_wptr = uvd_v4_2_ring_set_wptr, 756 .parse_cs = amdgpu_uvd_ring_parse_cs, 757 .emit_frame_size = 758 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 759 .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 760 .emit_ib = uvd_v4_2_ring_emit_ib, 761 .emit_fence = uvd_v4_2_ring_emit_fence, 762 .test_ring = uvd_v4_2_ring_test_ring, 763 .test_ib = amdgpu_uvd_ring_test_ib, 764 .insert_nop = uvd_v4_2_ring_insert_nop, 765 .pad_ib = amdgpu_ring_generic_pad_ib, 766 .begin_use = amdgpu_uvd_ring_begin_use, 767 .end_use = amdgpu_uvd_ring_end_use, 768 }; 769 770 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 771 { 772 adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; 773 } 774 775 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 776 .set = uvd_v4_2_set_interrupt_state, 777 .process = uvd_v4_2_process_interrupt, 778 }; 779 780 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 781 { 782 adev->uvd.inst->irq.num_types = 1; 783 adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; 784 } 785 786 const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 787 { 788 .type = AMD_IP_BLOCK_TYPE_UVD, 789 .major = 4, 790 .minor = 2, 791 .rev = 0, 792 .funcs = &uvd_v4_2_ip_funcs, 793 }; 794