1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37d5b4e25dSChristian König #include "bif/bif_4_1_d.h" 38d5b4e25dSChristian König 394be5097cSRex Zhu #include "smu/smu_7_0_1_d.h" 404be5097cSRex Zhu #include "smu/smu_7_0_1_sh_mask.h" 414be5097cSRex Zhu 42a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 44a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 46a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 47aa4747c0SRex Zhu static int uvd_v4_2_set_clockgating_state(void *handle, 48aa4747c0SRex Zhu enum amd_clockgating_state state); 49ca581e45SRex Zhu static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 50ca581e45SRex Zhu bool sw_mode); 51a2e73f56SAlex Deucher /** 52a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 53a2e73f56SAlex Deucher * 54a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 55a2e73f56SAlex Deucher * 56a2e73f56SAlex Deucher * Returns the current hardware read pointer 57a2e73f56SAlex Deucher */ 58a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 59a2e73f56SAlex Deucher { 60a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 61a2e73f56SAlex Deucher 62a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 63a2e73f56SAlex Deucher } 64a2e73f56SAlex Deucher 65a2e73f56SAlex Deucher /** 66a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 67a2e73f56SAlex Deucher * 68a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 69a2e73f56SAlex Deucher * 70a2e73f56SAlex Deucher * Returns the current hardware write pointer 71a2e73f56SAlex Deucher */ 72a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 73a2e73f56SAlex Deucher { 74a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 75a2e73f56SAlex Deucher 76a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 77a2e73f56SAlex Deucher } 78a2e73f56SAlex Deucher 79a2e73f56SAlex Deucher /** 80a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 81a2e73f56SAlex Deucher * 82a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 83a2e73f56SAlex Deucher * 84a2e73f56SAlex Deucher * Commits the write pointer to the hardware 85a2e73f56SAlex Deucher */ 86a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 87a2e73f56SAlex Deucher { 88a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 89a2e73f56SAlex Deucher 90a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 91a2e73f56SAlex Deucher } 92a2e73f56SAlex Deucher 935fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 94a2e73f56SAlex Deucher { 955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 965fc3aeebSyanyang1 97a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 98a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 99a2e73f56SAlex Deucher 100a2e73f56SAlex Deucher return 0; 101a2e73f56SAlex Deucher } 102a2e73f56SAlex Deucher 1035fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 104a2e73f56SAlex Deucher { 105a2e73f56SAlex Deucher struct amdgpu_ring *ring; 1065fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 107a2e73f56SAlex Deucher int r; 108a2e73f56SAlex Deucher 109a2e73f56SAlex Deucher /* UVD TRAP */ 110a2e73f56SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 111a2e73f56SAlex Deucher if (r) 112a2e73f56SAlex Deucher return r; 113a2e73f56SAlex Deucher 114a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 115a2e73f56SAlex Deucher if (r) 116a2e73f56SAlex Deucher return r; 117a2e73f56SAlex Deucher 118a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 119a2e73f56SAlex Deucher if (r) 120a2e73f56SAlex Deucher return r; 121a2e73f56SAlex Deucher 122a2e73f56SAlex Deucher ring = &adev->uvd.ring; 123a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 12479887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 125a2e73f56SAlex Deucher 126a2e73f56SAlex Deucher return r; 127a2e73f56SAlex Deucher } 128a2e73f56SAlex Deucher 1295fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 130a2e73f56SAlex Deucher { 131a2e73f56SAlex Deucher int r; 1325fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 133a2e73f56SAlex Deucher 134a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 135a2e73f56SAlex Deucher if (r) 136a2e73f56SAlex Deucher return r; 137a2e73f56SAlex Deucher 138a2e73f56SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 139a2e73f56SAlex Deucher if (r) 140a2e73f56SAlex Deucher return r; 141a2e73f56SAlex Deucher 142a2e73f56SAlex Deucher return r; 143a2e73f56SAlex Deucher } 144ca581e45SRex Zhu static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 145ca581e45SRex Zhu bool enable); 146a2e73f56SAlex Deucher /** 147a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 148a2e73f56SAlex Deucher * 149a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 150a2e73f56SAlex Deucher * 151a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 152a2e73f56SAlex Deucher */ 1535fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 154a2e73f56SAlex Deucher { 1555fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 156a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 157a2e73f56SAlex Deucher uint32_t tmp; 158a2e73f56SAlex Deucher int r; 159a2e73f56SAlex Deucher 160ca581e45SRex Zhu uvd_v4_2_enable_mgcg(adev, true); 161aa4747c0SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 162a2e73f56SAlex Deucher r = uvd_v4_2_start(adev); 163a2e73f56SAlex Deucher if (r) 164a2e73f56SAlex Deucher goto done; 165a2e73f56SAlex Deucher 166a2e73f56SAlex Deucher ring->ready = true; 167a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 168a2e73f56SAlex Deucher if (r) { 169a2e73f56SAlex Deucher ring->ready = false; 170a2e73f56SAlex Deucher goto done; 171a2e73f56SAlex Deucher } 172a2e73f56SAlex Deucher 173a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 174a2e73f56SAlex Deucher if (r) { 175a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 176a2e73f56SAlex Deucher goto done; 177a2e73f56SAlex Deucher } 178a2e73f56SAlex Deucher 179a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 180a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 181a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 182a2e73f56SAlex Deucher 183a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 184a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 185a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 186a2e73f56SAlex Deucher 187a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 188a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 189a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 190a2e73f56SAlex Deucher 191a2e73f56SAlex Deucher /* Clear timeout status bits */ 192a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 193a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 194a2e73f56SAlex Deucher 195a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 196a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 197a2e73f56SAlex Deucher 198a27de35cSChristian König amdgpu_ring_commit(ring); 199a2e73f56SAlex Deucher 200a2e73f56SAlex Deucher done: 201a2e73f56SAlex Deucher 202a2e73f56SAlex Deucher if (!r) 203a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 204a2e73f56SAlex Deucher 205a2e73f56SAlex Deucher return r; 206a2e73f56SAlex Deucher } 207a2e73f56SAlex Deucher 208a2e73f56SAlex Deucher /** 209a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 210a2e73f56SAlex Deucher * 211a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 212a2e73f56SAlex Deucher * 213a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 214a2e73f56SAlex Deucher */ 2155fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 216a2e73f56SAlex Deucher { 2175fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 219a2e73f56SAlex Deucher 220a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 221a2e73f56SAlex Deucher ring->ready = false; 222a2e73f56SAlex Deucher 223a2e73f56SAlex Deucher return 0; 224a2e73f56SAlex Deucher } 225a2e73f56SAlex Deucher 2265fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 227a2e73f56SAlex Deucher { 228a2e73f56SAlex Deucher int r; 2295fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 230a2e73f56SAlex Deucher 2313f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 232a2e73f56SAlex Deucher if (r) 233a2e73f56SAlex Deucher return r; 234a2e73f56SAlex Deucher 2353f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 236a2e73f56SAlex Deucher if (r) 237a2e73f56SAlex Deucher return r; 238a2e73f56SAlex Deucher 239a2e73f56SAlex Deucher return r; 240a2e73f56SAlex Deucher } 241a2e73f56SAlex Deucher 2425fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 243a2e73f56SAlex Deucher { 244a2e73f56SAlex Deucher int r; 2455fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 246a2e73f56SAlex Deucher 247a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 248a2e73f56SAlex Deucher if (r) 249a2e73f56SAlex Deucher return r; 250a2e73f56SAlex Deucher 251a2e73f56SAlex Deucher r = uvd_v4_2_hw_init(adev); 252a2e73f56SAlex Deucher if (r) 253a2e73f56SAlex Deucher return r; 254a2e73f56SAlex Deucher 255a2e73f56SAlex Deucher return r; 256a2e73f56SAlex Deucher } 257a2e73f56SAlex Deucher 258a2e73f56SAlex Deucher /** 259a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 260a2e73f56SAlex Deucher * 261a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 262a2e73f56SAlex Deucher * 263a2e73f56SAlex Deucher * Setup and start the UVD block 264a2e73f56SAlex Deucher */ 265a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 266a2e73f56SAlex Deucher { 267a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 268a2e73f56SAlex Deucher uint32_t rb_bufsz; 269a2e73f56SAlex Deucher int i, j, r; 270a2e73f56SAlex Deucher /* disable byte swapping */ 271a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 272a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 273a2e73f56SAlex Deucher 274ca581e45SRex Zhu WREG32(mmUVD_CGC_GATE, 0); 275ca581e45SRex Zhu uvd_v4_2_set_dcm(adev, true); 276ca581e45SRex Zhu 277a2e73f56SAlex Deucher uvd_v4_2_mc_resume(adev); 278a2e73f56SAlex Deucher 279a2e73f56SAlex Deucher /* disable interupt */ 280a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 281a2e73f56SAlex Deucher 282a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 283a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 284a2e73f56SAlex Deucher mdelay(1); 285a2e73f56SAlex Deucher 286a2e73f56SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 287a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 288a2e73f56SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 289a2e73f56SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 290a2e73f56SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 291a2e73f56SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 292a2e73f56SAlex Deucher mdelay(5); 293a2e73f56SAlex Deucher 294a2e73f56SAlex Deucher /* take UVD block out of reset */ 295a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 296a2e73f56SAlex Deucher mdelay(5); 297a2e73f56SAlex Deucher 298a2e73f56SAlex Deucher /* initialize UVD memory controller */ 299a2e73f56SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 300a2e73f56SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 301a2e73f56SAlex Deucher 302a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 303a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 304a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 305a2e73f56SAlex Deucher mp_swap_cntl = 0; 306a2e73f56SAlex Deucher #endif 307a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 308a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 309a2e73f56SAlex Deucher 310a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 311a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 312a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 313a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 314a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 315a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 316a2e73f56SAlex Deucher 317a2e73f56SAlex Deucher /* take all subblocks out of reset, except VCPU */ 318a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 319a2e73f56SAlex Deucher mdelay(5); 320a2e73f56SAlex Deucher 321a2e73f56SAlex Deucher /* enable VCPU clock */ 322a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 323a2e73f56SAlex Deucher 324a2e73f56SAlex Deucher /* enable UMC */ 325a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 326a2e73f56SAlex Deucher 327a2e73f56SAlex Deucher /* boot up the VCPU */ 328a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 329a2e73f56SAlex Deucher mdelay(10); 330a2e73f56SAlex Deucher 331a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 332a2e73f56SAlex Deucher uint32_t status; 333a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 334a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 335a2e73f56SAlex Deucher if (status & 2) 336a2e73f56SAlex Deucher break; 337a2e73f56SAlex Deucher mdelay(10); 338a2e73f56SAlex Deucher } 339a2e73f56SAlex Deucher r = 0; 340a2e73f56SAlex Deucher if (status & 2) 341a2e73f56SAlex Deucher break; 342a2e73f56SAlex Deucher 343a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 344a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 345a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 346a2e73f56SAlex Deucher mdelay(10); 347a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 348a2e73f56SAlex Deucher mdelay(10); 349a2e73f56SAlex Deucher r = -1; 350a2e73f56SAlex Deucher } 351a2e73f56SAlex Deucher 352a2e73f56SAlex Deucher if (r) { 353a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 354a2e73f56SAlex Deucher return r; 355a2e73f56SAlex Deucher } 356a2e73f56SAlex Deucher 357a2e73f56SAlex Deucher /* enable interupt */ 358a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 359a2e73f56SAlex Deucher 360a2e73f56SAlex Deucher /* force RBC into idle state */ 361a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 362a2e73f56SAlex Deucher 363a2e73f56SAlex Deucher /* Set the write pointer delay */ 364a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 365a2e73f56SAlex Deucher 366a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 367a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 368a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 369a2e73f56SAlex Deucher 370a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 371a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 372a2e73f56SAlex Deucher 373a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 374a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 375a2e73f56SAlex Deucher 376a2e73f56SAlex Deucher /* set the ring address */ 377a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 378a2e73f56SAlex Deucher 379a2e73f56SAlex Deucher /* Set ring buffer size */ 380a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 381a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 382a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 383a2e73f56SAlex Deucher 384a2e73f56SAlex Deucher return 0; 385a2e73f56SAlex Deucher } 386a2e73f56SAlex Deucher 387a2e73f56SAlex Deucher /** 388a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 389a2e73f56SAlex Deucher * 390a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 391a2e73f56SAlex Deucher * 392a2e73f56SAlex Deucher * stop the UVD block 393a2e73f56SAlex Deucher */ 394a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 395a2e73f56SAlex Deucher { 396a2e73f56SAlex Deucher /* force RBC into idle state */ 397a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 398a2e73f56SAlex Deucher 399a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 400a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 401a2e73f56SAlex Deucher mdelay(1); 402a2e73f56SAlex Deucher 403a2e73f56SAlex Deucher /* put VCPU into reset */ 404a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 405a2e73f56SAlex Deucher mdelay(5); 406a2e73f56SAlex Deucher 407a2e73f56SAlex Deucher /* disable VCPU clock */ 408a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 409a2e73f56SAlex Deucher 410a2e73f56SAlex Deucher /* Unstall UMC and register bus */ 411a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 412ca581e45SRex Zhu 413ca581e45SRex Zhu uvd_v4_2_set_dcm(adev, false); 414a2e73f56SAlex Deucher } 415a2e73f56SAlex Deucher 416a2e73f56SAlex Deucher /** 417a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 418a2e73f56SAlex Deucher * 419a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 420a2e73f56SAlex Deucher * @fence: fence to emit 421a2e73f56SAlex Deucher * 422a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 423a2e73f56SAlex Deucher */ 424a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 425890ee23fSChunming Zhou unsigned flags) 426a2e73f56SAlex Deucher { 427890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 428a2e73f56SAlex Deucher 429a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 430a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 431a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 432a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 433a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 434a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 435a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 436a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 437a2e73f56SAlex Deucher 438a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 439a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 440a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 441a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 442a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 443a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 444a2e73f56SAlex Deucher } 445a2e73f56SAlex Deucher 446a2e73f56SAlex Deucher /** 447d5b4e25dSChristian König * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush 448d5b4e25dSChristian König * 449d5b4e25dSChristian König * @ring: amdgpu_ring pointer 450d5b4e25dSChristian König * 451d5b4e25dSChristian König * Emits an hdp flush. 452d5b4e25dSChristian König */ 453d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 454d5b4e25dSChristian König { 455d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 456d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 457d5b4e25dSChristian König } 458d5b4e25dSChristian König 459d5b4e25dSChristian König /** 460d5b4e25dSChristian König * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate 461d5b4e25dSChristian König * 462d5b4e25dSChristian König * @ring: amdgpu_ring pointer 463d5b4e25dSChristian König * 464d5b4e25dSChristian König * Emits an hdp invalidate. 465d5b4e25dSChristian König */ 466d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 467d5b4e25dSChristian König { 468d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 469d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 470d5b4e25dSChristian König } 471d5b4e25dSChristian König 472d5b4e25dSChristian König /** 473a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 474a2e73f56SAlex Deucher * 475a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 476a2e73f56SAlex Deucher * 477a2e73f56SAlex Deucher * Test if we can successfully write to the context register 478a2e73f56SAlex Deucher */ 479a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 480a2e73f56SAlex Deucher { 481a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 482a2e73f56SAlex Deucher uint32_t tmp = 0; 483a2e73f56SAlex Deucher unsigned i; 484a2e73f56SAlex Deucher int r; 485a2e73f56SAlex Deucher 486a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 487a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 488a2e73f56SAlex Deucher if (r) { 489a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 490a2e73f56SAlex Deucher ring->idx, r); 491a2e73f56SAlex Deucher return r; 492a2e73f56SAlex Deucher } 493a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 494a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 495a27de35cSChristian König amdgpu_ring_commit(ring); 496a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 497a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 498a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 499a2e73f56SAlex Deucher break; 500a2e73f56SAlex Deucher DRM_UDELAY(1); 501a2e73f56SAlex Deucher } 502a2e73f56SAlex Deucher 503a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 504a2e73f56SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 505a2e73f56SAlex Deucher ring->idx, i); 506a2e73f56SAlex Deucher } else { 507a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 508a2e73f56SAlex Deucher ring->idx, tmp); 509a2e73f56SAlex Deucher r = -EINVAL; 510a2e73f56SAlex Deucher } 511a2e73f56SAlex Deucher return r; 512a2e73f56SAlex Deucher } 513a2e73f56SAlex Deucher 514a2e73f56SAlex Deucher /** 515a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 516a2e73f56SAlex Deucher * 517a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 518a2e73f56SAlex Deucher * @ib: indirect buffer to execute 519a2e73f56SAlex Deucher * 520a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 521a2e73f56SAlex Deucher */ 522a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 523d88bf583SChristian König struct amdgpu_ib *ib, 524d88bf583SChristian König unsigned vm_id, bool ctx_switch) 525a2e73f56SAlex Deucher { 526a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 527a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 528a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 529a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 530a2e73f56SAlex Deucher } 531a2e73f56SAlex Deucher 532a2e73f56SAlex Deucher /** 533a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 534a2e73f56SAlex Deucher * 535a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 536a2e73f56SAlex Deucher * 537a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 538a2e73f56SAlex Deucher */ 539a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 540a2e73f56SAlex Deucher { 541a2e73f56SAlex Deucher uint64_t addr; 542a2e73f56SAlex Deucher uint32_t size; 543a2e73f56SAlex Deucher 544a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 545a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 546a2e73f56SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 547a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 548a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 549a2e73f56SAlex Deucher 550a2e73f56SAlex Deucher addr += size; 551c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 552a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 553a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 554a2e73f56SAlex Deucher 555a2e73f56SAlex Deucher addr += size; 556c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 557c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 558a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 559a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 560a2e73f56SAlex Deucher 561a2e73f56SAlex Deucher /* bits 28-31 */ 562a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 563a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 564a2e73f56SAlex Deucher 565a2e73f56SAlex Deucher /* bits 32-39 */ 566a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 567a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 568a2e73f56SAlex Deucher 56976ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 57076ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 57176ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 572a2e73f56SAlex Deucher } 573a2e73f56SAlex Deucher 574a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 575a2e73f56SAlex Deucher bool enable) 576a2e73f56SAlex Deucher { 577a2e73f56SAlex Deucher u32 orig, data; 578a2e73f56SAlex Deucher 579e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 580a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 581aa4747c0SRex Zhu data |= 0xfff; 582a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 583a2e73f56SAlex Deucher 584a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 585a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 586a2e73f56SAlex Deucher if (orig != data) 587a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 588a2e73f56SAlex Deucher } else { 589a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 590a2e73f56SAlex Deucher data &= ~0xfff; 591a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 592a2e73f56SAlex Deucher 593a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 594a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 595a2e73f56SAlex Deucher if (orig != data) 596a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 597a2e73f56SAlex Deucher } 598a2e73f56SAlex Deucher } 599a2e73f56SAlex Deucher 600a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 601a2e73f56SAlex Deucher bool sw_mode) 602a2e73f56SAlex Deucher { 603a2e73f56SAlex Deucher u32 tmp, tmp2; 604a2e73f56SAlex Deucher 605953618cfSRex Zhu WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 606953618cfSRex Zhu 607a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 608a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 609a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 610a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 611a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 612a2e73f56SAlex Deucher 613a2e73f56SAlex Deucher if (sw_mode) { 614a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 615a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 616a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 617a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 618a2e73f56SAlex Deucher } else { 619a2e73f56SAlex Deucher tmp |= 0x7ffff800; 620a2e73f56SAlex Deucher tmp2 = 0; 621a2e73f56SAlex Deucher } 622a2e73f56SAlex Deucher 623a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 624a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 625a2e73f56SAlex Deucher } 626a2e73f56SAlex Deucher 6275fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 628a2e73f56SAlex Deucher { 6295fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6305fc3aeebSyanyang1 631a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 632a2e73f56SAlex Deucher } 633a2e73f56SAlex Deucher 6345fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 635a2e73f56SAlex Deucher { 636a2e73f56SAlex Deucher unsigned i; 6375fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 638a2e73f56SAlex Deucher 639a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 640a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 641a2e73f56SAlex Deucher return 0; 642a2e73f56SAlex Deucher } 643a2e73f56SAlex Deucher return -ETIMEDOUT; 644a2e73f56SAlex Deucher } 645a2e73f56SAlex Deucher 6465fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 647a2e73f56SAlex Deucher { 6485fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6495fc3aeebSyanyang1 650a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 651a2e73f56SAlex Deucher 652a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 653a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 654a2e73f56SAlex Deucher mdelay(5); 655a2e73f56SAlex Deucher 656a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 657a2e73f56SAlex Deucher } 658a2e73f56SAlex Deucher 659a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 660a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 661a2e73f56SAlex Deucher unsigned type, 662a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 663a2e73f56SAlex Deucher { 664a2e73f56SAlex Deucher // TODO 665a2e73f56SAlex Deucher return 0; 666a2e73f56SAlex Deucher } 667a2e73f56SAlex Deucher 668a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 669a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 670a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 671a2e73f56SAlex Deucher { 672a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 673a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 674a2e73f56SAlex Deucher return 0; 675a2e73f56SAlex Deucher } 676a2e73f56SAlex Deucher 6775fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 6785fc3aeebSyanyang1 enum amd_clockgating_state state) 679a2e73f56SAlex Deucher { 680a2e73f56SAlex Deucher return 0; 681a2e73f56SAlex Deucher } 682a2e73f56SAlex Deucher 6835fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 6845fc3aeebSyanyang1 enum amd_powergating_state state) 685a2e73f56SAlex Deucher { 686a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 687a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 688a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 689a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 690a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 691a2e73f56SAlex Deucher * the smc and the hw blocks 692a2e73f56SAlex Deucher */ 6935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6945fc3aeebSyanyang1 6955fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 696a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 697a2e73f56SAlex Deucher return 0; 698a2e73f56SAlex Deucher } else { 699a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 700a2e73f56SAlex Deucher } 701a2e73f56SAlex Deucher } 702a2e73f56SAlex Deucher 703a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 70488a907d6STom St Denis .name = "uvd_v4_2", 705a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 706a2e73f56SAlex Deucher .late_init = NULL, 707a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 708a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 709a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 710a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 711a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 712a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 713a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 714a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 715a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 716a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 717a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 718a2e73f56SAlex Deucher }; 719a2e73f56SAlex Deucher 720a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 72121cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 72279887142SChristian König .align_mask = 0xf, 72379887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 724a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 725a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 726a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 727a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 728e12f3d7aSChristian König .emit_frame_size = 729e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_flush */ 730e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ 731e12f3d7aSChristian König 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 732e12f3d7aSChristian König .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 733a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 734a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 735d5b4e25dSChristian König .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, 736d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, 737a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 7388de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 739edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 7409e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 741c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 742c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 743a2e73f56SAlex Deucher }; 744a2e73f56SAlex Deucher 745a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 746a2e73f56SAlex Deucher { 747a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 748a2e73f56SAlex Deucher } 749a2e73f56SAlex Deucher 750a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 751a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 752a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 753a2e73f56SAlex Deucher }; 754a2e73f56SAlex Deucher 755a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 756a2e73f56SAlex Deucher { 757a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 758a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 759a2e73f56SAlex Deucher } 760a1255107SAlex Deucher 761a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 762a1255107SAlex Deucher { 763a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 764a1255107SAlex Deucher .major = 4, 765a1255107SAlex Deucher .minor = 2, 766a1255107SAlex Deucher .rev = 0, 767a1255107SAlex Deucher .funcs = &uvd_v4_2_ip_funcs, 768a1255107SAlex Deucher }; 769