1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37d5b4e25dSChristian König #include "bif/bif_4_1_d.h" 38d5b4e25dSChristian König 39a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 40a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 41a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 42a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 44a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 45a2e73f56SAlex Deucher 46a2e73f56SAlex Deucher /** 47a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 48a2e73f56SAlex Deucher * 49a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 50a2e73f56SAlex Deucher * 51a2e73f56SAlex Deucher * Returns the current hardware read pointer 52a2e73f56SAlex Deucher */ 53a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 54a2e73f56SAlex Deucher { 55a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 56a2e73f56SAlex Deucher 57a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 58a2e73f56SAlex Deucher } 59a2e73f56SAlex Deucher 60a2e73f56SAlex Deucher /** 61a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 62a2e73f56SAlex Deucher * 63a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 64a2e73f56SAlex Deucher * 65a2e73f56SAlex Deucher * Returns the current hardware write pointer 66a2e73f56SAlex Deucher */ 67a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 68a2e73f56SAlex Deucher { 69a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 70a2e73f56SAlex Deucher 71a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 72a2e73f56SAlex Deucher } 73a2e73f56SAlex Deucher 74a2e73f56SAlex Deucher /** 75a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 76a2e73f56SAlex Deucher * 77a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 78a2e73f56SAlex Deucher * 79a2e73f56SAlex Deucher * Commits the write pointer to the hardware 80a2e73f56SAlex Deucher */ 81a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 82a2e73f56SAlex Deucher { 83a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 84a2e73f56SAlex Deucher 85a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 86a2e73f56SAlex Deucher } 87a2e73f56SAlex Deucher 885fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 89a2e73f56SAlex Deucher { 905fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 915fc3aeebSyanyang1 92a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 93a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 94a2e73f56SAlex Deucher 95a2e73f56SAlex Deucher return 0; 96a2e73f56SAlex Deucher } 97a2e73f56SAlex Deucher 985fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 99a2e73f56SAlex Deucher { 100a2e73f56SAlex Deucher struct amdgpu_ring *ring; 1015fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102a2e73f56SAlex Deucher int r; 103a2e73f56SAlex Deucher 104a2e73f56SAlex Deucher /* UVD TRAP */ 105a2e73f56SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 106a2e73f56SAlex Deucher if (r) 107a2e73f56SAlex Deucher return r; 108a2e73f56SAlex Deucher 109a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 110a2e73f56SAlex Deucher if (r) 111a2e73f56SAlex Deucher return r; 112a2e73f56SAlex Deucher 113a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 114a2e73f56SAlex Deucher if (r) 115a2e73f56SAlex Deucher return r; 116a2e73f56SAlex Deucher 117a2e73f56SAlex Deucher ring = &adev->uvd.ring; 118a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 119a3f1cf35SChristian König r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, 120a2e73f56SAlex Deucher &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 121a2e73f56SAlex Deucher 122a2e73f56SAlex Deucher return r; 123a2e73f56SAlex Deucher } 124a2e73f56SAlex Deucher 1255fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 126a2e73f56SAlex Deucher { 127a2e73f56SAlex Deucher int r; 1285fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 129a2e73f56SAlex Deucher 130a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 131a2e73f56SAlex Deucher if (r) 132a2e73f56SAlex Deucher return r; 133a2e73f56SAlex Deucher 134a2e73f56SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 135a2e73f56SAlex Deucher if (r) 136a2e73f56SAlex Deucher return r; 137a2e73f56SAlex Deucher 138a2e73f56SAlex Deucher return r; 139a2e73f56SAlex Deucher } 140a2e73f56SAlex Deucher 141a2e73f56SAlex Deucher /** 142a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 143a2e73f56SAlex Deucher * 144a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 145a2e73f56SAlex Deucher * 146a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 147a2e73f56SAlex Deucher */ 1485fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 149a2e73f56SAlex Deucher { 1505fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 151a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 152a2e73f56SAlex Deucher uint32_t tmp; 153a2e73f56SAlex Deucher int r; 154a2e73f56SAlex Deucher 155a2e73f56SAlex Deucher /* raise clocks while booting up the VCPU */ 156a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 157a2e73f56SAlex Deucher 158a2e73f56SAlex Deucher r = uvd_v4_2_start(adev); 159a2e73f56SAlex Deucher if (r) 160a2e73f56SAlex Deucher goto done; 161a2e73f56SAlex Deucher 162a2e73f56SAlex Deucher ring->ready = true; 163a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 164a2e73f56SAlex Deucher if (r) { 165a2e73f56SAlex Deucher ring->ready = false; 166a2e73f56SAlex Deucher goto done; 167a2e73f56SAlex Deucher } 168a2e73f56SAlex Deucher 169a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 170a2e73f56SAlex Deucher if (r) { 171a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 172a2e73f56SAlex Deucher goto done; 173a2e73f56SAlex Deucher } 174a2e73f56SAlex Deucher 175a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 176a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 177a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 178a2e73f56SAlex Deucher 179a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 180a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 181a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 182a2e73f56SAlex Deucher 183a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 184a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 185a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 186a2e73f56SAlex Deucher 187a2e73f56SAlex Deucher /* Clear timeout status bits */ 188a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 189a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 190a2e73f56SAlex Deucher 191a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 192a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 193a2e73f56SAlex Deucher 194a27de35cSChristian König amdgpu_ring_commit(ring); 195a2e73f56SAlex Deucher 196a2e73f56SAlex Deucher done: 197a2e73f56SAlex Deucher /* lower clocks again */ 198a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 199a2e73f56SAlex Deucher 200a2e73f56SAlex Deucher if (!r) 201a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 202a2e73f56SAlex Deucher 203a2e73f56SAlex Deucher return r; 204a2e73f56SAlex Deucher } 205a2e73f56SAlex Deucher 206a2e73f56SAlex Deucher /** 207a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 208a2e73f56SAlex Deucher * 209a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 210a2e73f56SAlex Deucher * 211a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 212a2e73f56SAlex Deucher */ 2135fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 214a2e73f56SAlex Deucher { 2155fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 216a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 217a2e73f56SAlex Deucher 218a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 219a2e73f56SAlex Deucher ring->ready = false; 220a2e73f56SAlex Deucher 221a2e73f56SAlex Deucher return 0; 222a2e73f56SAlex Deucher } 223a2e73f56SAlex Deucher 2245fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 225a2e73f56SAlex Deucher { 226a2e73f56SAlex Deucher int r; 2275fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 228a2e73f56SAlex Deucher 2293f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 230a2e73f56SAlex Deucher if (r) 231a2e73f56SAlex Deucher return r; 232a2e73f56SAlex Deucher 2333f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 234a2e73f56SAlex Deucher if (r) 235a2e73f56SAlex Deucher return r; 236a2e73f56SAlex Deucher 237a2e73f56SAlex Deucher return r; 238a2e73f56SAlex Deucher } 239a2e73f56SAlex Deucher 2405fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 241a2e73f56SAlex Deucher { 242a2e73f56SAlex Deucher int r; 2435fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 244a2e73f56SAlex Deucher 245a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 246a2e73f56SAlex Deucher if (r) 247a2e73f56SAlex Deucher return r; 248a2e73f56SAlex Deucher 249a2e73f56SAlex Deucher r = uvd_v4_2_hw_init(adev); 250a2e73f56SAlex Deucher if (r) 251a2e73f56SAlex Deucher return r; 252a2e73f56SAlex Deucher 253a2e73f56SAlex Deucher return r; 254a2e73f56SAlex Deucher } 255a2e73f56SAlex Deucher 256a2e73f56SAlex Deucher /** 257a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 258a2e73f56SAlex Deucher * 259a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 260a2e73f56SAlex Deucher * 261a2e73f56SAlex Deucher * Setup and start the UVD block 262a2e73f56SAlex Deucher */ 263a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 264a2e73f56SAlex Deucher { 265a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 266a2e73f56SAlex Deucher uint32_t rb_bufsz; 267a2e73f56SAlex Deucher int i, j, r; 268a2e73f56SAlex Deucher 269a2e73f56SAlex Deucher /* disable byte swapping */ 270a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 271a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 272a2e73f56SAlex Deucher 273a2e73f56SAlex Deucher uvd_v4_2_mc_resume(adev); 274a2e73f56SAlex Deucher 275a2e73f56SAlex Deucher /* disable clock gating */ 276a2e73f56SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 277a2e73f56SAlex Deucher 278a2e73f56SAlex Deucher /* disable interupt */ 279a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 280a2e73f56SAlex Deucher 281a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 282a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 283a2e73f56SAlex Deucher mdelay(1); 284a2e73f56SAlex Deucher 285a2e73f56SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 286a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 287a2e73f56SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 288a2e73f56SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 289a2e73f56SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 290a2e73f56SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 291a2e73f56SAlex Deucher mdelay(5); 292a2e73f56SAlex Deucher 293a2e73f56SAlex Deucher /* take UVD block out of reset */ 294a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 295a2e73f56SAlex Deucher mdelay(5); 296a2e73f56SAlex Deucher 297a2e73f56SAlex Deucher /* initialize UVD memory controller */ 298a2e73f56SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 299a2e73f56SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 300a2e73f56SAlex Deucher 301a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 302a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 303a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 304a2e73f56SAlex Deucher mp_swap_cntl = 0; 305a2e73f56SAlex Deucher #endif 306a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 307a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 308a2e73f56SAlex Deucher 309a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 310a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 311a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 312a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 313a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 314a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 315a2e73f56SAlex Deucher 316a2e73f56SAlex Deucher /* take all subblocks out of reset, except VCPU */ 317a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 318a2e73f56SAlex Deucher mdelay(5); 319a2e73f56SAlex Deucher 320a2e73f56SAlex Deucher /* enable VCPU clock */ 321a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 322a2e73f56SAlex Deucher 323a2e73f56SAlex Deucher /* enable UMC */ 324a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 325a2e73f56SAlex Deucher 326a2e73f56SAlex Deucher /* boot up the VCPU */ 327a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 328a2e73f56SAlex Deucher mdelay(10); 329a2e73f56SAlex Deucher 330a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 331a2e73f56SAlex Deucher uint32_t status; 332a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 333a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 334a2e73f56SAlex Deucher if (status & 2) 335a2e73f56SAlex Deucher break; 336a2e73f56SAlex Deucher mdelay(10); 337a2e73f56SAlex Deucher } 338a2e73f56SAlex Deucher r = 0; 339a2e73f56SAlex Deucher if (status & 2) 340a2e73f56SAlex Deucher break; 341a2e73f56SAlex Deucher 342a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 343a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 344a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 345a2e73f56SAlex Deucher mdelay(10); 346a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 347a2e73f56SAlex Deucher mdelay(10); 348a2e73f56SAlex Deucher r = -1; 349a2e73f56SAlex Deucher } 350a2e73f56SAlex Deucher 351a2e73f56SAlex Deucher if (r) { 352a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 353a2e73f56SAlex Deucher return r; 354a2e73f56SAlex Deucher } 355a2e73f56SAlex Deucher 356a2e73f56SAlex Deucher /* enable interupt */ 357a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 358a2e73f56SAlex Deucher 359a2e73f56SAlex Deucher /* force RBC into idle state */ 360a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 361a2e73f56SAlex Deucher 362a2e73f56SAlex Deucher /* Set the write pointer delay */ 363a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 364a2e73f56SAlex Deucher 365a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 366a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 367a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 368a2e73f56SAlex Deucher 369a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 370a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 371a2e73f56SAlex Deucher 372a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 373a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 374a2e73f56SAlex Deucher 375a2e73f56SAlex Deucher /* set the ring address */ 376a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 377a2e73f56SAlex Deucher 378a2e73f56SAlex Deucher /* Set ring buffer size */ 379a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 380a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 381a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 382a2e73f56SAlex Deucher 383a2e73f56SAlex Deucher return 0; 384a2e73f56SAlex Deucher } 385a2e73f56SAlex Deucher 386a2e73f56SAlex Deucher /** 387a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 388a2e73f56SAlex Deucher * 389a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 390a2e73f56SAlex Deucher * 391a2e73f56SAlex Deucher * stop the UVD block 392a2e73f56SAlex Deucher */ 393a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 394a2e73f56SAlex Deucher { 395a2e73f56SAlex Deucher /* force RBC into idle state */ 396a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 397a2e73f56SAlex Deucher 398a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 399a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 400a2e73f56SAlex Deucher mdelay(1); 401a2e73f56SAlex Deucher 402a2e73f56SAlex Deucher /* put VCPU into reset */ 403a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 404a2e73f56SAlex Deucher mdelay(5); 405a2e73f56SAlex Deucher 406a2e73f56SAlex Deucher /* disable VCPU clock */ 407a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 408a2e73f56SAlex Deucher 409a2e73f56SAlex Deucher /* Unstall UMC and register bus */ 410a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 411a2e73f56SAlex Deucher } 412a2e73f56SAlex Deucher 413a2e73f56SAlex Deucher /** 414a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 415a2e73f56SAlex Deucher * 416a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 417a2e73f56SAlex Deucher * @fence: fence to emit 418a2e73f56SAlex Deucher * 419a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 420a2e73f56SAlex Deucher */ 421a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 422890ee23fSChunming Zhou unsigned flags) 423a2e73f56SAlex Deucher { 424890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 425a2e73f56SAlex Deucher 426a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 427a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 428a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 429a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 430a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 431a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 432a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 433a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 434a2e73f56SAlex Deucher 435a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 436a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 437a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 438a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 439a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 440a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 441a2e73f56SAlex Deucher } 442a2e73f56SAlex Deucher 443a2e73f56SAlex Deucher /** 444d5b4e25dSChristian König * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush 445d5b4e25dSChristian König * 446d5b4e25dSChristian König * @ring: amdgpu_ring pointer 447d5b4e25dSChristian König * 448d5b4e25dSChristian König * Emits an hdp flush. 449d5b4e25dSChristian König */ 450d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 451d5b4e25dSChristian König { 452d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 453d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 454d5b4e25dSChristian König } 455d5b4e25dSChristian König 456d5b4e25dSChristian König /** 457d5b4e25dSChristian König * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate 458d5b4e25dSChristian König * 459d5b4e25dSChristian König * @ring: amdgpu_ring pointer 460d5b4e25dSChristian König * 461d5b4e25dSChristian König * Emits an hdp invalidate. 462d5b4e25dSChristian König */ 463d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 464d5b4e25dSChristian König { 465d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 466d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 467d5b4e25dSChristian König } 468d5b4e25dSChristian König 469d5b4e25dSChristian König /** 470a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 471a2e73f56SAlex Deucher * 472a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 473a2e73f56SAlex Deucher * 474a2e73f56SAlex Deucher * Test if we can successfully write to the context register 475a2e73f56SAlex Deucher */ 476a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 477a2e73f56SAlex Deucher { 478a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 479a2e73f56SAlex Deucher uint32_t tmp = 0; 480a2e73f56SAlex Deucher unsigned i; 481a2e73f56SAlex Deucher int r; 482a2e73f56SAlex Deucher 483a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 484a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 485a2e73f56SAlex Deucher if (r) { 486a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 487a2e73f56SAlex Deucher ring->idx, r); 488a2e73f56SAlex Deucher return r; 489a2e73f56SAlex Deucher } 490a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 491a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 492a27de35cSChristian König amdgpu_ring_commit(ring); 493a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 494a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 495a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 496a2e73f56SAlex Deucher break; 497a2e73f56SAlex Deucher DRM_UDELAY(1); 498a2e73f56SAlex Deucher } 499a2e73f56SAlex Deucher 500a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 501a2e73f56SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 502a2e73f56SAlex Deucher ring->idx, i); 503a2e73f56SAlex Deucher } else { 504a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 505a2e73f56SAlex Deucher ring->idx, tmp); 506a2e73f56SAlex Deucher r = -EINVAL; 507a2e73f56SAlex Deucher } 508a2e73f56SAlex Deucher return r; 509a2e73f56SAlex Deucher } 510a2e73f56SAlex Deucher 511a2e73f56SAlex Deucher /** 512a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 513a2e73f56SAlex Deucher * 514a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 515a2e73f56SAlex Deucher * @ib: indirect buffer to execute 516a2e73f56SAlex Deucher * 517a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 518a2e73f56SAlex Deucher */ 519a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 520d88bf583SChristian König struct amdgpu_ib *ib, 521d88bf583SChristian König unsigned vm_id, bool ctx_switch) 522a2e73f56SAlex Deucher { 523a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 524a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 525a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 526a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 527a2e73f56SAlex Deucher } 528a2e73f56SAlex Deucher 529a2e73f56SAlex Deucher /** 530a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ib - test ib execution 531a2e73f56SAlex Deucher * 532a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 533a2e73f56SAlex Deucher * 534a2e73f56SAlex Deucher * Test if we can successfully execute an IB 535a2e73f56SAlex Deucher */ 536a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring) 537a2e73f56SAlex Deucher { 538a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 5390e3f154aSChunming Zhou struct fence *fence = NULL; 540a2e73f56SAlex Deucher int r; 541a2e73f56SAlex Deucher 542a2e73f56SAlex Deucher r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 543a2e73f56SAlex Deucher if (r) { 544a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 545a2e73f56SAlex Deucher return r; 546a2e73f56SAlex Deucher } 547a2e73f56SAlex Deucher 548a2e73f56SAlex Deucher r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 549a2e73f56SAlex Deucher if (r) { 550a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 551a2e73f56SAlex Deucher goto error; 552a2e73f56SAlex Deucher } 553a2e73f56SAlex Deucher 554d7af97dbSChristian König r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 555a2e73f56SAlex Deucher if (r) { 556a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 557a2e73f56SAlex Deucher goto error; 558a2e73f56SAlex Deucher } 559a2e73f56SAlex Deucher 5600e3f154aSChunming Zhou r = fence_wait(fence, false); 561a2e73f56SAlex Deucher if (r) { 562a2e73f56SAlex Deucher DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 563a2e73f56SAlex Deucher goto error; 564a2e73f56SAlex Deucher } 565a2e73f56SAlex Deucher DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 566a2e73f56SAlex Deucher error: 5670e3f154aSChunming Zhou fence_put(fence); 568a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 569a2e73f56SAlex Deucher return r; 570a2e73f56SAlex Deucher } 571a2e73f56SAlex Deucher 572a2e73f56SAlex Deucher /** 573a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 574a2e73f56SAlex Deucher * 575a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 576a2e73f56SAlex Deucher * 577a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 578a2e73f56SAlex Deucher */ 579a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 580a2e73f56SAlex Deucher { 581a2e73f56SAlex Deucher uint64_t addr; 582a2e73f56SAlex Deucher uint32_t size; 583a2e73f56SAlex Deucher 584a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 585a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 586a2e73f56SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 587a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 588a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 589a2e73f56SAlex Deucher 590a2e73f56SAlex Deucher addr += size; 591c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 592a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 593a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 594a2e73f56SAlex Deucher 595a2e73f56SAlex Deucher addr += size; 596c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 597c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 598a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 599a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 600a2e73f56SAlex Deucher 601a2e73f56SAlex Deucher /* bits 28-31 */ 602a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 603a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 604a2e73f56SAlex Deucher 605a2e73f56SAlex Deucher /* bits 32-39 */ 606a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 607a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 608a2e73f56SAlex Deucher 60976ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 61076ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 61176ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 61276ed6cb0SAlex Deucher 613a2e73f56SAlex Deucher uvd_v4_2_init_cg(adev); 614a2e73f56SAlex Deucher } 615a2e73f56SAlex Deucher 616a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 617a2e73f56SAlex Deucher bool enable) 618a2e73f56SAlex Deucher { 619a2e73f56SAlex Deucher u32 orig, data; 620a2e73f56SAlex Deucher 621e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 622a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 623a2e73f56SAlex Deucher data = 0xfff; 624a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 625a2e73f56SAlex Deucher 626a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 627a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 628a2e73f56SAlex Deucher if (orig != data) 629a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 630a2e73f56SAlex Deucher } else { 631a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 632a2e73f56SAlex Deucher data &= ~0xfff; 633a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 634a2e73f56SAlex Deucher 635a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 636a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 637a2e73f56SAlex Deucher if (orig != data) 638a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 639a2e73f56SAlex Deucher } 640a2e73f56SAlex Deucher } 641a2e73f56SAlex Deucher 642a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 643a2e73f56SAlex Deucher bool sw_mode) 644a2e73f56SAlex Deucher { 645a2e73f56SAlex Deucher u32 tmp, tmp2; 646a2e73f56SAlex Deucher 647a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 648a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 649a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 650a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 651a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 652a2e73f56SAlex Deucher 653a2e73f56SAlex Deucher if (sw_mode) { 654a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 655a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 656a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 657a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 658a2e73f56SAlex Deucher } else { 659a2e73f56SAlex Deucher tmp |= 0x7ffff800; 660a2e73f56SAlex Deucher tmp2 = 0; 661a2e73f56SAlex Deucher } 662a2e73f56SAlex Deucher 663a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 664a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 665a2e73f56SAlex Deucher } 666a2e73f56SAlex Deucher 667a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 668a2e73f56SAlex Deucher { 669a2e73f56SAlex Deucher bool hw_mode = true; 670a2e73f56SAlex Deucher 671a2e73f56SAlex Deucher if (hw_mode) { 672a2e73f56SAlex Deucher uvd_v4_2_set_dcm(adev, false); 673a2e73f56SAlex Deucher } else { 674a2e73f56SAlex Deucher u32 tmp = RREG32(mmUVD_CGC_CTRL); 675a2e73f56SAlex Deucher tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 676a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 677a2e73f56SAlex Deucher } 678a2e73f56SAlex Deucher } 679a2e73f56SAlex Deucher 6805fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 681a2e73f56SAlex Deucher { 6825fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6835fc3aeebSyanyang1 684a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 685a2e73f56SAlex Deucher } 686a2e73f56SAlex Deucher 6875fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 688a2e73f56SAlex Deucher { 689a2e73f56SAlex Deucher unsigned i; 6905fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 691a2e73f56SAlex Deucher 692a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 693a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 694a2e73f56SAlex Deucher return 0; 695a2e73f56SAlex Deucher } 696a2e73f56SAlex Deucher return -ETIMEDOUT; 697a2e73f56SAlex Deucher } 698a2e73f56SAlex Deucher 6995fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 700a2e73f56SAlex Deucher { 7015fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7025fc3aeebSyanyang1 703a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 704a2e73f56SAlex Deucher 705a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 706a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 707a2e73f56SAlex Deucher mdelay(5); 708a2e73f56SAlex Deucher 709a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 710a2e73f56SAlex Deucher } 711a2e73f56SAlex Deucher 712a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 713a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 714a2e73f56SAlex Deucher unsigned type, 715a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 716a2e73f56SAlex Deucher { 717a2e73f56SAlex Deucher // TODO 718a2e73f56SAlex Deucher return 0; 719a2e73f56SAlex Deucher } 720a2e73f56SAlex Deucher 721a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 722a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 723a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 724a2e73f56SAlex Deucher { 725a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 726a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 727a2e73f56SAlex Deucher return 0; 728a2e73f56SAlex Deucher } 729a2e73f56SAlex Deucher 7305fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 7315fc3aeebSyanyang1 enum amd_clockgating_state state) 732a2e73f56SAlex Deucher { 733a2e73f56SAlex Deucher bool gate = false; 7345fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 735a2e73f56SAlex Deucher 736e3b04bc7SAlex Deucher if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 73735e5912dSAlex Deucher return 0; 73835e5912dSAlex Deucher 7395fc3aeebSyanyang1 if (state == AMD_CG_STATE_GATE) 740a2e73f56SAlex Deucher gate = true; 741a2e73f56SAlex Deucher 742a2e73f56SAlex Deucher uvd_v4_2_enable_mgcg(adev, gate); 743a2e73f56SAlex Deucher 744a2e73f56SAlex Deucher return 0; 745a2e73f56SAlex Deucher } 746a2e73f56SAlex Deucher 7475fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 7485fc3aeebSyanyang1 enum amd_powergating_state state) 749a2e73f56SAlex Deucher { 750a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 751a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 752a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 753a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 754a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 755a2e73f56SAlex Deucher * the smc and the hw blocks 756a2e73f56SAlex Deucher */ 7575fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7585fc3aeebSyanyang1 759e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 760b6df77fcSAlex Deucher return 0; 7615fc3aeebSyanyang1 7625fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 763a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 764a2e73f56SAlex Deucher return 0; 765a2e73f56SAlex Deucher } else { 766a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 767a2e73f56SAlex Deucher } 768a2e73f56SAlex Deucher } 769a2e73f56SAlex Deucher 7705fc3aeebSyanyang1 const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 77188a907d6STom St Denis .name = "uvd_v4_2", 772a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 773a2e73f56SAlex Deucher .late_init = NULL, 774a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 775a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 776a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 777a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 778a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 779a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 780a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 781a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 782a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 783a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 784a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 785a2e73f56SAlex Deucher }; 786a2e73f56SAlex Deucher 787a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 788a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 789a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 790a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 791a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 792a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 793a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 794d5b4e25dSChristian König .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, 795d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, 796a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 797a2e73f56SAlex Deucher .test_ib = uvd_v4_2_ring_test_ib, 798edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 7999e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 800c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 801c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 802a2e73f56SAlex Deucher }; 803a2e73f56SAlex Deucher 804a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 805a2e73f56SAlex Deucher { 806a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 807a2e73f56SAlex Deucher } 808a2e73f56SAlex Deucher 809a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 810a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 811a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 812a2e73f56SAlex Deucher }; 813a2e73f56SAlex Deucher 814a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 815a2e73f56SAlex Deucher { 816a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 817a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 818a2e73f56SAlex Deucher } 819