1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37d5b4e25dSChristian König #include "bif/bif_4_1_d.h" 38d5b4e25dSChristian König 394be5097cSRex Zhu #include "smu/smu_7_0_1_d.h" 404be5097cSRex Zhu #include "smu/smu_7_0_1_sh_mask.h" 414be5097cSRex Zhu 42a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 44a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 46a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 47aa4747c0SRex Zhu static int uvd_v4_2_set_clockgating_state(void *handle, 48aa4747c0SRex Zhu enum amd_clockgating_state state); 49ca581e45SRex Zhu static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 50ca581e45SRex Zhu bool sw_mode); 51a2e73f56SAlex Deucher /** 52a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 53a2e73f56SAlex Deucher * 54a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 55a2e73f56SAlex Deucher * 56a2e73f56SAlex Deucher * Returns the current hardware read pointer 57a2e73f56SAlex Deucher */ 58536fbf94SKen Wang static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 59a2e73f56SAlex Deucher { 60a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 61a2e73f56SAlex Deucher 62a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 63a2e73f56SAlex Deucher } 64a2e73f56SAlex Deucher 65a2e73f56SAlex Deucher /** 66a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 67a2e73f56SAlex Deucher * 68a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 69a2e73f56SAlex Deucher * 70a2e73f56SAlex Deucher * Returns the current hardware write pointer 71a2e73f56SAlex Deucher */ 72536fbf94SKen Wang static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 73a2e73f56SAlex Deucher { 74a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 75a2e73f56SAlex Deucher 76a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 77a2e73f56SAlex Deucher } 78a2e73f56SAlex Deucher 79a2e73f56SAlex Deucher /** 80a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 81a2e73f56SAlex Deucher * 82a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 83a2e73f56SAlex Deucher * 84a2e73f56SAlex Deucher * Commits the write pointer to the hardware 85a2e73f56SAlex Deucher */ 86a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 87a2e73f56SAlex Deucher { 88a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 89a2e73f56SAlex Deucher 90536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 91a2e73f56SAlex Deucher } 92a2e73f56SAlex Deucher 935fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 94a2e73f56SAlex Deucher { 955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 965fc3aeebSyanyang1 97a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 98a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 99a2e73f56SAlex Deucher 100a2e73f56SAlex Deucher return 0; 101a2e73f56SAlex Deucher } 102a2e73f56SAlex Deucher 1035fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 104a2e73f56SAlex Deucher { 105a2e73f56SAlex Deucher struct amdgpu_ring *ring; 1065fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 107a2e73f56SAlex Deucher int r; 108a2e73f56SAlex Deucher 109a2e73f56SAlex Deucher /* UVD TRAP */ 110d766e6a3SAlex Deucher r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq); 111a2e73f56SAlex Deucher if (r) 112a2e73f56SAlex Deucher return r; 113a2e73f56SAlex Deucher 114a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 115a2e73f56SAlex Deucher if (r) 116a2e73f56SAlex Deucher return r; 117a2e73f56SAlex Deucher 118a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 119a2e73f56SAlex Deucher if (r) 120a2e73f56SAlex Deucher return r; 121a2e73f56SAlex Deucher 122a2e73f56SAlex Deucher ring = &adev->uvd.ring; 123a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 12479887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 125a2e73f56SAlex Deucher 126a2e73f56SAlex Deucher return r; 127a2e73f56SAlex Deucher } 128a2e73f56SAlex Deucher 1295fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 130a2e73f56SAlex Deucher { 131a2e73f56SAlex Deucher int r; 1325fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 133a2e73f56SAlex Deucher 134a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 135a2e73f56SAlex Deucher if (r) 136a2e73f56SAlex Deucher return r; 137a2e73f56SAlex Deucher 13850237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 139a2e73f56SAlex Deucher } 14050237287SRex Zhu 141ca581e45SRex Zhu static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 142ca581e45SRex Zhu bool enable); 143a2e73f56SAlex Deucher /** 144a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 145a2e73f56SAlex Deucher * 146a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 147a2e73f56SAlex Deucher * 148a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 149a2e73f56SAlex Deucher */ 1505fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 151a2e73f56SAlex Deucher { 1525fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 154a2e73f56SAlex Deucher uint32_t tmp; 155a2e73f56SAlex Deucher int r; 156a2e73f56SAlex Deucher 157ca581e45SRex Zhu uvd_v4_2_enable_mgcg(adev, true); 158aa4747c0SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 159a2e73f56SAlex Deucher 160a2e73f56SAlex Deucher ring->ready = true; 161a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 162a2e73f56SAlex Deucher if (r) { 163a2e73f56SAlex Deucher ring->ready = false; 164a2e73f56SAlex Deucher goto done; 165a2e73f56SAlex Deucher } 166a2e73f56SAlex Deucher 167a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 168a2e73f56SAlex Deucher if (r) { 169a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170a2e73f56SAlex Deucher goto done; 171a2e73f56SAlex Deucher } 172a2e73f56SAlex Deucher 173a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 175a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176a2e73f56SAlex Deucher 177a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 179a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180a2e73f56SAlex Deucher 181a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 183a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184a2e73f56SAlex Deucher 185a2e73f56SAlex Deucher /* Clear timeout status bits */ 186a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 188a2e73f56SAlex Deucher 189a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 191a2e73f56SAlex Deucher 192a27de35cSChristian König amdgpu_ring_commit(ring); 193a2e73f56SAlex Deucher 194a2e73f56SAlex Deucher done: 195a2e73f56SAlex Deucher if (!r) 196a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 197a2e73f56SAlex Deucher 198a2e73f56SAlex Deucher return r; 199a2e73f56SAlex Deucher } 200a2e73f56SAlex Deucher 201a2e73f56SAlex Deucher /** 202a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 203a2e73f56SAlex Deucher * 204a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 205a2e73f56SAlex Deucher * 206a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 207a2e73f56SAlex Deucher */ 2085fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 209a2e73f56SAlex Deucher { 2105fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 211a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 212a2e73f56SAlex Deucher 2138b55d17eSRex Zhu if (RREG32(mmUVD_STATUS) != 0) 214a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 2158b55d17eSRex Zhu 216a2e73f56SAlex Deucher ring->ready = false; 217a2e73f56SAlex Deucher 218a2e73f56SAlex Deucher return 0; 219a2e73f56SAlex Deucher } 220a2e73f56SAlex Deucher 2215fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 222a2e73f56SAlex Deucher { 223a2e73f56SAlex Deucher int r; 2245fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225a2e73f56SAlex Deucher 2263f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 227a2e73f56SAlex Deucher if (r) 228a2e73f56SAlex Deucher return r; 229a2e73f56SAlex Deucher 23050237287SRex Zhu return amdgpu_uvd_suspend(adev); 231a2e73f56SAlex Deucher } 232a2e73f56SAlex Deucher 2335fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 234a2e73f56SAlex Deucher { 235a2e73f56SAlex Deucher int r; 2365fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 237a2e73f56SAlex Deucher 238a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 239a2e73f56SAlex Deucher if (r) 240a2e73f56SAlex Deucher return r; 241a2e73f56SAlex Deucher 24250237287SRex Zhu return uvd_v4_2_hw_init(adev); 243a2e73f56SAlex Deucher } 244a2e73f56SAlex Deucher 245a2e73f56SAlex Deucher /** 246a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 247a2e73f56SAlex Deucher * 248a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 249a2e73f56SAlex Deucher * 250a2e73f56SAlex Deucher * Setup and start the UVD block 251a2e73f56SAlex Deucher */ 252a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 253a2e73f56SAlex Deucher { 254a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 255a2e73f56SAlex Deucher uint32_t rb_bufsz; 256a2e73f56SAlex Deucher int i, j, r; 2578b55d17eSRex Zhu u32 tmp; 258a2e73f56SAlex Deucher /* disable byte swapping */ 259a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 260a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 261a2e73f56SAlex Deucher 2628b55d17eSRex Zhu /* set uvd busy */ 2638b55d17eSRex Zhu WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); 2648b55d17eSRex Zhu 265ca581e45SRex Zhu uvd_v4_2_set_dcm(adev, true); 2668b55d17eSRex Zhu WREG32(mmUVD_CGC_GATE, 0); 267a2e73f56SAlex Deucher 268a2e73f56SAlex Deucher /* take UVD block out of reset */ 269a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 270a2e73f56SAlex Deucher mdelay(5); 271a2e73f56SAlex Deucher 2728b55d17eSRex Zhu /* enable VCPU clock */ 2738b55d17eSRex Zhu WREG32(mmUVD_VCPU_CNTL, 1 << 9); 2748b55d17eSRex Zhu 2758b55d17eSRex Zhu /* disable interupt */ 2768b55d17eSRex Zhu WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 277a2e73f56SAlex Deucher 278a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 279a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 280a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 281a2e73f56SAlex Deucher mp_swap_cntl = 0; 282a2e73f56SAlex Deucher #endif 283a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 284a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 2858b55d17eSRex Zhu /* initialize UVD memory controller */ 2868b55d17eSRex Zhu WREG32(mmUVD_LMI_CTRL, 0x203108); 2878b55d17eSRex Zhu 2888b55d17eSRex Zhu tmp = RREG32(mmUVD_MPC_CNTL); 2898b55d17eSRex Zhu WREG32(mmUVD_MPC_CNTL, tmp | 0x10); 290a2e73f56SAlex Deucher 291a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 292a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 293a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 294a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 295a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 296a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 297a2e73f56SAlex Deucher 2988b55d17eSRex Zhu uvd_v4_2_mc_resume(adev); 299a2e73f56SAlex Deucher 3008b55d17eSRex Zhu tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); 3018b55d17eSRex Zhu WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); 302a2e73f56SAlex Deucher 303a2e73f56SAlex Deucher /* enable UMC */ 304a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 305a2e73f56SAlex Deucher 3068b55d17eSRex Zhu WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 3078b55d17eSRex Zhu 3088b55d17eSRex Zhu WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 3098b55d17eSRex Zhu 3108b55d17eSRex Zhu WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 3118b55d17eSRex Zhu 312a2e73f56SAlex Deucher mdelay(10); 313a2e73f56SAlex Deucher 314a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 315a2e73f56SAlex Deucher uint32_t status; 316a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 317a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 318a2e73f56SAlex Deucher if (status & 2) 319a2e73f56SAlex Deucher break; 320a2e73f56SAlex Deucher mdelay(10); 321a2e73f56SAlex Deucher } 322a2e73f56SAlex Deucher r = 0; 323a2e73f56SAlex Deucher if (status & 2) 324a2e73f56SAlex Deucher break; 325a2e73f56SAlex Deucher 326a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 327a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 328a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 329a2e73f56SAlex Deucher mdelay(10); 330a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 331a2e73f56SAlex Deucher mdelay(10); 332a2e73f56SAlex Deucher r = -1; 333a2e73f56SAlex Deucher } 334a2e73f56SAlex Deucher 335a2e73f56SAlex Deucher if (r) { 336a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 337a2e73f56SAlex Deucher return r; 338a2e73f56SAlex Deucher } 339a2e73f56SAlex Deucher 340a2e73f56SAlex Deucher /* enable interupt */ 341a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 342a2e73f56SAlex Deucher 3438b55d17eSRex Zhu WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); 3448b55d17eSRex Zhu 345a2e73f56SAlex Deucher /* force RBC into idle state */ 346a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 347a2e73f56SAlex Deucher 348a2e73f56SAlex Deucher /* Set the write pointer delay */ 349a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 350a2e73f56SAlex Deucher 351a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 352a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 353a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 354a2e73f56SAlex Deucher 355a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 356a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 357a2e73f56SAlex Deucher 358a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 359536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 360a2e73f56SAlex Deucher 361a2e73f56SAlex Deucher /* set the ring address */ 362a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 363a2e73f56SAlex Deucher 364a2e73f56SAlex Deucher /* Set ring buffer size */ 365a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 366a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 367a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 368a2e73f56SAlex Deucher 369a2e73f56SAlex Deucher return 0; 370a2e73f56SAlex Deucher } 371a2e73f56SAlex Deucher 372a2e73f56SAlex Deucher /** 373a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 374a2e73f56SAlex Deucher * 375a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 376a2e73f56SAlex Deucher * 377a2e73f56SAlex Deucher * stop the UVD block 378a2e73f56SAlex Deucher */ 379a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 380a2e73f56SAlex Deucher { 3818b55d17eSRex Zhu uint32_t i, j; 3828b55d17eSRex Zhu uint32_t status; 3838b55d17eSRex Zhu 384a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 385a2e73f56SAlex Deucher 3868b55d17eSRex Zhu for (i = 0; i < 10; ++i) { 3878b55d17eSRex Zhu for (j = 0; j < 100; ++j) { 3888b55d17eSRex Zhu status = RREG32(mmUVD_STATUS); 3898b55d17eSRex Zhu if (status & 2) 3908b55d17eSRex Zhu break; 3918b55d17eSRex Zhu mdelay(1); 3928b55d17eSRex Zhu } 393e89d5b5cSTom St Denis if (status & 2) 3948b55d17eSRex Zhu break; 3958b55d17eSRex Zhu } 3968b55d17eSRex Zhu 3978b55d17eSRex Zhu for (i = 0; i < 10; ++i) { 3988b55d17eSRex Zhu for (j = 0; j < 100; ++j) { 3998b55d17eSRex Zhu status = RREG32(mmUVD_LMI_STATUS); 4008b55d17eSRex Zhu if (status & 0xf) 4018b55d17eSRex Zhu break; 4028b55d17eSRex Zhu mdelay(1); 4038b55d17eSRex Zhu } 404e89d5b5cSTom St Denis if (status & 0xf) 4058b55d17eSRex Zhu break; 4068b55d17eSRex Zhu } 4078b55d17eSRex Zhu 408a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 409a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 4108b55d17eSRex Zhu 4118b55d17eSRex Zhu for (i = 0; i < 10; ++i) { 4128b55d17eSRex Zhu for (j = 0; j < 100; ++j) { 4138b55d17eSRex Zhu status = RREG32(mmUVD_LMI_STATUS); 4148b55d17eSRex Zhu if (status & 0x240) 4158b55d17eSRex Zhu break; 416a2e73f56SAlex Deucher mdelay(1); 4178b55d17eSRex Zhu } 418e89d5b5cSTom St Denis if (status & 0x240) 4198b55d17eSRex Zhu break; 4208b55d17eSRex Zhu } 421a2e73f56SAlex Deucher 4228b55d17eSRex Zhu WREG32_P(0x3D49, 0, ~(1 << 2)); 423a2e73f56SAlex Deucher 4248b55d17eSRex Zhu WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); 425a2e73f56SAlex Deucher 4268b55d17eSRex Zhu /* put LMI, VCPU, RBC etc... into reset */ 4278b55d17eSRex Zhu WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 4288b55d17eSRex Zhu UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 4298b55d17eSRex Zhu UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 4308b55d17eSRex Zhu 4318b55d17eSRex Zhu WREG32(mmUVD_STATUS, 0); 432ca581e45SRex Zhu 433ca581e45SRex Zhu uvd_v4_2_set_dcm(adev, false); 434a2e73f56SAlex Deucher } 435a2e73f56SAlex Deucher 436a2e73f56SAlex Deucher /** 437a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 438a2e73f56SAlex Deucher * 439a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 440a2e73f56SAlex Deucher * @fence: fence to emit 441a2e73f56SAlex Deucher * 442a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 443a2e73f56SAlex Deucher */ 444a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 445890ee23fSChunming Zhou unsigned flags) 446a2e73f56SAlex Deucher { 447890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 448a2e73f56SAlex Deucher 449a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 450a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 451a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 452a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 453a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 454a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 455a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 456a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 457a2e73f56SAlex Deucher 458a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 459a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 460a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 461a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 462a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 463a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 464a2e73f56SAlex Deucher } 465a2e73f56SAlex Deucher 466a2e73f56SAlex Deucher /** 467d5b4e25dSChristian König * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush 468d5b4e25dSChristian König * 469d5b4e25dSChristian König * @ring: amdgpu_ring pointer 470d5b4e25dSChristian König * 471d5b4e25dSChristian König * Emits an hdp flush. 472d5b4e25dSChristian König */ 473d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 474d5b4e25dSChristian König { 475d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 476d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 477d5b4e25dSChristian König } 478d5b4e25dSChristian König 479d5b4e25dSChristian König /** 480d5b4e25dSChristian König * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate 481d5b4e25dSChristian König * 482d5b4e25dSChristian König * @ring: amdgpu_ring pointer 483d5b4e25dSChristian König * 484d5b4e25dSChristian König * Emits an hdp invalidate. 485d5b4e25dSChristian König */ 486d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 487d5b4e25dSChristian König { 488d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 489d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 490d5b4e25dSChristian König } 491d5b4e25dSChristian König 492d5b4e25dSChristian König /** 493a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 494a2e73f56SAlex Deucher * 495a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 496a2e73f56SAlex Deucher * 497a2e73f56SAlex Deucher * Test if we can successfully write to the context register 498a2e73f56SAlex Deucher */ 499a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 500a2e73f56SAlex Deucher { 501a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 502a2e73f56SAlex Deucher uint32_t tmp = 0; 503a2e73f56SAlex Deucher unsigned i; 504a2e73f56SAlex Deucher int r; 505a2e73f56SAlex Deucher 506a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 507a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 508a2e73f56SAlex Deucher if (r) { 509a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 510a2e73f56SAlex Deucher ring->idx, r); 511a2e73f56SAlex Deucher return r; 512a2e73f56SAlex Deucher } 513a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 514a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 515a27de35cSChristian König amdgpu_ring_commit(ring); 516a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 517a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 518a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 519a2e73f56SAlex Deucher break; 520a2e73f56SAlex Deucher DRM_UDELAY(1); 521a2e73f56SAlex Deucher } 522a2e73f56SAlex Deucher 523a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 5249953b72fSpding DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 525a2e73f56SAlex Deucher ring->idx, i); 526a2e73f56SAlex Deucher } else { 527a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 528a2e73f56SAlex Deucher ring->idx, tmp); 529a2e73f56SAlex Deucher r = -EINVAL; 530a2e73f56SAlex Deucher } 531a2e73f56SAlex Deucher return r; 532a2e73f56SAlex Deucher } 533a2e73f56SAlex Deucher 534a2e73f56SAlex Deucher /** 535a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 536a2e73f56SAlex Deucher * 537a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 538a2e73f56SAlex Deucher * @ib: indirect buffer to execute 539a2e73f56SAlex Deucher * 540a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 541a2e73f56SAlex Deucher */ 542a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 543d88bf583SChristian König struct amdgpu_ib *ib, 544d88bf583SChristian König unsigned vm_id, bool ctx_switch) 545a2e73f56SAlex Deucher { 546a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 547a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 548a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 549a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 550a2e73f56SAlex Deucher } 551a2e73f56SAlex Deucher 552a2e73f56SAlex Deucher /** 553a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 554a2e73f56SAlex Deucher * 555a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 556a2e73f56SAlex Deucher * 557a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 558a2e73f56SAlex Deucher */ 559a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 560a2e73f56SAlex Deucher { 561a2e73f56SAlex Deucher uint64_t addr; 562a2e73f56SAlex Deucher uint32_t size; 563a2e73f56SAlex Deucher 564a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 565a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 566c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; 567a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 568a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 569a2e73f56SAlex Deucher 570a2e73f56SAlex Deucher addr += size; 571c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 572a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 573a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 574a2e73f56SAlex Deucher 575a2e73f56SAlex Deucher addr += size; 576c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 577c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 578a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 579a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 580a2e73f56SAlex Deucher 581a2e73f56SAlex Deucher /* bits 28-31 */ 582a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 583a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 584a2e73f56SAlex Deucher 585a2e73f56SAlex Deucher /* bits 32-39 */ 586a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 587a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 588a2e73f56SAlex Deucher 58976ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 59076ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 59176ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 592a2e73f56SAlex Deucher } 593a2e73f56SAlex Deucher 594a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 595a2e73f56SAlex Deucher bool enable) 596a2e73f56SAlex Deucher { 597a2e73f56SAlex Deucher u32 orig, data; 598a2e73f56SAlex Deucher 599e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 600a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 601aa4747c0SRex Zhu data |= 0xfff; 602a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 603a2e73f56SAlex Deucher 604a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 605a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 606a2e73f56SAlex Deucher if (orig != data) 607a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 608a2e73f56SAlex Deucher } else { 609a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 610a2e73f56SAlex Deucher data &= ~0xfff; 611a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 612a2e73f56SAlex Deucher 613a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 614a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 615a2e73f56SAlex Deucher if (orig != data) 616a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 617a2e73f56SAlex Deucher } 618a2e73f56SAlex Deucher } 619a2e73f56SAlex Deucher 620a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 621a2e73f56SAlex Deucher bool sw_mode) 622a2e73f56SAlex Deucher { 623a2e73f56SAlex Deucher u32 tmp, tmp2; 624a2e73f56SAlex Deucher 625953618cfSRex Zhu WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 626953618cfSRex Zhu 627a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 628a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 629a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 630a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 631a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 632a2e73f56SAlex Deucher 633a2e73f56SAlex Deucher if (sw_mode) { 634a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 635a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 636a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 637a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 638a2e73f56SAlex Deucher } else { 639a2e73f56SAlex Deucher tmp |= 0x7ffff800; 640a2e73f56SAlex Deucher tmp2 = 0; 641a2e73f56SAlex Deucher } 642a2e73f56SAlex Deucher 643a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 644a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 645a2e73f56SAlex Deucher } 646a2e73f56SAlex Deucher 6475fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 648a2e73f56SAlex Deucher { 6495fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6505fc3aeebSyanyang1 651a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 652a2e73f56SAlex Deucher } 653a2e73f56SAlex Deucher 6545fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 655a2e73f56SAlex Deucher { 656a2e73f56SAlex Deucher unsigned i; 6575fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 658a2e73f56SAlex Deucher 659a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 660a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 661a2e73f56SAlex Deucher return 0; 662a2e73f56SAlex Deucher } 663a2e73f56SAlex Deucher return -ETIMEDOUT; 664a2e73f56SAlex Deucher } 665a2e73f56SAlex Deucher 6665fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 667a2e73f56SAlex Deucher { 6685fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6695fc3aeebSyanyang1 670a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 671a2e73f56SAlex Deucher 672a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 673a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 674a2e73f56SAlex Deucher mdelay(5); 675a2e73f56SAlex Deucher 676a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 677a2e73f56SAlex Deucher } 678a2e73f56SAlex Deucher 679a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 680a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 681a2e73f56SAlex Deucher unsigned type, 682a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 683a2e73f56SAlex Deucher { 684a2e73f56SAlex Deucher // TODO 685a2e73f56SAlex Deucher return 0; 686a2e73f56SAlex Deucher } 687a2e73f56SAlex Deucher 688a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 689a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 690a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 691a2e73f56SAlex Deucher { 692a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 693a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 694a2e73f56SAlex Deucher return 0; 695a2e73f56SAlex Deucher } 696a2e73f56SAlex Deucher 6975fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 6985fc3aeebSyanyang1 enum amd_clockgating_state state) 699a2e73f56SAlex Deucher { 700a2e73f56SAlex Deucher return 0; 701a2e73f56SAlex Deucher } 702a2e73f56SAlex Deucher 7035fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 7045fc3aeebSyanyang1 enum amd_powergating_state state) 705a2e73f56SAlex Deucher { 706a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 707a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 708a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 709a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 710a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 711a2e73f56SAlex Deucher * the smc and the hw blocks 712a2e73f56SAlex Deucher */ 7135fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7145fc3aeebSyanyang1 7155fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 716a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 7173a786966SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) { 718254cd2e0SRex Zhu if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 719254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) { 7203a786966SRex Zhu WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 7213a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 7223a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 7233a786966SRex Zhu mdelay(20); 7243a786966SRex Zhu } 7253a786966SRex Zhu } 726a2e73f56SAlex Deucher return 0; 727a2e73f56SAlex Deucher } else { 7283a786966SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) { 729254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 730254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 7313a786966SRex Zhu WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 7323a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 7333a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 7343a786966SRex Zhu mdelay(30); 7353a786966SRex Zhu } 7363a786966SRex Zhu } 737a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 738a2e73f56SAlex Deucher } 739a2e73f56SAlex Deucher } 740a2e73f56SAlex Deucher 741a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 74288a907d6STom St Denis .name = "uvd_v4_2", 743a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 744a2e73f56SAlex Deucher .late_init = NULL, 745a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 746a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 747a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 748a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 749a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 750a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 751a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 752a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 753a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 754a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 755a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 756a2e73f56SAlex Deucher }; 757a2e73f56SAlex Deucher 758a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 75921cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 76079887142SChristian König .align_mask = 0xf, 76179887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 762536fbf94SKen Wang .support_64bit_ptrs = false, 763a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 764a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 765a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 766a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 767e12f3d7aSChristian König .emit_frame_size = 768e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_flush */ 769e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ 770e12f3d7aSChristian König 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 771e12f3d7aSChristian König .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 772a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 773a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 774d5b4e25dSChristian König .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, 775d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, 776a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 7778de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 778edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 7799e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 780c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 781c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 782a2e73f56SAlex Deucher }; 783a2e73f56SAlex Deucher 784a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 785a2e73f56SAlex Deucher { 786a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 787a2e73f56SAlex Deucher } 788a2e73f56SAlex Deucher 789a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 790a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 791a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 792a2e73f56SAlex Deucher }; 793a2e73f56SAlex Deucher 794a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 795a2e73f56SAlex Deucher { 796a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 797a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 798a2e73f56SAlex Deucher } 799a1255107SAlex Deucher 800a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 801a1255107SAlex Deucher { 802a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 803a1255107SAlex Deucher .major = 4, 804a1255107SAlex Deucher .minor = 2, 805a1255107SAlex Deucher .rev = 0, 806a1255107SAlex Deucher .funcs = &uvd_v4_2_ip_funcs, 807a1255107SAlex Deucher }; 808