1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 38a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 39a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 40a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 41a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 42a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher 44a2e73f56SAlex Deucher /** 45a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 46a2e73f56SAlex Deucher * 47a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 48a2e73f56SAlex Deucher * 49a2e73f56SAlex Deucher * Returns the current hardware read pointer 50a2e73f56SAlex Deucher */ 51a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 52a2e73f56SAlex Deucher { 53a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 54a2e73f56SAlex Deucher 55a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 56a2e73f56SAlex Deucher } 57a2e73f56SAlex Deucher 58a2e73f56SAlex Deucher /** 59a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 60a2e73f56SAlex Deucher * 61a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 62a2e73f56SAlex Deucher * 63a2e73f56SAlex Deucher * Returns the current hardware write pointer 64a2e73f56SAlex Deucher */ 65a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 66a2e73f56SAlex Deucher { 67a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 68a2e73f56SAlex Deucher 69a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 70a2e73f56SAlex Deucher } 71a2e73f56SAlex Deucher 72a2e73f56SAlex Deucher /** 73a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 74a2e73f56SAlex Deucher * 75a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 76a2e73f56SAlex Deucher * 77a2e73f56SAlex Deucher * Commits the write pointer to the hardware 78a2e73f56SAlex Deucher */ 79a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 80a2e73f56SAlex Deucher { 81a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 82a2e73f56SAlex Deucher 83a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 84a2e73f56SAlex Deucher } 85a2e73f56SAlex Deucher 865fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 87a2e73f56SAlex Deucher { 885fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895fc3aeebSyanyang1 90a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 91a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 92a2e73f56SAlex Deucher 93a2e73f56SAlex Deucher return 0; 94a2e73f56SAlex Deucher } 95a2e73f56SAlex Deucher 965fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 97a2e73f56SAlex Deucher { 98a2e73f56SAlex Deucher struct amdgpu_ring *ring; 995fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 100a2e73f56SAlex Deucher int r; 101a2e73f56SAlex Deucher 102a2e73f56SAlex Deucher /* UVD TRAP */ 103a2e73f56SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 104a2e73f56SAlex Deucher if (r) 105a2e73f56SAlex Deucher return r; 106a2e73f56SAlex Deucher 107a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 108a2e73f56SAlex Deucher if (r) 109a2e73f56SAlex Deucher return r; 110a2e73f56SAlex Deucher 111a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 112a2e73f56SAlex Deucher if (r) 113a2e73f56SAlex Deucher return r; 114a2e73f56SAlex Deucher 115a2e73f56SAlex Deucher ring = &adev->uvd.ring; 116a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 117a2e73f56SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 118a2e73f56SAlex Deucher &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 119a2e73f56SAlex Deucher 120a2e73f56SAlex Deucher return r; 121a2e73f56SAlex Deucher } 122a2e73f56SAlex Deucher 1235fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 124a2e73f56SAlex Deucher { 125a2e73f56SAlex Deucher int r; 1265fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 127a2e73f56SAlex Deucher 128a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 129a2e73f56SAlex Deucher if (r) 130a2e73f56SAlex Deucher return r; 131a2e73f56SAlex Deucher 132a2e73f56SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 133a2e73f56SAlex Deucher if (r) 134a2e73f56SAlex Deucher return r; 135a2e73f56SAlex Deucher 136a2e73f56SAlex Deucher return r; 137a2e73f56SAlex Deucher } 138a2e73f56SAlex Deucher 139a2e73f56SAlex Deucher /** 140a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 141a2e73f56SAlex Deucher * 142a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 143a2e73f56SAlex Deucher * 144a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 145a2e73f56SAlex Deucher */ 1465fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 147a2e73f56SAlex Deucher { 1485fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 149a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 150a2e73f56SAlex Deucher uint32_t tmp; 151a2e73f56SAlex Deucher int r; 152a2e73f56SAlex Deucher 153a2e73f56SAlex Deucher /* raise clocks while booting up the VCPU */ 154a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 155a2e73f56SAlex Deucher 156a2e73f56SAlex Deucher r = uvd_v4_2_start(adev); 157a2e73f56SAlex Deucher if (r) 158a2e73f56SAlex Deucher goto done; 159a2e73f56SAlex Deucher 160a2e73f56SAlex Deucher ring->ready = true; 161a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 162a2e73f56SAlex Deucher if (r) { 163a2e73f56SAlex Deucher ring->ready = false; 164a2e73f56SAlex Deucher goto done; 165a2e73f56SAlex Deucher } 166a2e73f56SAlex Deucher 167a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 168a2e73f56SAlex Deucher if (r) { 169a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 170a2e73f56SAlex Deucher goto done; 171a2e73f56SAlex Deucher } 172a2e73f56SAlex Deucher 173a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 174a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 175a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 176a2e73f56SAlex Deucher 177a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 178a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 179a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180a2e73f56SAlex Deucher 181a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 182a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 183a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184a2e73f56SAlex Deucher 185a2e73f56SAlex Deucher /* Clear timeout status bits */ 186a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 187a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 188a2e73f56SAlex Deucher 189a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 190a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 191a2e73f56SAlex Deucher 192a27de35cSChristian König amdgpu_ring_commit(ring); 193a2e73f56SAlex Deucher 194a2e73f56SAlex Deucher done: 195a2e73f56SAlex Deucher /* lower clocks again */ 196a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 197a2e73f56SAlex Deucher 198a2e73f56SAlex Deucher if (!r) 199a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 200a2e73f56SAlex Deucher 201a2e73f56SAlex Deucher return r; 202a2e73f56SAlex Deucher } 203a2e73f56SAlex Deucher 204a2e73f56SAlex Deucher /** 205a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 206a2e73f56SAlex Deucher * 207a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 208a2e73f56SAlex Deucher * 209a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 210a2e73f56SAlex Deucher */ 2115fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 212a2e73f56SAlex Deucher { 2135fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 214a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 215a2e73f56SAlex Deucher 216a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 217a2e73f56SAlex Deucher ring->ready = false; 218a2e73f56SAlex Deucher 219a2e73f56SAlex Deucher return 0; 220a2e73f56SAlex Deucher } 221a2e73f56SAlex Deucher 2225fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 223a2e73f56SAlex Deucher { 224a2e73f56SAlex Deucher int r; 2255fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226a2e73f56SAlex Deucher 2273f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 228a2e73f56SAlex Deucher if (r) 229a2e73f56SAlex Deucher return r; 230a2e73f56SAlex Deucher 2313f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 232a2e73f56SAlex Deucher if (r) 233a2e73f56SAlex Deucher return r; 234a2e73f56SAlex Deucher 235a2e73f56SAlex Deucher return r; 236a2e73f56SAlex Deucher } 237a2e73f56SAlex Deucher 2385fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 239a2e73f56SAlex Deucher { 240a2e73f56SAlex Deucher int r; 2415fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 242a2e73f56SAlex Deucher 243a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 244a2e73f56SAlex Deucher if (r) 245a2e73f56SAlex Deucher return r; 246a2e73f56SAlex Deucher 247a2e73f56SAlex Deucher r = uvd_v4_2_hw_init(adev); 248a2e73f56SAlex Deucher if (r) 249a2e73f56SAlex Deucher return r; 250a2e73f56SAlex Deucher 251a2e73f56SAlex Deucher return r; 252a2e73f56SAlex Deucher } 253a2e73f56SAlex Deucher 254a2e73f56SAlex Deucher /** 255a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 256a2e73f56SAlex Deucher * 257a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 258a2e73f56SAlex Deucher * 259a2e73f56SAlex Deucher * Setup and start the UVD block 260a2e73f56SAlex Deucher */ 261a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 262a2e73f56SAlex Deucher { 263a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 264a2e73f56SAlex Deucher uint32_t rb_bufsz; 265a2e73f56SAlex Deucher int i, j, r; 266a2e73f56SAlex Deucher 267a2e73f56SAlex Deucher /* disable byte swapping */ 268a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 269a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 270a2e73f56SAlex Deucher 271a2e73f56SAlex Deucher uvd_v4_2_mc_resume(adev); 272a2e73f56SAlex Deucher 273a2e73f56SAlex Deucher /* disable clock gating */ 274a2e73f56SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 275a2e73f56SAlex Deucher 276a2e73f56SAlex Deucher /* disable interupt */ 277a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 278a2e73f56SAlex Deucher 279a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 280a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 281a2e73f56SAlex Deucher mdelay(1); 282a2e73f56SAlex Deucher 283a2e73f56SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 284a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 285a2e73f56SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 286a2e73f56SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 287a2e73f56SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 288a2e73f56SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 289a2e73f56SAlex Deucher mdelay(5); 290a2e73f56SAlex Deucher 291a2e73f56SAlex Deucher /* take UVD block out of reset */ 292a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 293a2e73f56SAlex Deucher mdelay(5); 294a2e73f56SAlex Deucher 295a2e73f56SAlex Deucher /* initialize UVD memory controller */ 296a2e73f56SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 297a2e73f56SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 298a2e73f56SAlex Deucher 299a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 300a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 301a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 302a2e73f56SAlex Deucher mp_swap_cntl = 0; 303a2e73f56SAlex Deucher #endif 304a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 305a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 306a2e73f56SAlex Deucher 307a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 308a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 309a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 310a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 311a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 312a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 313a2e73f56SAlex Deucher 314a2e73f56SAlex Deucher /* take all subblocks out of reset, except VCPU */ 315a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 316a2e73f56SAlex Deucher mdelay(5); 317a2e73f56SAlex Deucher 318a2e73f56SAlex Deucher /* enable VCPU clock */ 319a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 320a2e73f56SAlex Deucher 321a2e73f56SAlex Deucher /* enable UMC */ 322a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 323a2e73f56SAlex Deucher 324a2e73f56SAlex Deucher /* boot up the VCPU */ 325a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 326a2e73f56SAlex Deucher mdelay(10); 327a2e73f56SAlex Deucher 328a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 329a2e73f56SAlex Deucher uint32_t status; 330a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 331a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 332a2e73f56SAlex Deucher if (status & 2) 333a2e73f56SAlex Deucher break; 334a2e73f56SAlex Deucher mdelay(10); 335a2e73f56SAlex Deucher } 336a2e73f56SAlex Deucher r = 0; 337a2e73f56SAlex Deucher if (status & 2) 338a2e73f56SAlex Deucher break; 339a2e73f56SAlex Deucher 340a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 341a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 342a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 343a2e73f56SAlex Deucher mdelay(10); 344a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 345a2e73f56SAlex Deucher mdelay(10); 346a2e73f56SAlex Deucher r = -1; 347a2e73f56SAlex Deucher } 348a2e73f56SAlex Deucher 349a2e73f56SAlex Deucher if (r) { 350a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 351a2e73f56SAlex Deucher return r; 352a2e73f56SAlex Deucher } 353a2e73f56SAlex Deucher 354a2e73f56SAlex Deucher /* enable interupt */ 355a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 356a2e73f56SAlex Deucher 357a2e73f56SAlex Deucher /* force RBC into idle state */ 358a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 359a2e73f56SAlex Deucher 360a2e73f56SAlex Deucher /* Set the write pointer delay */ 361a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 362a2e73f56SAlex Deucher 363a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 364a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 365a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 366a2e73f56SAlex Deucher 367a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 368a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 369a2e73f56SAlex Deucher 370a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 371a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 372a2e73f56SAlex Deucher 373a2e73f56SAlex Deucher /* set the ring address */ 374a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 375a2e73f56SAlex Deucher 376a2e73f56SAlex Deucher /* Set ring buffer size */ 377a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 378a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 379a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 380a2e73f56SAlex Deucher 381a2e73f56SAlex Deucher return 0; 382a2e73f56SAlex Deucher } 383a2e73f56SAlex Deucher 384a2e73f56SAlex Deucher /** 385a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 386a2e73f56SAlex Deucher * 387a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 388a2e73f56SAlex Deucher * 389a2e73f56SAlex Deucher * stop the UVD block 390a2e73f56SAlex Deucher */ 391a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 392a2e73f56SAlex Deucher { 393a2e73f56SAlex Deucher /* force RBC into idle state */ 394a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 395a2e73f56SAlex Deucher 396a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 397a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 398a2e73f56SAlex Deucher mdelay(1); 399a2e73f56SAlex Deucher 400a2e73f56SAlex Deucher /* put VCPU into reset */ 401a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 402a2e73f56SAlex Deucher mdelay(5); 403a2e73f56SAlex Deucher 404a2e73f56SAlex Deucher /* disable VCPU clock */ 405a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 406a2e73f56SAlex Deucher 407a2e73f56SAlex Deucher /* Unstall UMC and register bus */ 408a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 409a2e73f56SAlex Deucher } 410a2e73f56SAlex Deucher 411a2e73f56SAlex Deucher /** 412a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 413a2e73f56SAlex Deucher * 414a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 415a2e73f56SAlex Deucher * @fence: fence to emit 416a2e73f56SAlex Deucher * 417a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 418a2e73f56SAlex Deucher */ 419a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 420890ee23fSChunming Zhou unsigned flags) 421a2e73f56SAlex Deucher { 422890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 423a2e73f56SAlex Deucher 424a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 425a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 426a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 427a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 428a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 429a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 430a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 431a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 432a2e73f56SAlex Deucher 433a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 434a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 435a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 436a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 437a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 438a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 439a2e73f56SAlex Deucher } 440a2e73f56SAlex Deucher 441a2e73f56SAlex Deucher /** 442a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 443a2e73f56SAlex Deucher * 444a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 445a2e73f56SAlex Deucher * 446a2e73f56SAlex Deucher * Test if we can successfully write to the context register 447a2e73f56SAlex Deucher */ 448a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 449a2e73f56SAlex Deucher { 450a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 451a2e73f56SAlex Deucher uint32_t tmp = 0; 452a2e73f56SAlex Deucher unsigned i; 453a2e73f56SAlex Deucher int r; 454a2e73f56SAlex Deucher 455a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 456a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 457a2e73f56SAlex Deucher if (r) { 458a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 459a2e73f56SAlex Deucher ring->idx, r); 460a2e73f56SAlex Deucher return r; 461a2e73f56SAlex Deucher } 462a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 463a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 464a27de35cSChristian König amdgpu_ring_commit(ring); 465a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 466a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 467a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 468a2e73f56SAlex Deucher break; 469a2e73f56SAlex Deucher DRM_UDELAY(1); 470a2e73f56SAlex Deucher } 471a2e73f56SAlex Deucher 472a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 473a2e73f56SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 474a2e73f56SAlex Deucher ring->idx, i); 475a2e73f56SAlex Deucher } else { 476a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 477a2e73f56SAlex Deucher ring->idx, tmp); 478a2e73f56SAlex Deucher r = -EINVAL; 479a2e73f56SAlex Deucher } 480a2e73f56SAlex Deucher return r; 481a2e73f56SAlex Deucher } 482a2e73f56SAlex Deucher 483a2e73f56SAlex Deucher /** 484a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 485a2e73f56SAlex Deucher * 486a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 487a2e73f56SAlex Deucher * @ib: indirect buffer to execute 488a2e73f56SAlex Deucher * 489a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 490a2e73f56SAlex Deucher */ 491a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 492a2e73f56SAlex Deucher struct amdgpu_ib *ib) 493a2e73f56SAlex Deucher { 494a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 495a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 496a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 497a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 498a2e73f56SAlex Deucher } 499a2e73f56SAlex Deucher 500a2e73f56SAlex Deucher /** 501a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ib - test ib execution 502a2e73f56SAlex Deucher * 503a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 504a2e73f56SAlex Deucher * 505a2e73f56SAlex Deucher * Test if we can successfully execute an IB 506a2e73f56SAlex Deucher */ 507a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring) 508a2e73f56SAlex Deucher { 509a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 5100e3f154aSChunming Zhou struct fence *fence = NULL; 511a2e73f56SAlex Deucher int r; 512a2e73f56SAlex Deucher 513a2e73f56SAlex Deucher r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 514a2e73f56SAlex Deucher if (r) { 515a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 516a2e73f56SAlex Deucher return r; 517a2e73f56SAlex Deucher } 518a2e73f56SAlex Deucher 519a2e73f56SAlex Deucher r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 520a2e73f56SAlex Deucher if (r) { 521a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 522a2e73f56SAlex Deucher goto error; 523a2e73f56SAlex Deucher } 524a2e73f56SAlex Deucher 525d7af97dbSChristian König r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 526a2e73f56SAlex Deucher if (r) { 527a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 528a2e73f56SAlex Deucher goto error; 529a2e73f56SAlex Deucher } 530a2e73f56SAlex Deucher 5310e3f154aSChunming Zhou r = fence_wait(fence, false); 532a2e73f56SAlex Deucher if (r) { 533a2e73f56SAlex Deucher DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 534a2e73f56SAlex Deucher goto error; 535a2e73f56SAlex Deucher } 536a2e73f56SAlex Deucher DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 537a2e73f56SAlex Deucher error: 5380e3f154aSChunming Zhou fence_put(fence); 539a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 540a2e73f56SAlex Deucher return r; 541a2e73f56SAlex Deucher } 542a2e73f56SAlex Deucher 543a2e73f56SAlex Deucher /** 544a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 545a2e73f56SAlex Deucher * 546a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 547a2e73f56SAlex Deucher * 548a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 549a2e73f56SAlex Deucher */ 550a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 551a2e73f56SAlex Deucher { 552a2e73f56SAlex Deucher uint64_t addr; 553a2e73f56SAlex Deucher uint32_t size; 554a2e73f56SAlex Deucher 555a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 556a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 557a2e73f56SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 558a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 559a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 560a2e73f56SAlex Deucher 561a2e73f56SAlex Deucher addr += size; 562c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 563a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 564a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 565a2e73f56SAlex Deucher 566a2e73f56SAlex Deucher addr += size; 567c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 568c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 569a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 570a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 571a2e73f56SAlex Deucher 572a2e73f56SAlex Deucher /* bits 28-31 */ 573a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 574a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 575a2e73f56SAlex Deucher 576a2e73f56SAlex Deucher /* bits 32-39 */ 577a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 578a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 579a2e73f56SAlex Deucher 58076ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 58176ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 58276ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 58376ed6cb0SAlex Deucher 584a2e73f56SAlex Deucher uvd_v4_2_init_cg(adev); 585a2e73f56SAlex Deucher } 586a2e73f56SAlex Deucher 587a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 588a2e73f56SAlex Deucher bool enable) 589a2e73f56SAlex Deucher { 590a2e73f56SAlex Deucher u32 orig, data; 591a2e73f56SAlex Deucher 592e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 593a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 594a2e73f56SAlex Deucher data = 0xfff; 595a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 596a2e73f56SAlex Deucher 597a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 598a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 599a2e73f56SAlex Deucher if (orig != data) 600a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 601a2e73f56SAlex Deucher } else { 602a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 603a2e73f56SAlex Deucher data &= ~0xfff; 604a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 605a2e73f56SAlex Deucher 606a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 607a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 608a2e73f56SAlex Deucher if (orig != data) 609a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 610a2e73f56SAlex Deucher } 611a2e73f56SAlex Deucher } 612a2e73f56SAlex Deucher 613a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 614a2e73f56SAlex Deucher bool sw_mode) 615a2e73f56SAlex Deucher { 616a2e73f56SAlex Deucher u32 tmp, tmp2; 617a2e73f56SAlex Deucher 618a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 619a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 620a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 621a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 622a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 623a2e73f56SAlex Deucher 624a2e73f56SAlex Deucher if (sw_mode) { 625a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 626a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 627a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 628a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 629a2e73f56SAlex Deucher } else { 630a2e73f56SAlex Deucher tmp |= 0x7ffff800; 631a2e73f56SAlex Deucher tmp2 = 0; 632a2e73f56SAlex Deucher } 633a2e73f56SAlex Deucher 634a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 635a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 636a2e73f56SAlex Deucher } 637a2e73f56SAlex Deucher 638a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 639a2e73f56SAlex Deucher { 640a2e73f56SAlex Deucher bool hw_mode = true; 641a2e73f56SAlex Deucher 642a2e73f56SAlex Deucher if (hw_mode) { 643a2e73f56SAlex Deucher uvd_v4_2_set_dcm(adev, false); 644a2e73f56SAlex Deucher } else { 645a2e73f56SAlex Deucher u32 tmp = RREG32(mmUVD_CGC_CTRL); 646a2e73f56SAlex Deucher tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 647a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 648a2e73f56SAlex Deucher } 649a2e73f56SAlex Deucher } 650a2e73f56SAlex Deucher 6515fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 652a2e73f56SAlex Deucher { 6535fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6545fc3aeebSyanyang1 655a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 656a2e73f56SAlex Deucher } 657a2e73f56SAlex Deucher 6585fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 659a2e73f56SAlex Deucher { 660a2e73f56SAlex Deucher unsigned i; 6615fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662a2e73f56SAlex Deucher 663a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 664a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 665a2e73f56SAlex Deucher return 0; 666a2e73f56SAlex Deucher } 667a2e73f56SAlex Deucher return -ETIMEDOUT; 668a2e73f56SAlex Deucher } 669a2e73f56SAlex Deucher 6705fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 671a2e73f56SAlex Deucher { 6725fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6735fc3aeebSyanyang1 674a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 675a2e73f56SAlex Deucher 676a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 677a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 678a2e73f56SAlex Deucher mdelay(5); 679a2e73f56SAlex Deucher 680a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 681a2e73f56SAlex Deucher } 682a2e73f56SAlex Deucher 6835fc3aeebSyanyang1 static void uvd_v4_2_print_status(void *handle) 684a2e73f56SAlex Deucher { 6855fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 686a2e73f56SAlex Deucher dev_info(adev->dev, "UVD 4.2 registers\n"); 687a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 688a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_ADDR_LOW)); 689a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 690a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_ADDR_HIGH)); 691a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 692a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_CMD)); 693a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 694a2e73f56SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_CMD)); 695a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 696a2e73f56SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA0)); 697a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 698a2e73f56SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA1)); 699a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 700a2e73f56SAlex Deucher RREG32(mmUVD_ENGINE_CNTL)); 701a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 702a2e73f56SAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 703a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 704a2e73f56SAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 705a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 706a2e73f56SAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 707a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 708a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_CNTL)); 709a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 710a2e73f56SAlex Deucher RREG32(mmUVD_LMI_EXT40_ADDR)); 711a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 712a2e73f56SAlex Deucher RREG32(mmUVD_CTX_INDEX)); 713a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 714a2e73f56SAlex Deucher RREG32(mmUVD_CTX_DATA)); 715a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 716a2e73f56SAlex Deucher RREG32(mmUVD_CGC_GATE)); 717a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 718a2e73f56SAlex Deucher RREG32(mmUVD_CGC_CTRL)); 719a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 720a2e73f56SAlex Deucher RREG32(mmUVD_LMI_CTRL2)); 721a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 722a2e73f56SAlex Deucher RREG32(mmUVD_MASTINT_EN)); 723a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 724a2e73f56SAlex Deucher RREG32(mmUVD_LMI_ADDR_EXT)); 725a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 726a2e73f56SAlex Deucher RREG32(mmUVD_LMI_CTRL)); 727a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 728a2e73f56SAlex Deucher RREG32(mmUVD_LMI_SWAP_CNTL)); 729a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 730a2e73f56SAlex Deucher RREG32(mmUVD_MP_SWAP_CNTL)); 731a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 732a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA0)); 733a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 734a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA1)); 735a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 736a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB0)); 737a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 738a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB1)); 739a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 740a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUX)); 741a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 742a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_ALU)); 743a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 744a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 745a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 746a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE0)); 747a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 748a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 749a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 750a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE1)); 751a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 752a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 753a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 754a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE2)); 755a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 756a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CNTL)); 757a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 758a2e73f56SAlex Deucher RREG32(mmUVD_SOFT_RESET)); 759a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n", 760a2e73f56SAlex Deucher RREG32(mmUVD_RBC_IB_BASE)); 761a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 762a2e73f56SAlex Deucher RREG32(mmUVD_RBC_IB_SIZE)); 763a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n", 764a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_BASE)); 765a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 766a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_RPTR)); 767a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 768a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR)); 769a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 770a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 771a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 772a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_CNTL)); 773a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 774a2e73f56SAlex Deucher RREG32(mmUVD_STATUS)); 775a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 776a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 777a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 778a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 779a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 780a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 781a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 782a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 783a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 784a2e73f56SAlex Deucher RREG32(mmUVD_CONTEXT_ID)); 78576ed6cb0SAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 78676ed6cb0SAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 78776ed6cb0SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 78876ed6cb0SAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 78976ed6cb0SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 79076ed6cb0SAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 79176ed6cb0SAlex Deucher 792a2e73f56SAlex Deucher } 793a2e73f56SAlex Deucher 794a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 795a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 796a2e73f56SAlex Deucher unsigned type, 797a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 798a2e73f56SAlex Deucher { 799a2e73f56SAlex Deucher // TODO 800a2e73f56SAlex Deucher return 0; 801a2e73f56SAlex Deucher } 802a2e73f56SAlex Deucher 803a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 804a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 805a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 806a2e73f56SAlex Deucher { 807a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 808a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 809a2e73f56SAlex Deucher return 0; 810a2e73f56SAlex Deucher } 811a2e73f56SAlex Deucher 8125fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 8135fc3aeebSyanyang1 enum amd_clockgating_state state) 814a2e73f56SAlex Deucher { 815a2e73f56SAlex Deucher bool gate = false; 8165fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 817a2e73f56SAlex Deucher 818e3b04bc7SAlex Deucher if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 81935e5912dSAlex Deucher return 0; 82035e5912dSAlex Deucher 8215fc3aeebSyanyang1 if (state == AMD_CG_STATE_GATE) 822a2e73f56SAlex Deucher gate = true; 823a2e73f56SAlex Deucher 824a2e73f56SAlex Deucher uvd_v4_2_enable_mgcg(adev, gate); 825a2e73f56SAlex Deucher 826a2e73f56SAlex Deucher return 0; 827a2e73f56SAlex Deucher } 828a2e73f56SAlex Deucher 8295fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 8305fc3aeebSyanyang1 enum amd_powergating_state state) 831a2e73f56SAlex Deucher { 832a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 833a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 834a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 835a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 836a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 837a2e73f56SAlex Deucher * the smc and the hw blocks 838a2e73f56SAlex Deucher */ 8395fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8405fc3aeebSyanyang1 841e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 842b6df77fcSAlex Deucher return 0; 8435fc3aeebSyanyang1 8445fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 845a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 846a2e73f56SAlex Deucher return 0; 847a2e73f56SAlex Deucher } else { 848a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 849a2e73f56SAlex Deucher } 850a2e73f56SAlex Deucher } 851a2e73f56SAlex Deucher 8525fc3aeebSyanyang1 const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 853a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 854a2e73f56SAlex Deucher .late_init = NULL, 855a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 856a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 857a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 858a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 859a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 860a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 861a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 862a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 863a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 864a2e73f56SAlex Deucher .print_status = uvd_v4_2_print_status, 865a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 866a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 867a2e73f56SAlex Deucher }; 868a2e73f56SAlex Deucher 869a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 870a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 871a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 872a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 873a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 874a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 875a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 876a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 877a2e73f56SAlex Deucher .test_ib = uvd_v4_2_ring_test_ib, 878edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 8799e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 880a2e73f56SAlex Deucher }; 881a2e73f56SAlex Deucher 882a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 883a2e73f56SAlex Deucher { 884a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 885a2e73f56SAlex Deucher } 886a2e73f56SAlex Deucher 887a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 888a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 889a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 890a2e73f56SAlex Deucher }; 891a2e73f56SAlex Deucher 892a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 893a2e73f56SAlex Deucher { 894a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 895a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 896a2e73f56SAlex Deucher } 897