1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 38a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 39a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 40a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 41a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 42a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher 44a2e73f56SAlex Deucher /** 45a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 46a2e73f56SAlex Deucher * 47a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 48a2e73f56SAlex Deucher * 49a2e73f56SAlex Deucher * Returns the current hardware read pointer 50a2e73f56SAlex Deucher */ 51a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 52a2e73f56SAlex Deucher { 53a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 54a2e73f56SAlex Deucher 55a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 56a2e73f56SAlex Deucher } 57a2e73f56SAlex Deucher 58a2e73f56SAlex Deucher /** 59a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 60a2e73f56SAlex Deucher * 61a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 62a2e73f56SAlex Deucher * 63a2e73f56SAlex Deucher * Returns the current hardware write pointer 64a2e73f56SAlex Deucher */ 65a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 66a2e73f56SAlex Deucher { 67a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 68a2e73f56SAlex Deucher 69a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 70a2e73f56SAlex Deucher } 71a2e73f56SAlex Deucher 72a2e73f56SAlex Deucher /** 73a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 74a2e73f56SAlex Deucher * 75a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 76a2e73f56SAlex Deucher * 77a2e73f56SAlex Deucher * Commits the write pointer to the hardware 78a2e73f56SAlex Deucher */ 79a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 80a2e73f56SAlex Deucher { 81a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 82a2e73f56SAlex Deucher 83a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 84a2e73f56SAlex Deucher } 85a2e73f56SAlex Deucher 86a2e73f56SAlex Deucher static int uvd_v4_2_early_init(struct amdgpu_device *adev) 87a2e73f56SAlex Deucher { 88a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 89a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 90a2e73f56SAlex Deucher 91a2e73f56SAlex Deucher return 0; 92a2e73f56SAlex Deucher } 93a2e73f56SAlex Deucher 94a2e73f56SAlex Deucher static int uvd_v4_2_sw_init(struct amdgpu_device *adev) 95a2e73f56SAlex Deucher { 96a2e73f56SAlex Deucher struct amdgpu_ring *ring; 97a2e73f56SAlex Deucher int r; 98a2e73f56SAlex Deucher 99a2e73f56SAlex Deucher /* UVD TRAP */ 100a2e73f56SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 101a2e73f56SAlex Deucher if (r) 102a2e73f56SAlex Deucher return r; 103a2e73f56SAlex Deucher 104a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 105a2e73f56SAlex Deucher if (r) 106a2e73f56SAlex Deucher return r; 107a2e73f56SAlex Deucher 108a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 109a2e73f56SAlex Deucher if (r) 110a2e73f56SAlex Deucher return r; 111a2e73f56SAlex Deucher 112a2e73f56SAlex Deucher ring = &adev->uvd.ring; 113a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 114a2e73f56SAlex Deucher r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 115a2e73f56SAlex Deucher &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 116a2e73f56SAlex Deucher 117a2e73f56SAlex Deucher return r; 118a2e73f56SAlex Deucher } 119a2e73f56SAlex Deucher 120a2e73f56SAlex Deucher static int uvd_v4_2_sw_fini(struct amdgpu_device *adev) 121a2e73f56SAlex Deucher { 122a2e73f56SAlex Deucher int r; 123a2e73f56SAlex Deucher 124a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 125a2e73f56SAlex Deucher if (r) 126a2e73f56SAlex Deucher return r; 127a2e73f56SAlex Deucher 128a2e73f56SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 129a2e73f56SAlex Deucher if (r) 130a2e73f56SAlex Deucher return r; 131a2e73f56SAlex Deucher 132a2e73f56SAlex Deucher return r; 133a2e73f56SAlex Deucher } 134a2e73f56SAlex Deucher 135a2e73f56SAlex Deucher /** 136a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 137a2e73f56SAlex Deucher * 138a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 139a2e73f56SAlex Deucher * 140a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 141a2e73f56SAlex Deucher */ 142a2e73f56SAlex Deucher static int uvd_v4_2_hw_init(struct amdgpu_device *adev) 143a2e73f56SAlex Deucher { 144a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 145a2e73f56SAlex Deucher uint32_t tmp; 146a2e73f56SAlex Deucher int r; 147a2e73f56SAlex Deucher 148a2e73f56SAlex Deucher /* raise clocks while booting up the VCPU */ 149a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 150a2e73f56SAlex Deucher 151a2e73f56SAlex Deucher r = uvd_v4_2_start(adev); 152a2e73f56SAlex Deucher if (r) 153a2e73f56SAlex Deucher goto done; 154a2e73f56SAlex Deucher 155a2e73f56SAlex Deucher ring->ready = true; 156a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 157a2e73f56SAlex Deucher if (r) { 158a2e73f56SAlex Deucher ring->ready = false; 159a2e73f56SAlex Deucher goto done; 160a2e73f56SAlex Deucher } 161a2e73f56SAlex Deucher 162a2e73f56SAlex Deucher r = amdgpu_ring_lock(ring, 10); 163a2e73f56SAlex Deucher if (r) { 164a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 165a2e73f56SAlex Deucher goto done; 166a2e73f56SAlex Deucher } 167a2e73f56SAlex Deucher 168a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 169a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 170a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 171a2e73f56SAlex Deucher 172a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 173a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 174a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 175a2e73f56SAlex Deucher 176a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 177a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 178a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 179a2e73f56SAlex Deucher 180a2e73f56SAlex Deucher /* Clear timeout status bits */ 181a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 182a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 183a2e73f56SAlex Deucher 184a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 185a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 186a2e73f56SAlex Deucher 187a2e73f56SAlex Deucher amdgpu_ring_unlock_commit(ring); 188a2e73f56SAlex Deucher 189a2e73f56SAlex Deucher done: 190a2e73f56SAlex Deucher /* lower clocks again */ 191a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 192a2e73f56SAlex Deucher 193a2e73f56SAlex Deucher if (!r) 194a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 195a2e73f56SAlex Deucher 196a2e73f56SAlex Deucher return r; 197a2e73f56SAlex Deucher } 198a2e73f56SAlex Deucher 199a2e73f56SAlex Deucher /** 200a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 201a2e73f56SAlex Deucher * 202a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 203a2e73f56SAlex Deucher * 204a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 205a2e73f56SAlex Deucher */ 206a2e73f56SAlex Deucher static int uvd_v4_2_hw_fini(struct amdgpu_device *adev) 207a2e73f56SAlex Deucher { 208a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 209a2e73f56SAlex Deucher 210a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 211a2e73f56SAlex Deucher ring->ready = false; 212a2e73f56SAlex Deucher 213a2e73f56SAlex Deucher return 0; 214a2e73f56SAlex Deucher } 215a2e73f56SAlex Deucher 216a2e73f56SAlex Deucher static int uvd_v4_2_suspend(struct amdgpu_device *adev) 217a2e73f56SAlex Deucher { 218a2e73f56SAlex Deucher int r; 219a2e73f56SAlex Deucher 220a2e73f56SAlex Deucher r = uvd_v4_2_hw_fini(adev); 221a2e73f56SAlex Deucher if (r) 222a2e73f56SAlex Deucher return r; 223a2e73f56SAlex Deucher 224a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 225a2e73f56SAlex Deucher if (r) 226a2e73f56SAlex Deucher return r; 227a2e73f56SAlex Deucher 228a2e73f56SAlex Deucher return r; 229a2e73f56SAlex Deucher } 230a2e73f56SAlex Deucher 231a2e73f56SAlex Deucher static int uvd_v4_2_resume(struct amdgpu_device *adev) 232a2e73f56SAlex Deucher { 233a2e73f56SAlex Deucher int r; 234a2e73f56SAlex Deucher 235a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 236a2e73f56SAlex Deucher if (r) 237a2e73f56SAlex Deucher return r; 238a2e73f56SAlex Deucher 239a2e73f56SAlex Deucher r = uvd_v4_2_hw_init(adev); 240a2e73f56SAlex Deucher if (r) 241a2e73f56SAlex Deucher return r; 242a2e73f56SAlex Deucher 243a2e73f56SAlex Deucher return r; 244a2e73f56SAlex Deucher } 245a2e73f56SAlex Deucher 246a2e73f56SAlex Deucher /** 247a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 248a2e73f56SAlex Deucher * 249a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 250a2e73f56SAlex Deucher * 251a2e73f56SAlex Deucher * Setup and start the UVD block 252a2e73f56SAlex Deucher */ 253a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 254a2e73f56SAlex Deucher { 255a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 256a2e73f56SAlex Deucher uint32_t rb_bufsz; 257a2e73f56SAlex Deucher int i, j, r; 258a2e73f56SAlex Deucher 259a2e73f56SAlex Deucher /* disable byte swapping */ 260a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 261a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 262a2e73f56SAlex Deucher 263a2e73f56SAlex Deucher uvd_v4_2_mc_resume(adev); 264a2e73f56SAlex Deucher 265a2e73f56SAlex Deucher /* disable clock gating */ 266a2e73f56SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 267a2e73f56SAlex Deucher 268a2e73f56SAlex Deucher /* disable interupt */ 269a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 270a2e73f56SAlex Deucher 271a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 272a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 273a2e73f56SAlex Deucher mdelay(1); 274a2e73f56SAlex Deucher 275a2e73f56SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 276a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 277a2e73f56SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 278a2e73f56SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 279a2e73f56SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 280a2e73f56SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 281a2e73f56SAlex Deucher mdelay(5); 282a2e73f56SAlex Deucher 283a2e73f56SAlex Deucher /* take UVD block out of reset */ 284a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 285a2e73f56SAlex Deucher mdelay(5); 286a2e73f56SAlex Deucher 287a2e73f56SAlex Deucher /* initialize UVD memory controller */ 288a2e73f56SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 289a2e73f56SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 290a2e73f56SAlex Deucher 291a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 292a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 293a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 294a2e73f56SAlex Deucher mp_swap_cntl = 0; 295a2e73f56SAlex Deucher #endif 296a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 297a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 298a2e73f56SAlex Deucher 299a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 300a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 301a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 302a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 303a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 304a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 305a2e73f56SAlex Deucher 306a2e73f56SAlex Deucher /* take all subblocks out of reset, except VCPU */ 307a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 308a2e73f56SAlex Deucher mdelay(5); 309a2e73f56SAlex Deucher 310a2e73f56SAlex Deucher /* enable VCPU clock */ 311a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 312a2e73f56SAlex Deucher 313a2e73f56SAlex Deucher /* enable UMC */ 314a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 315a2e73f56SAlex Deucher 316a2e73f56SAlex Deucher /* boot up the VCPU */ 317a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 318a2e73f56SAlex Deucher mdelay(10); 319a2e73f56SAlex Deucher 320a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 321a2e73f56SAlex Deucher uint32_t status; 322a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 323a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 324a2e73f56SAlex Deucher if (status & 2) 325a2e73f56SAlex Deucher break; 326a2e73f56SAlex Deucher mdelay(10); 327a2e73f56SAlex Deucher } 328a2e73f56SAlex Deucher r = 0; 329a2e73f56SAlex Deucher if (status & 2) 330a2e73f56SAlex Deucher break; 331a2e73f56SAlex Deucher 332a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 333a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 334a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 335a2e73f56SAlex Deucher mdelay(10); 336a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 337a2e73f56SAlex Deucher mdelay(10); 338a2e73f56SAlex Deucher r = -1; 339a2e73f56SAlex Deucher } 340a2e73f56SAlex Deucher 341a2e73f56SAlex Deucher if (r) { 342a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 343a2e73f56SAlex Deucher return r; 344a2e73f56SAlex Deucher } 345a2e73f56SAlex Deucher 346a2e73f56SAlex Deucher /* enable interupt */ 347a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 348a2e73f56SAlex Deucher 349a2e73f56SAlex Deucher /* force RBC into idle state */ 350a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 351a2e73f56SAlex Deucher 352a2e73f56SAlex Deucher /* Set the write pointer delay */ 353a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 354a2e73f56SAlex Deucher 355a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 356a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 357a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 358a2e73f56SAlex Deucher 359a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 360a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 361a2e73f56SAlex Deucher 362a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 363a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 364a2e73f56SAlex Deucher 365a2e73f56SAlex Deucher /* set the ring address */ 366a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 367a2e73f56SAlex Deucher 368a2e73f56SAlex Deucher /* Set ring buffer size */ 369a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 370a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 371a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 372a2e73f56SAlex Deucher 373a2e73f56SAlex Deucher return 0; 374a2e73f56SAlex Deucher } 375a2e73f56SAlex Deucher 376a2e73f56SAlex Deucher /** 377a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 378a2e73f56SAlex Deucher * 379a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 380a2e73f56SAlex Deucher * 381a2e73f56SAlex Deucher * stop the UVD block 382a2e73f56SAlex Deucher */ 383a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 384a2e73f56SAlex Deucher { 385a2e73f56SAlex Deucher /* force RBC into idle state */ 386a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 387a2e73f56SAlex Deucher 388a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 389a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 390a2e73f56SAlex Deucher mdelay(1); 391a2e73f56SAlex Deucher 392a2e73f56SAlex Deucher /* put VCPU into reset */ 393a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 394a2e73f56SAlex Deucher mdelay(5); 395a2e73f56SAlex Deucher 396a2e73f56SAlex Deucher /* disable VCPU clock */ 397a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 398a2e73f56SAlex Deucher 399a2e73f56SAlex Deucher /* Unstall UMC and register bus */ 400a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 401a2e73f56SAlex Deucher } 402a2e73f56SAlex Deucher 403a2e73f56SAlex Deucher /** 404a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 405a2e73f56SAlex Deucher * 406a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 407a2e73f56SAlex Deucher * @fence: fence to emit 408a2e73f56SAlex Deucher * 409a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 410a2e73f56SAlex Deucher */ 411a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 412a2e73f56SAlex Deucher bool write64bit) 413a2e73f56SAlex Deucher { 414a2e73f56SAlex Deucher WARN_ON(write64bit); 415a2e73f56SAlex Deucher 416a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 417a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 418a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 419a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 420a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 421a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 422a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 423a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 424a2e73f56SAlex Deucher 425a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 426a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 427a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 428a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 429a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 430a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 431a2e73f56SAlex Deucher } 432a2e73f56SAlex Deucher 433a2e73f56SAlex Deucher /** 434a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_semaphore - emit semaphore command 435a2e73f56SAlex Deucher * 436a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 437a2e73f56SAlex Deucher * @semaphore: semaphore to emit commands for 438a2e73f56SAlex Deucher * @emit_wait: true if we should emit a wait command 439a2e73f56SAlex Deucher * 440a2e73f56SAlex Deucher * Emit a semaphore command (either wait or signal) to the UVD ring. 441a2e73f56SAlex Deucher */ 442a2e73f56SAlex Deucher static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring, 443a2e73f56SAlex Deucher struct amdgpu_semaphore *semaphore, 444a2e73f56SAlex Deucher bool emit_wait) 445a2e73f56SAlex Deucher { 446a2e73f56SAlex Deucher uint64_t addr = semaphore->gpu_addr; 447a2e73f56SAlex Deucher 448a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); 449a2e73f56SAlex Deucher amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); 450a2e73f56SAlex Deucher 451a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); 452a2e73f56SAlex Deucher amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); 453a2e73f56SAlex Deucher 454a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); 455a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); 456a2e73f56SAlex Deucher 457a2e73f56SAlex Deucher return true; 458a2e73f56SAlex Deucher } 459a2e73f56SAlex Deucher 460a2e73f56SAlex Deucher /** 461a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 462a2e73f56SAlex Deucher * 463a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 464a2e73f56SAlex Deucher * 465a2e73f56SAlex Deucher * Test if we can successfully write to the context register 466a2e73f56SAlex Deucher */ 467a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 468a2e73f56SAlex Deucher { 469a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 470a2e73f56SAlex Deucher uint32_t tmp = 0; 471a2e73f56SAlex Deucher unsigned i; 472a2e73f56SAlex Deucher int r; 473a2e73f56SAlex Deucher 474a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 475a2e73f56SAlex Deucher r = amdgpu_ring_lock(ring, 3); 476a2e73f56SAlex Deucher if (r) { 477a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 478a2e73f56SAlex Deucher ring->idx, r); 479a2e73f56SAlex Deucher return r; 480a2e73f56SAlex Deucher } 481a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 482a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 483a2e73f56SAlex Deucher amdgpu_ring_unlock_commit(ring); 484a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 485a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 486a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 487a2e73f56SAlex Deucher break; 488a2e73f56SAlex Deucher DRM_UDELAY(1); 489a2e73f56SAlex Deucher } 490a2e73f56SAlex Deucher 491a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 492a2e73f56SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 493a2e73f56SAlex Deucher ring->idx, i); 494a2e73f56SAlex Deucher } else { 495a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 496a2e73f56SAlex Deucher ring->idx, tmp); 497a2e73f56SAlex Deucher r = -EINVAL; 498a2e73f56SAlex Deucher } 499a2e73f56SAlex Deucher return r; 500a2e73f56SAlex Deucher } 501a2e73f56SAlex Deucher 502a2e73f56SAlex Deucher /** 503a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 504a2e73f56SAlex Deucher * 505a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 506a2e73f56SAlex Deucher * @ib: indirect buffer to execute 507a2e73f56SAlex Deucher * 508a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 509a2e73f56SAlex Deucher */ 510a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 511a2e73f56SAlex Deucher struct amdgpu_ib *ib) 512a2e73f56SAlex Deucher { 513a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 514a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 515a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 516a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 517a2e73f56SAlex Deucher } 518a2e73f56SAlex Deucher 519a2e73f56SAlex Deucher /** 520a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ib - test ib execution 521a2e73f56SAlex Deucher * 522a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 523a2e73f56SAlex Deucher * 524a2e73f56SAlex Deucher * Test if we can successfully execute an IB 525a2e73f56SAlex Deucher */ 526a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring) 527a2e73f56SAlex Deucher { 528a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 529a2e73f56SAlex Deucher struct amdgpu_fence *fence = NULL; 530a2e73f56SAlex Deucher int r; 531a2e73f56SAlex Deucher 532a2e73f56SAlex Deucher r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 533a2e73f56SAlex Deucher if (r) { 534a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); 535a2e73f56SAlex Deucher return r; 536a2e73f56SAlex Deucher } 537a2e73f56SAlex Deucher 538a2e73f56SAlex Deucher r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 539a2e73f56SAlex Deucher if (r) { 540a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 541a2e73f56SAlex Deucher goto error; 542a2e73f56SAlex Deucher } 543a2e73f56SAlex Deucher 544a2e73f56SAlex Deucher r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence); 545a2e73f56SAlex Deucher if (r) { 546a2e73f56SAlex Deucher DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 547a2e73f56SAlex Deucher goto error; 548a2e73f56SAlex Deucher } 549a2e73f56SAlex Deucher 550a2e73f56SAlex Deucher r = amdgpu_fence_wait(fence, false); 551a2e73f56SAlex Deucher if (r) { 552a2e73f56SAlex Deucher DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 553a2e73f56SAlex Deucher goto error; 554a2e73f56SAlex Deucher } 555a2e73f56SAlex Deucher DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 556a2e73f56SAlex Deucher error: 557a2e73f56SAlex Deucher amdgpu_fence_unref(&fence); 558a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 559a2e73f56SAlex Deucher return r; 560a2e73f56SAlex Deucher } 561a2e73f56SAlex Deucher 562a2e73f56SAlex Deucher /** 563a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 564a2e73f56SAlex Deucher * 565a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 566a2e73f56SAlex Deucher * 567a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 568a2e73f56SAlex Deucher */ 569a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 570a2e73f56SAlex Deucher { 571a2e73f56SAlex Deucher uint64_t addr; 572a2e73f56SAlex Deucher uint32_t size; 573a2e73f56SAlex Deucher 574a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 575a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 576a2e73f56SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 577a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 578a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 579a2e73f56SAlex Deucher 580a2e73f56SAlex Deucher addr += size; 581a2e73f56SAlex Deucher size = AMDGPU_UVD_STACK_SIZE >> 3; 582a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 583a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 584a2e73f56SAlex Deucher 585a2e73f56SAlex Deucher addr += size; 586a2e73f56SAlex Deucher size = AMDGPU_UVD_HEAP_SIZE >> 3; 587a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 588a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 589a2e73f56SAlex Deucher 590a2e73f56SAlex Deucher /* bits 28-31 */ 591a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 592a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 593a2e73f56SAlex Deucher 594a2e73f56SAlex Deucher /* bits 32-39 */ 595a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 596a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 597a2e73f56SAlex Deucher 598a2e73f56SAlex Deucher uvd_v4_2_init_cg(adev); 599a2e73f56SAlex Deucher } 600a2e73f56SAlex Deucher 601a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 602a2e73f56SAlex Deucher bool enable) 603a2e73f56SAlex Deucher { 604a2e73f56SAlex Deucher u32 orig, data; 605a2e73f56SAlex Deucher 606a2e73f56SAlex Deucher if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) { 607a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 608a2e73f56SAlex Deucher data = 0xfff; 609a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 610a2e73f56SAlex Deucher 611a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 612a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 613a2e73f56SAlex Deucher if (orig != data) 614a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 615a2e73f56SAlex Deucher } else { 616a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 617a2e73f56SAlex Deucher data &= ~0xfff; 618a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 619a2e73f56SAlex Deucher 620a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 621a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 622a2e73f56SAlex Deucher if (orig != data) 623a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 624a2e73f56SAlex Deucher } 625a2e73f56SAlex Deucher } 626a2e73f56SAlex Deucher 627a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 628a2e73f56SAlex Deucher bool sw_mode) 629a2e73f56SAlex Deucher { 630a2e73f56SAlex Deucher u32 tmp, tmp2; 631a2e73f56SAlex Deucher 632a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 633a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 634a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 635a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 636a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 637a2e73f56SAlex Deucher 638a2e73f56SAlex Deucher if (sw_mode) { 639a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 640a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 641a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 642a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 643a2e73f56SAlex Deucher } else { 644a2e73f56SAlex Deucher tmp |= 0x7ffff800; 645a2e73f56SAlex Deucher tmp2 = 0; 646a2e73f56SAlex Deucher } 647a2e73f56SAlex Deucher 648a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 649a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 650a2e73f56SAlex Deucher } 651a2e73f56SAlex Deucher 652a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 653a2e73f56SAlex Deucher { 654a2e73f56SAlex Deucher bool hw_mode = true; 655a2e73f56SAlex Deucher 656a2e73f56SAlex Deucher if (hw_mode) { 657a2e73f56SAlex Deucher uvd_v4_2_set_dcm(adev, false); 658a2e73f56SAlex Deucher } else { 659a2e73f56SAlex Deucher u32 tmp = RREG32(mmUVD_CGC_CTRL); 660a2e73f56SAlex Deucher tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 661a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 662a2e73f56SAlex Deucher } 663a2e73f56SAlex Deucher } 664a2e73f56SAlex Deucher 665a2e73f56SAlex Deucher static bool uvd_v4_2_is_idle(struct amdgpu_device *adev) 666a2e73f56SAlex Deucher { 667a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 668a2e73f56SAlex Deucher } 669a2e73f56SAlex Deucher 670a2e73f56SAlex Deucher static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev) 671a2e73f56SAlex Deucher { 672a2e73f56SAlex Deucher unsigned i; 673a2e73f56SAlex Deucher 674a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 675a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 676a2e73f56SAlex Deucher return 0; 677a2e73f56SAlex Deucher } 678a2e73f56SAlex Deucher return -ETIMEDOUT; 679a2e73f56SAlex Deucher } 680a2e73f56SAlex Deucher 681a2e73f56SAlex Deucher static int uvd_v4_2_soft_reset(struct amdgpu_device *adev) 682a2e73f56SAlex Deucher { 683a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 684a2e73f56SAlex Deucher 685a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 686a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 687a2e73f56SAlex Deucher mdelay(5); 688a2e73f56SAlex Deucher 689a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 690a2e73f56SAlex Deucher } 691a2e73f56SAlex Deucher 692a2e73f56SAlex Deucher static void uvd_v4_2_print_status(struct amdgpu_device *adev) 693a2e73f56SAlex Deucher { 694a2e73f56SAlex Deucher dev_info(adev->dev, "UVD 4.2 registers\n"); 695a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 696a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_ADDR_LOW)); 697a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 698a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_ADDR_HIGH)); 699a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 700a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_CMD)); 701a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 702a2e73f56SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_CMD)); 703a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 704a2e73f56SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA0)); 705a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 706a2e73f56SAlex Deucher RREG32(mmUVD_GPCOM_VCPU_DATA1)); 707a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 708a2e73f56SAlex Deucher RREG32(mmUVD_ENGINE_CNTL)); 709a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 710a2e73f56SAlex Deucher RREG32(mmUVD_UDEC_ADDR_CONFIG)); 711a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 712a2e73f56SAlex Deucher RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 713a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 714a2e73f56SAlex Deucher RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 715a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 716a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_CNTL)); 717a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 718a2e73f56SAlex Deucher RREG32(mmUVD_LMI_EXT40_ADDR)); 719a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 720a2e73f56SAlex Deucher RREG32(mmUVD_CTX_INDEX)); 721a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 722a2e73f56SAlex Deucher RREG32(mmUVD_CTX_DATA)); 723a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 724a2e73f56SAlex Deucher RREG32(mmUVD_CGC_GATE)); 725a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 726a2e73f56SAlex Deucher RREG32(mmUVD_CGC_CTRL)); 727a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 728a2e73f56SAlex Deucher RREG32(mmUVD_LMI_CTRL2)); 729a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 730a2e73f56SAlex Deucher RREG32(mmUVD_MASTINT_EN)); 731a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 732a2e73f56SAlex Deucher RREG32(mmUVD_LMI_ADDR_EXT)); 733a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 734a2e73f56SAlex Deucher RREG32(mmUVD_LMI_CTRL)); 735a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 736a2e73f56SAlex Deucher RREG32(mmUVD_LMI_SWAP_CNTL)); 737a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 738a2e73f56SAlex Deucher RREG32(mmUVD_MP_SWAP_CNTL)); 739a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 740a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA0)); 741a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 742a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXA1)); 743a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 744a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB0)); 745a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 746a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUXB1)); 747a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 748a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_MUX)); 749a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 750a2e73f56SAlex Deucher RREG32(mmUVD_MPC_SET_ALU)); 751a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 752a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 753a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 754a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE0)); 755a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 756a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 757a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 758a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE1)); 759a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 760a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 761a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 762a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CACHE_SIZE2)); 763a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 764a2e73f56SAlex Deucher RREG32(mmUVD_VCPU_CNTL)); 765a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 766a2e73f56SAlex Deucher RREG32(mmUVD_SOFT_RESET)); 767a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n", 768a2e73f56SAlex Deucher RREG32(mmUVD_RBC_IB_BASE)); 769a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 770a2e73f56SAlex Deucher RREG32(mmUVD_RBC_IB_SIZE)); 771a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n", 772a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_BASE)); 773a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 774a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_RPTR)); 775a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 776a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR)); 777a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 778a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 779a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 780a2e73f56SAlex Deucher RREG32(mmUVD_RBC_RB_CNTL)); 781a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 782a2e73f56SAlex Deucher RREG32(mmUVD_STATUS)); 783a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 784a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 785a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 786a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 787a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 788a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 789a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 790a2e73f56SAlex Deucher RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 791a2e73f56SAlex Deucher dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 792a2e73f56SAlex Deucher RREG32(mmUVD_CONTEXT_ID)); 793a2e73f56SAlex Deucher } 794a2e73f56SAlex Deucher 795a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 796a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 797a2e73f56SAlex Deucher unsigned type, 798a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 799a2e73f56SAlex Deucher { 800a2e73f56SAlex Deucher // TODO 801a2e73f56SAlex Deucher return 0; 802a2e73f56SAlex Deucher } 803a2e73f56SAlex Deucher 804a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 805a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 806a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 807a2e73f56SAlex Deucher { 808a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 809a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 810a2e73f56SAlex Deucher return 0; 811a2e73f56SAlex Deucher } 812a2e73f56SAlex Deucher 813a2e73f56SAlex Deucher static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev, 814a2e73f56SAlex Deucher enum amdgpu_clockgating_state state) 815a2e73f56SAlex Deucher { 816a2e73f56SAlex Deucher bool gate = false; 817a2e73f56SAlex Deucher 818a2e73f56SAlex Deucher if (state == AMDGPU_CG_STATE_GATE) 819a2e73f56SAlex Deucher gate = true; 820a2e73f56SAlex Deucher 821a2e73f56SAlex Deucher uvd_v4_2_enable_mgcg(adev, gate); 822a2e73f56SAlex Deucher 823a2e73f56SAlex Deucher return 0; 824a2e73f56SAlex Deucher } 825a2e73f56SAlex Deucher 826a2e73f56SAlex Deucher static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev, 827a2e73f56SAlex Deucher enum amdgpu_powergating_state state) 828a2e73f56SAlex Deucher { 829a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 830a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 831a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 832a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 833a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 834a2e73f56SAlex Deucher * the smc and the hw blocks 835a2e73f56SAlex Deucher */ 836a2e73f56SAlex Deucher if (state == AMDGPU_PG_STATE_GATE) { 837a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 838a2e73f56SAlex Deucher return 0; 839a2e73f56SAlex Deucher } else { 840a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 841a2e73f56SAlex Deucher } 842a2e73f56SAlex Deucher } 843a2e73f56SAlex Deucher 844a2e73f56SAlex Deucher const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = { 845a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 846a2e73f56SAlex Deucher .late_init = NULL, 847a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 848a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 849a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 850a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 851a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 852a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 853a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 854a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 855a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 856a2e73f56SAlex Deucher .print_status = uvd_v4_2_print_status, 857a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 858a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 859a2e73f56SAlex Deucher }; 860a2e73f56SAlex Deucher 861a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 862a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 863a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 864a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 865a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 866a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 867a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 868a2e73f56SAlex Deucher .emit_semaphore = uvd_v4_2_ring_emit_semaphore, 869a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 870a2e73f56SAlex Deucher .test_ib = uvd_v4_2_ring_test_ib, 871a2e73f56SAlex Deucher .is_lockup = amdgpu_ring_test_lockup, 872a2e73f56SAlex Deucher }; 873a2e73f56SAlex Deucher 874a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 875a2e73f56SAlex Deucher { 876a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 877a2e73f56SAlex Deucher } 878a2e73f56SAlex Deucher 879a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 880a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 881a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 882a2e73f56SAlex Deucher }; 883a2e73f56SAlex Deucher 884a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 885a2e73f56SAlex Deucher { 886a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 887a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 888a2e73f56SAlex Deucher } 889