1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37d5b4e25dSChristian König #include "bif/bif_4_1_d.h" 38d5b4e25dSChristian König 394be5097cSRex Zhu #include "smu/smu_7_0_1_d.h" 404be5097cSRex Zhu #include "smu/smu_7_0_1_sh_mask.h" 414be5097cSRex Zhu 42a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 44a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 45a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 46a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 47a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 48aa4747c0SRex Zhu static int uvd_v4_2_set_clockgating_state(void *handle, 49aa4747c0SRex Zhu enum amd_clockgating_state state); 50a2e73f56SAlex Deucher /** 51a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 52a2e73f56SAlex Deucher * 53a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 54a2e73f56SAlex Deucher * 55a2e73f56SAlex Deucher * Returns the current hardware read pointer 56a2e73f56SAlex Deucher */ 57a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 58a2e73f56SAlex Deucher { 59a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 60a2e73f56SAlex Deucher 61a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 62a2e73f56SAlex Deucher } 63a2e73f56SAlex Deucher 64a2e73f56SAlex Deucher /** 65a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 66a2e73f56SAlex Deucher * 67a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 68a2e73f56SAlex Deucher * 69a2e73f56SAlex Deucher * Returns the current hardware write pointer 70a2e73f56SAlex Deucher */ 71a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 72a2e73f56SAlex Deucher { 73a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 74a2e73f56SAlex Deucher 75a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 76a2e73f56SAlex Deucher } 77a2e73f56SAlex Deucher 78a2e73f56SAlex Deucher /** 79a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 80a2e73f56SAlex Deucher * 81a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 82a2e73f56SAlex Deucher * 83a2e73f56SAlex Deucher * Commits the write pointer to the hardware 84a2e73f56SAlex Deucher */ 85a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 86a2e73f56SAlex Deucher { 87a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 88a2e73f56SAlex Deucher 89a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 90a2e73f56SAlex Deucher } 91a2e73f56SAlex Deucher 925fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 93a2e73f56SAlex Deucher { 945fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 955fc3aeebSyanyang1 96a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 97a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 98a2e73f56SAlex Deucher 99a2e73f56SAlex Deucher return 0; 100a2e73f56SAlex Deucher } 101a2e73f56SAlex Deucher 1025fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 103a2e73f56SAlex Deucher { 104a2e73f56SAlex Deucher struct amdgpu_ring *ring; 1055fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 106a2e73f56SAlex Deucher int r; 107a2e73f56SAlex Deucher 108a2e73f56SAlex Deucher /* UVD TRAP */ 109a2e73f56SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 110a2e73f56SAlex Deucher if (r) 111a2e73f56SAlex Deucher return r; 112a2e73f56SAlex Deucher 113a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 114a2e73f56SAlex Deucher if (r) 115a2e73f56SAlex Deucher return r; 116a2e73f56SAlex Deucher 117a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 118a2e73f56SAlex Deucher if (r) 119a2e73f56SAlex Deucher return r; 120a2e73f56SAlex Deucher 121a2e73f56SAlex Deucher ring = &adev->uvd.ring; 122a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 12379887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 124a2e73f56SAlex Deucher 125a2e73f56SAlex Deucher return r; 126a2e73f56SAlex Deucher } 127a2e73f56SAlex Deucher 1285fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 129a2e73f56SAlex Deucher { 130a2e73f56SAlex Deucher int r; 1315fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 132a2e73f56SAlex Deucher 133a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 134a2e73f56SAlex Deucher if (r) 135a2e73f56SAlex Deucher return r; 136a2e73f56SAlex Deucher 137a2e73f56SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 138a2e73f56SAlex Deucher if (r) 139a2e73f56SAlex Deucher return r; 140a2e73f56SAlex Deucher 141a2e73f56SAlex Deucher return r; 142a2e73f56SAlex Deucher } 143a2e73f56SAlex Deucher 144a2e73f56SAlex Deucher /** 145a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 146a2e73f56SAlex Deucher * 147a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 148a2e73f56SAlex Deucher * 149a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 150a2e73f56SAlex Deucher */ 1515fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 152a2e73f56SAlex Deucher { 1535fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 154a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 155a2e73f56SAlex Deucher uint32_t tmp; 156a2e73f56SAlex Deucher int r; 157a2e73f56SAlex Deucher 158aa4747c0SRex Zhu uvd_v4_2_init_cg(adev); 159aa4747c0SRex Zhu uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE); 160aa4747c0SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 161a2e73f56SAlex Deucher r = uvd_v4_2_start(adev); 162a2e73f56SAlex Deucher if (r) 163a2e73f56SAlex Deucher goto done; 164a2e73f56SAlex Deucher 165a2e73f56SAlex Deucher ring->ready = true; 166a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 167a2e73f56SAlex Deucher if (r) { 168a2e73f56SAlex Deucher ring->ready = false; 169a2e73f56SAlex Deucher goto done; 170a2e73f56SAlex Deucher } 171a2e73f56SAlex Deucher 172a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 173a2e73f56SAlex Deucher if (r) { 174a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 175a2e73f56SAlex Deucher goto done; 176a2e73f56SAlex Deucher } 177a2e73f56SAlex Deucher 178a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 179a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 180a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 181a2e73f56SAlex Deucher 182a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 183a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 184a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 185a2e73f56SAlex Deucher 186a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 187a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 188a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 189a2e73f56SAlex Deucher 190a2e73f56SAlex Deucher /* Clear timeout status bits */ 191a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 192a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 193a2e73f56SAlex Deucher 194a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 195a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 196a2e73f56SAlex Deucher 197a27de35cSChristian König amdgpu_ring_commit(ring); 198a2e73f56SAlex Deucher 199a2e73f56SAlex Deucher done: 200a2e73f56SAlex Deucher 201a2e73f56SAlex Deucher if (!r) 202a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 203a2e73f56SAlex Deucher 204a2e73f56SAlex Deucher return r; 205a2e73f56SAlex Deucher } 206a2e73f56SAlex Deucher 207a2e73f56SAlex Deucher /** 208a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 209a2e73f56SAlex Deucher * 210a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 211a2e73f56SAlex Deucher * 212a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 213a2e73f56SAlex Deucher */ 2145fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 215a2e73f56SAlex Deucher { 2165fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 217a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 218a2e73f56SAlex Deucher 219a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 220a2e73f56SAlex Deucher ring->ready = false; 221a2e73f56SAlex Deucher 222a2e73f56SAlex Deucher return 0; 223a2e73f56SAlex Deucher } 224a2e73f56SAlex Deucher 2255fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 226a2e73f56SAlex Deucher { 227a2e73f56SAlex Deucher int r; 2285fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 229a2e73f56SAlex Deucher 2303f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 231a2e73f56SAlex Deucher if (r) 232a2e73f56SAlex Deucher return r; 233a2e73f56SAlex Deucher 2343f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 235a2e73f56SAlex Deucher if (r) 236a2e73f56SAlex Deucher return r; 237a2e73f56SAlex Deucher 238a2e73f56SAlex Deucher return r; 239a2e73f56SAlex Deucher } 240a2e73f56SAlex Deucher 2415fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 242a2e73f56SAlex Deucher { 243a2e73f56SAlex Deucher int r; 2445fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 245a2e73f56SAlex Deucher 246a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 247a2e73f56SAlex Deucher if (r) 248a2e73f56SAlex Deucher return r; 249a2e73f56SAlex Deucher 250a2e73f56SAlex Deucher r = uvd_v4_2_hw_init(adev); 251a2e73f56SAlex Deucher if (r) 252a2e73f56SAlex Deucher return r; 253a2e73f56SAlex Deucher 254a2e73f56SAlex Deucher return r; 255a2e73f56SAlex Deucher } 256a2e73f56SAlex Deucher 257a2e73f56SAlex Deucher /** 258a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 259a2e73f56SAlex Deucher * 260a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 261a2e73f56SAlex Deucher * 262a2e73f56SAlex Deucher * Setup and start the UVD block 263a2e73f56SAlex Deucher */ 264a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 265a2e73f56SAlex Deucher { 266a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 267a2e73f56SAlex Deucher uint32_t rb_bufsz; 268a2e73f56SAlex Deucher int i, j, r; 269a2e73f56SAlex Deucher 270a2e73f56SAlex Deucher /* disable byte swapping */ 271a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 272a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 273a2e73f56SAlex Deucher 274a2e73f56SAlex Deucher uvd_v4_2_mc_resume(adev); 275a2e73f56SAlex Deucher 276a2e73f56SAlex Deucher /* disable interupt */ 277a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 278a2e73f56SAlex Deucher 279a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 280a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 281a2e73f56SAlex Deucher mdelay(1); 282a2e73f56SAlex Deucher 283a2e73f56SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 284a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 285a2e73f56SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 286a2e73f56SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 287a2e73f56SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 288a2e73f56SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 289a2e73f56SAlex Deucher mdelay(5); 290a2e73f56SAlex Deucher 291a2e73f56SAlex Deucher /* take UVD block out of reset */ 292a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 293a2e73f56SAlex Deucher mdelay(5); 294a2e73f56SAlex Deucher 295a2e73f56SAlex Deucher /* initialize UVD memory controller */ 296a2e73f56SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 297a2e73f56SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 298a2e73f56SAlex Deucher 299a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 300a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 301a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 302a2e73f56SAlex Deucher mp_swap_cntl = 0; 303a2e73f56SAlex Deucher #endif 304a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 305a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 306a2e73f56SAlex Deucher 307a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 308a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 309a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 310a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 311a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 312a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 313a2e73f56SAlex Deucher 314a2e73f56SAlex Deucher /* take all subblocks out of reset, except VCPU */ 315a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 316a2e73f56SAlex Deucher mdelay(5); 317a2e73f56SAlex Deucher 318a2e73f56SAlex Deucher /* enable VCPU clock */ 319a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 320a2e73f56SAlex Deucher 321a2e73f56SAlex Deucher /* enable UMC */ 322a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 323a2e73f56SAlex Deucher 324a2e73f56SAlex Deucher /* boot up the VCPU */ 325a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 326a2e73f56SAlex Deucher mdelay(10); 327a2e73f56SAlex Deucher 328a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 329a2e73f56SAlex Deucher uint32_t status; 330a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 331a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 332a2e73f56SAlex Deucher if (status & 2) 333a2e73f56SAlex Deucher break; 334a2e73f56SAlex Deucher mdelay(10); 335a2e73f56SAlex Deucher } 336a2e73f56SAlex Deucher r = 0; 337a2e73f56SAlex Deucher if (status & 2) 338a2e73f56SAlex Deucher break; 339a2e73f56SAlex Deucher 340a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 341a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 342a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 343a2e73f56SAlex Deucher mdelay(10); 344a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 345a2e73f56SAlex Deucher mdelay(10); 346a2e73f56SAlex Deucher r = -1; 347a2e73f56SAlex Deucher } 348a2e73f56SAlex Deucher 349a2e73f56SAlex Deucher if (r) { 350a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 351a2e73f56SAlex Deucher return r; 352a2e73f56SAlex Deucher } 353a2e73f56SAlex Deucher 354a2e73f56SAlex Deucher /* enable interupt */ 355a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 356a2e73f56SAlex Deucher 357a2e73f56SAlex Deucher /* force RBC into idle state */ 358a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 359a2e73f56SAlex Deucher 360a2e73f56SAlex Deucher /* Set the write pointer delay */ 361a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 362a2e73f56SAlex Deucher 363a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 364a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 365a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 366a2e73f56SAlex Deucher 367a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 368a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 369a2e73f56SAlex Deucher 370a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 371a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 372a2e73f56SAlex Deucher 373a2e73f56SAlex Deucher /* set the ring address */ 374a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 375a2e73f56SAlex Deucher 376a2e73f56SAlex Deucher /* Set ring buffer size */ 377a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 378a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 379a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 380a2e73f56SAlex Deucher 381a2e73f56SAlex Deucher return 0; 382a2e73f56SAlex Deucher } 383a2e73f56SAlex Deucher 384a2e73f56SAlex Deucher /** 385a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 386a2e73f56SAlex Deucher * 387a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 388a2e73f56SAlex Deucher * 389a2e73f56SAlex Deucher * stop the UVD block 390a2e73f56SAlex Deucher */ 391a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 392a2e73f56SAlex Deucher { 393a2e73f56SAlex Deucher /* force RBC into idle state */ 394a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 395a2e73f56SAlex Deucher 396a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 397a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 398a2e73f56SAlex Deucher mdelay(1); 399a2e73f56SAlex Deucher 400a2e73f56SAlex Deucher /* put VCPU into reset */ 401a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 402a2e73f56SAlex Deucher mdelay(5); 403a2e73f56SAlex Deucher 404a2e73f56SAlex Deucher /* disable VCPU clock */ 405a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 406a2e73f56SAlex Deucher 407a2e73f56SAlex Deucher /* Unstall UMC and register bus */ 408a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 409a2e73f56SAlex Deucher } 410a2e73f56SAlex Deucher 411a2e73f56SAlex Deucher /** 412a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 413a2e73f56SAlex Deucher * 414a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 415a2e73f56SAlex Deucher * @fence: fence to emit 416a2e73f56SAlex Deucher * 417a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 418a2e73f56SAlex Deucher */ 419a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 420890ee23fSChunming Zhou unsigned flags) 421a2e73f56SAlex Deucher { 422890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 423a2e73f56SAlex Deucher 424a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 425a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 426a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 427a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 428a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 429a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 430a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 431a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 432a2e73f56SAlex Deucher 433a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 434a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 435a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 436a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 437a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 438a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 439a2e73f56SAlex Deucher } 440a2e73f56SAlex Deucher 441a2e73f56SAlex Deucher /** 442d5b4e25dSChristian König * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush 443d5b4e25dSChristian König * 444d5b4e25dSChristian König * @ring: amdgpu_ring pointer 445d5b4e25dSChristian König * 446d5b4e25dSChristian König * Emits an hdp flush. 447d5b4e25dSChristian König */ 448d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 449d5b4e25dSChristian König { 450d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 451d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 452d5b4e25dSChristian König } 453d5b4e25dSChristian König 454d5b4e25dSChristian König /** 455d5b4e25dSChristian König * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate 456d5b4e25dSChristian König * 457d5b4e25dSChristian König * @ring: amdgpu_ring pointer 458d5b4e25dSChristian König * 459d5b4e25dSChristian König * Emits an hdp invalidate. 460d5b4e25dSChristian König */ 461d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 462d5b4e25dSChristian König { 463d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 464d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 465d5b4e25dSChristian König } 466d5b4e25dSChristian König 467d5b4e25dSChristian König /** 468a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 469a2e73f56SAlex Deucher * 470a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 471a2e73f56SAlex Deucher * 472a2e73f56SAlex Deucher * Test if we can successfully write to the context register 473a2e73f56SAlex Deucher */ 474a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 475a2e73f56SAlex Deucher { 476a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 477a2e73f56SAlex Deucher uint32_t tmp = 0; 478a2e73f56SAlex Deucher unsigned i; 479a2e73f56SAlex Deucher int r; 480a2e73f56SAlex Deucher 481a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 482a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 483a2e73f56SAlex Deucher if (r) { 484a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 485a2e73f56SAlex Deucher ring->idx, r); 486a2e73f56SAlex Deucher return r; 487a2e73f56SAlex Deucher } 488a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 489a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 490a27de35cSChristian König amdgpu_ring_commit(ring); 491a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 492a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 493a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 494a2e73f56SAlex Deucher break; 495a2e73f56SAlex Deucher DRM_UDELAY(1); 496a2e73f56SAlex Deucher } 497a2e73f56SAlex Deucher 498a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 499a2e73f56SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 500a2e73f56SAlex Deucher ring->idx, i); 501a2e73f56SAlex Deucher } else { 502a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 503a2e73f56SAlex Deucher ring->idx, tmp); 504a2e73f56SAlex Deucher r = -EINVAL; 505a2e73f56SAlex Deucher } 506a2e73f56SAlex Deucher return r; 507a2e73f56SAlex Deucher } 508a2e73f56SAlex Deucher 509a2e73f56SAlex Deucher /** 510a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 511a2e73f56SAlex Deucher * 512a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 513a2e73f56SAlex Deucher * @ib: indirect buffer to execute 514a2e73f56SAlex Deucher * 515a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 516a2e73f56SAlex Deucher */ 517a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 518d88bf583SChristian König struct amdgpu_ib *ib, 519d88bf583SChristian König unsigned vm_id, bool ctx_switch) 520a2e73f56SAlex Deucher { 521a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 522a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 523a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 524a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 525a2e73f56SAlex Deucher } 526a2e73f56SAlex Deucher 527a2e73f56SAlex Deucher /** 528a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 529a2e73f56SAlex Deucher * 530a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 531a2e73f56SAlex Deucher * 532a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 533a2e73f56SAlex Deucher */ 534a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 535a2e73f56SAlex Deucher { 536a2e73f56SAlex Deucher uint64_t addr; 537a2e73f56SAlex Deucher uint32_t size; 538a2e73f56SAlex Deucher 539a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 540a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 541a2e73f56SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 542a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 543a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 544a2e73f56SAlex Deucher 545a2e73f56SAlex Deucher addr += size; 546c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 547a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 548a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 549a2e73f56SAlex Deucher 550a2e73f56SAlex Deucher addr += size; 551c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 552c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 553a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 554a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 555a2e73f56SAlex Deucher 556a2e73f56SAlex Deucher /* bits 28-31 */ 557a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 558a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 559a2e73f56SAlex Deucher 560a2e73f56SAlex Deucher /* bits 32-39 */ 561a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 562a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 563a2e73f56SAlex Deucher 56476ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 56576ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 56676ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 567a2e73f56SAlex Deucher } 568a2e73f56SAlex Deucher 569a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 570a2e73f56SAlex Deucher bool enable) 571a2e73f56SAlex Deucher { 572a2e73f56SAlex Deucher u32 orig, data; 573a2e73f56SAlex Deucher 574e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 575a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 576aa4747c0SRex Zhu data |= 0xfff; 577a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 578a2e73f56SAlex Deucher 579a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 580a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 581a2e73f56SAlex Deucher if (orig != data) 582a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 583a2e73f56SAlex Deucher } else { 584a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 585a2e73f56SAlex Deucher data &= ~0xfff; 586a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 587a2e73f56SAlex Deucher 588a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 589a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 590a2e73f56SAlex Deucher if (orig != data) 591a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 592a2e73f56SAlex Deucher } 593a2e73f56SAlex Deucher } 594a2e73f56SAlex Deucher 595a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 596a2e73f56SAlex Deucher bool sw_mode) 597a2e73f56SAlex Deucher { 598a2e73f56SAlex Deucher u32 tmp, tmp2; 599a2e73f56SAlex Deucher 600953618cfSRex Zhu WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 601953618cfSRex Zhu 602a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 603a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 604a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 605a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 606a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 607a2e73f56SAlex Deucher 608a2e73f56SAlex Deucher if (sw_mode) { 609a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 610a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 611a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 612a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 613a2e73f56SAlex Deucher } else { 614a2e73f56SAlex Deucher tmp |= 0x7ffff800; 615a2e73f56SAlex Deucher tmp2 = 0; 616a2e73f56SAlex Deucher } 617a2e73f56SAlex Deucher 618a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 619a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 620a2e73f56SAlex Deucher } 621a2e73f56SAlex Deucher 622a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 623a2e73f56SAlex Deucher { 624a2e73f56SAlex Deucher bool hw_mode = true; 625a2e73f56SAlex Deucher 626a2e73f56SAlex Deucher if (hw_mode) { 627a2e73f56SAlex Deucher uvd_v4_2_set_dcm(adev, false); 628a2e73f56SAlex Deucher } else { 629a2e73f56SAlex Deucher u32 tmp = RREG32(mmUVD_CGC_CTRL); 630a2e73f56SAlex Deucher tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 631a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 632a2e73f56SAlex Deucher } 633a2e73f56SAlex Deucher } 634a2e73f56SAlex Deucher 6355fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 636a2e73f56SAlex Deucher { 6375fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6385fc3aeebSyanyang1 639a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 640a2e73f56SAlex Deucher } 641a2e73f56SAlex Deucher 6425fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 643a2e73f56SAlex Deucher { 644a2e73f56SAlex Deucher unsigned i; 6455fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 646a2e73f56SAlex Deucher 647a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 648a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 649a2e73f56SAlex Deucher return 0; 650a2e73f56SAlex Deucher } 651a2e73f56SAlex Deucher return -ETIMEDOUT; 652a2e73f56SAlex Deucher } 653a2e73f56SAlex Deucher 6545fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 655a2e73f56SAlex Deucher { 6565fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6575fc3aeebSyanyang1 658a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 659a2e73f56SAlex Deucher 660a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 661a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 662a2e73f56SAlex Deucher mdelay(5); 663a2e73f56SAlex Deucher 664a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 665a2e73f56SAlex Deucher } 666a2e73f56SAlex Deucher 667a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 668a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 669a2e73f56SAlex Deucher unsigned type, 670a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 671a2e73f56SAlex Deucher { 672a2e73f56SAlex Deucher // TODO 673a2e73f56SAlex Deucher return 0; 674a2e73f56SAlex Deucher } 675a2e73f56SAlex Deucher 676a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 677a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 678a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 679a2e73f56SAlex Deucher { 680a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 681a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 682a2e73f56SAlex Deucher return 0; 683a2e73f56SAlex Deucher } 684a2e73f56SAlex Deucher 6855fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 6865fc3aeebSyanyang1 enum amd_clockgating_state state) 687a2e73f56SAlex Deucher { 688a2e73f56SAlex Deucher bool gate = false; 6895fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 690a2e73f56SAlex Deucher 6914be5097cSRex Zhu if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 6924be5097cSRex Zhu return 0; 6934be5097cSRex Zhu 694aa4747c0SRex Zhu if (state == AMD_CG_STATE_GATE) 695aa4747c0SRex Zhu gate = true; 696aa4747c0SRex Zhu 697a2e73f56SAlex Deucher uvd_v4_2_enable_mgcg(adev, gate); 698a2e73f56SAlex Deucher 699a2e73f56SAlex Deucher return 0; 700a2e73f56SAlex Deucher } 701a2e73f56SAlex Deucher 7025fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 7035fc3aeebSyanyang1 enum amd_powergating_state state) 704a2e73f56SAlex Deucher { 705a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 706a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 707a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 708a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 709a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 710a2e73f56SAlex Deucher * the smc and the hw blocks 711a2e73f56SAlex Deucher */ 7125fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7135fc3aeebSyanyang1 714e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 715b6df77fcSAlex Deucher return 0; 7165fc3aeebSyanyang1 7175fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 718a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 719a2e73f56SAlex Deucher return 0; 720a2e73f56SAlex Deucher } else { 721a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 722a2e73f56SAlex Deucher } 723a2e73f56SAlex Deucher } 724a2e73f56SAlex Deucher 725a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 72688a907d6STom St Denis .name = "uvd_v4_2", 727a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 728a2e73f56SAlex Deucher .late_init = NULL, 729a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 730a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 731a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 732a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 733a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 734a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 735a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 736a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 737a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 738a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 739a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 740a2e73f56SAlex Deucher }; 741a2e73f56SAlex Deucher 742a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 74321cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 74479887142SChristian König .align_mask = 0xf, 74579887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 746a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 747a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 748a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 749a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 750e12f3d7aSChristian König .emit_frame_size = 751e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_flush */ 752e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ 753e12f3d7aSChristian König 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 754e12f3d7aSChristian König .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 755a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 756a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 757d5b4e25dSChristian König .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, 758d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, 759a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 7608de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 761edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 7629e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 763c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 764c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 765a2e73f56SAlex Deucher }; 766a2e73f56SAlex Deucher 767a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 768a2e73f56SAlex Deucher { 769a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 770a2e73f56SAlex Deucher } 771a2e73f56SAlex Deucher 772a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 773a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 774a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 775a2e73f56SAlex Deucher }; 776a2e73f56SAlex Deucher 777a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 778a2e73f56SAlex Deucher { 779a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 780a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 781a2e73f56SAlex Deucher } 782a1255107SAlex Deucher 783a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 784a1255107SAlex Deucher { 785a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 786a1255107SAlex Deucher .major = 4, 787a1255107SAlex Deucher .minor = 2, 788a1255107SAlex Deucher .rev = 0, 789a1255107SAlex Deucher .funcs = &uvd_v4_2_ip_funcs, 790a1255107SAlex Deucher }; 791