1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37d5b4e25dSChristian König #include "bif/bif_4_1_d.h" 38d5b4e25dSChristian König 394be5097cSRex Zhu #include "smu/smu_7_0_1_d.h" 404be5097cSRex Zhu #include "smu/smu_7_0_1_sh_mask.h" 414be5097cSRex Zhu 42a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 44a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 45a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 46a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 47a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 48a2e73f56SAlex Deucher 49a2e73f56SAlex Deucher /** 50a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 51a2e73f56SAlex Deucher * 52a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 53a2e73f56SAlex Deucher * 54a2e73f56SAlex Deucher * Returns the current hardware read pointer 55a2e73f56SAlex Deucher */ 56a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 57a2e73f56SAlex Deucher { 58a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 59a2e73f56SAlex Deucher 60a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 61a2e73f56SAlex Deucher } 62a2e73f56SAlex Deucher 63a2e73f56SAlex Deucher /** 64a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 65a2e73f56SAlex Deucher * 66a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 67a2e73f56SAlex Deucher * 68a2e73f56SAlex Deucher * Returns the current hardware write pointer 69a2e73f56SAlex Deucher */ 70a2e73f56SAlex Deucher static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 71a2e73f56SAlex Deucher { 72a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 73a2e73f56SAlex Deucher 74a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 75a2e73f56SAlex Deucher } 76a2e73f56SAlex Deucher 77a2e73f56SAlex Deucher /** 78a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 79a2e73f56SAlex Deucher * 80a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 81a2e73f56SAlex Deucher * 82a2e73f56SAlex Deucher * Commits the write pointer to the hardware 83a2e73f56SAlex Deucher */ 84a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 85a2e73f56SAlex Deucher { 86a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 87a2e73f56SAlex Deucher 88a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 89a2e73f56SAlex Deucher } 90a2e73f56SAlex Deucher 915fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 92a2e73f56SAlex Deucher { 935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 945fc3aeebSyanyang1 95a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 96a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 97a2e73f56SAlex Deucher 98a2e73f56SAlex Deucher return 0; 99a2e73f56SAlex Deucher } 100a2e73f56SAlex Deucher 1015fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 102a2e73f56SAlex Deucher { 103a2e73f56SAlex Deucher struct amdgpu_ring *ring; 1045fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 105a2e73f56SAlex Deucher int r; 106a2e73f56SAlex Deucher 107a2e73f56SAlex Deucher /* UVD TRAP */ 108a2e73f56SAlex Deucher r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 109a2e73f56SAlex Deucher if (r) 110a2e73f56SAlex Deucher return r; 111a2e73f56SAlex Deucher 112a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 113a2e73f56SAlex Deucher if (r) 114a2e73f56SAlex Deucher return r; 115a2e73f56SAlex Deucher 116a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 117a2e73f56SAlex Deucher if (r) 118a2e73f56SAlex Deucher return r; 119a2e73f56SAlex Deucher 120a2e73f56SAlex Deucher ring = &adev->uvd.ring; 121a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 12279887142SChristian König r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 123a2e73f56SAlex Deucher 124a2e73f56SAlex Deucher return r; 125a2e73f56SAlex Deucher } 126a2e73f56SAlex Deucher 1275fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 128a2e73f56SAlex Deucher { 129a2e73f56SAlex Deucher int r; 1305fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 131a2e73f56SAlex Deucher 132a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 133a2e73f56SAlex Deucher if (r) 134a2e73f56SAlex Deucher return r; 135a2e73f56SAlex Deucher 136a2e73f56SAlex Deucher r = amdgpu_uvd_sw_fini(adev); 137a2e73f56SAlex Deucher if (r) 138a2e73f56SAlex Deucher return r; 139a2e73f56SAlex Deucher 140a2e73f56SAlex Deucher return r; 141a2e73f56SAlex Deucher } 142a2e73f56SAlex Deucher 143a2e73f56SAlex Deucher /** 144a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 145a2e73f56SAlex Deucher * 146a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 147a2e73f56SAlex Deucher * 148a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 149a2e73f56SAlex Deucher */ 1505fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 151a2e73f56SAlex Deucher { 1525fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 154a2e73f56SAlex Deucher uint32_t tmp; 155a2e73f56SAlex Deucher int r; 156a2e73f56SAlex Deucher 157a2e73f56SAlex Deucher /* raise clocks while booting up the VCPU */ 158a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 159a2e73f56SAlex Deucher 160a2e73f56SAlex Deucher r = uvd_v4_2_start(adev); 161a2e73f56SAlex Deucher if (r) 162a2e73f56SAlex Deucher goto done; 163a2e73f56SAlex Deucher 164a2e73f56SAlex Deucher ring->ready = true; 165a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 166a2e73f56SAlex Deucher if (r) { 167a2e73f56SAlex Deucher ring->ready = false; 168a2e73f56SAlex Deucher goto done; 169a2e73f56SAlex Deucher } 170a2e73f56SAlex Deucher 171a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 172a2e73f56SAlex Deucher if (r) { 173a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 174a2e73f56SAlex Deucher goto done; 175a2e73f56SAlex Deucher } 176a2e73f56SAlex Deucher 177a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 178a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 179a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 180a2e73f56SAlex Deucher 181a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 182a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 183a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 184a2e73f56SAlex Deucher 185a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 186a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 187a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 188a2e73f56SAlex Deucher 189a2e73f56SAlex Deucher /* Clear timeout status bits */ 190a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 191a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 192a2e73f56SAlex Deucher 193a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 194a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 195a2e73f56SAlex Deucher 196a27de35cSChristian König amdgpu_ring_commit(ring); 197a2e73f56SAlex Deucher 198a2e73f56SAlex Deucher done: 199a2e73f56SAlex Deucher /* lower clocks again */ 200a2e73f56SAlex Deucher amdgpu_asic_set_uvd_clocks(adev, 0, 0); 201a2e73f56SAlex Deucher 202a2e73f56SAlex Deucher if (!r) 203a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 204a2e73f56SAlex Deucher 205a2e73f56SAlex Deucher return r; 206a2e73f56SAlex Deucher } 207a2e73f56SAlex Deucher 208a2e73f56SAlex Deucher /** 209a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 210a2e73f56SAlex Deucher * 211a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 212a2e73f56SAlex Deucher * 213a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 214a2e73f56SAlex Deucher */ 2155fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 216a2e73f56SAlex Deucher { 2175fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 219a2e73f56SAlex Deucher 220a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 221a2e73f56SAlex Deucher ring->ready = false; 222a2e73f56SAlex Deucher 223a2e73f56SAlex Deucher return 0; 224a2e73f56SAlex Deucher } 225a2e73f56SAlex Deucher 2265fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 227a2e73f56SAlex Deucher { 228a2e73f56SAlex Deucher int r; 2295fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 230a2e73f56SAlex Deucher 2313f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 232a2e73f56SAlex Deucher if (r) 233a2e73f56SAlex Deucher return r; 234a2e73f56SAlex Deucher 2353f99dd81SLeo Liu r = amdgpu_uvd_suspend(adev); 236a2e73f56SAlex Deucher if (r) 237a2e73f56SAlex Deucher return r; 238a2e73f56SAlex Deucher 239a2e73f56SAlex Deucher return r; 240a2e73f56SAlex Deucher } 241a2e73f56SAlex Deucher 2425fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 243a2e73f56SAlex Deucher { 244a2e73f56SAlex Deucher int r; 2455fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 246a2e73f56SAlex Deucher 247a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 248a2e73f56SAlex Deucher if (r) 249a2e73f56SAlex Deucher return r; 250a2e73f56SAlex Deucher 251a2e73f56SAlex Deucher r = uvd_v4_2_hw_init(adev); 252a2e73f56SAlex Deucher if (r) 253a2e73f56SAlex Deucher return r; 254a2e73f56SAlex Deucher 255a2e73f56SAlex Deucher return r; 256a2e73f56SAlex Deucher } 257a2e73f56SAlex Deucher 258a2e73f56SAlex Deucher /** 259a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 260a2e73f56SAlex Deucher * 261a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 262a2e73f56SAlex Deucher * 263a2e73f56SAlex Deucher * Setup and start the UVD block 264a2e73f56SAlex Deucher */ 265a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 266a2e73f56SAlex Deucher { 267a2e73f56SAlex Deucher struct amdgpu_ring *ring = &adev->uvd.ring; 268a2e73f56SAlex Deucher uint32_t rb_bufsz; 269a2e73f56SAlex Deucher int i, j, r; 270a2e73f56SAlex Deucher 271a2e73f56SAlex Deucher /* disable byte swapping */ 272a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 273a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 274a2e73f56SAlex Deucher 275a2e73f56SAlex Deucher uvd_v4_2_mc_resume(adev); 276a2e73f56SAlex Deucher 277a2e73f56SAlex Deucher /* disable clock gating */ 278a2e73f56SAlex Deucher WREG32(mmUVD_CGC_GATE, 0); 279a2e73f56SAlex Deucher 280a2e73f56SAlex Deucher /* disable interupt */ 281a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 282a2e73f56SAlex Deucher 283a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 284a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 285a2e73f56SAlex Deucher mdelay(1); 286a2e73f56SAlex Deucher 287a2e73f56SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */ 288a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 289a2e73f56SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 290a2e73f56SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 291a2e73f56SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 292a2e73f56SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 293a2e73f56SAlex Deucher mdelay(5); 294a2e73f56SAlex Deucher 295a2e73f56SAlex Deucher /* take UVD block out of reset */ 296a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 297a2e73f56SAlex Deucher mdelay(5); 298a2e73f56SAlex Deucher 299a2e73f56SAlex Deucher /* initialize UVD memory controller */ 300a2e73f56SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 301a2e73f56SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20)); 302a2e73f56SAlex Deucher 303a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 304a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 305a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 306a2e73f56SAlex Deucher mp_swap_cntl = 0; 307a2e73f56SAlex Deucher #endif 308a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 309a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 310a2e73f56SAlex Deucher 311a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 312a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 313a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 314a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 315a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 316a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 317a2e73f56SAlex Deucher 318a2e73f56SAlex Deucher /* take all subblocks out of reset, except VCPU */ 319a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 320a2e73f56SAlex Deucher mdelay(5); 321a2e73f56SAlex Deucher 322a2e73f56SAlex Deucher /* enable VCPU clock */ 323a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9); 324a2e73f56SAlex Deucher 325a2e73f56SAlex Deucher /* enable UMC */ 326a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 327a2e73f56SAlex Deucher 328a2e73f56SAlex Deucher /* boot up the VCPU */ 329a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0); 330a2e73f56SAlex Deucher mdelay(10); 331a2e73f56SAlex Deucher 332a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 333a2e73f56SAlex Deucher uint32_t status; 334a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 335a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 336a2e73f56SAlex Deucher if (status & 2) 337a2e73f56SAlex Deucher break; 338a2e73f56SAlex Deucher mdelay(10); 339a2e73f56SAlex Deucher } 340a2e73f56SAlex Deucher r = 0; 341a2e73f56SAlex Deucher if (status & 2) 342a2e73f56SAlex Deucher break; 343a2e73f56SAlex Deucher 344a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 345a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 346a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 347a2e73f56SAlex Deucher mdelay(10); 348a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 349a2e73f56SAlex Deucher mdelay(10); 350a2e73f56SAlex Deucher r = -1; 351a2e73f56SAlex Deucher } 352a2e73f56SAlex Deucher 353a2e73f56SAlex Deucher if (r) { 354a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 355a2e73f56SAlex Deucher return r; 356a2e73f56SAlex Deucher } 357a2e73f56SAlex Deucher 358a2e73f56SAlex Deucher /* enable interupt */ 359a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 360a2e73f56SAlex Deucher 361a2e73f56SAlex Deucher /* force RBC into idle state */ 362a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 363a2e73f56SAlex Deucher 364a2e73f56SAlex Deucher /* Set the write pointer delay */ 365a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 366a2e73f56SAlex Deucher 367a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 368a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 369a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 370a2e73f56SAlex Deucher 371a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 372a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 373a2e73f56SAlex Deucher 374a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 375a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 376a2e73f56SAlex Deucher 377a2e73f56SAlex Deucher /* set the ring address */ 378a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 379a2e73f56SAlex Deucher 380a2e73f56SAlex Deucher /* Set ring buffer size */ 381a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 382a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 383a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 384a2e73f56SAlex Deucher 385a2e73f56SAlex Deucher return 0; 386a2e73f56SAlex Deucher } 387a2e73f56SAlex Deucher 388a2e73f56SAlex Deucher /** 389a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 390a2e73f56SAlex Deucher * 391a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 392a2e73f56SAlex Deucher * 393a2e73f56SAlex Deucher * stop the UVD block 394a2e73f56SAlex Deucher */ 395a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 396a2e73f56SAlex Deucher { 397a2e73f56SAlex Deucher /* force RBC into idle state */ 398a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 399a2e73f56SAlex Deucher 400a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 401a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 402a2e73f56SAlex Deucher mdelay(1); 403a2e73f56SAlex Deucher 404a2e73f56SAlex Deucher /* put VCPU into reset */ 405a2e73f56SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 406a2e73f56SAlex Deucher mdelay(5); 407a2e73f56SAlex Deucher 408a2e73f56SAlex Deucher /* disable VCPU clock */ 409a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0); 410a2e73f56SAlex Deucher 411a2e73f56SAlex Deucher /* Unstall UMC and register bus */ 412a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 413a2e73f56SAlex Deucher } 414a2e73f56SAlex Deucher 415a2e73f56SAlex Deucher /** 416a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 417a2e73f56SAlex Deucher * 418a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 419a2e73f56SAlex Deucher * @fence: fence to emit 420a2e73f56SAlex Deucher * 421a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 422a2e73f56SAlex Deucher */ 423a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 424890ee23fSChunming Zhou unsigned flags) 425a2e73f56SAlex Deucher { 426890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 427a2e73f56SAlex Deucher 428a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 429a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 430a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 431a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 432a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 433a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 434a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 435a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 436a2e73f56SAlex Deucher 437a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 438a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 439a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 440a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 441a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 442a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 443a2e73f56SAlex Deucher } 444a2e73f56SAlex Deucher 445a2e73f56SAlex Deucher /** 446d5b4e25dSChristian König * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush 447d5b4e25dSChristian König * 448d5b4e25dSChristian König * @ring: amdgpu_ring pointer 449d5b4e25dSChristian König * 450d5b4e25dSChristian König * Emits an hdp flush. 451d5b4e25dSChristian König */ 452d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 453d5b4e25dSChristian König { 454d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 455d5b4e25dSChristian König amdgpu_ring_write(ring, 0); 456d5b4e25dSChristian König } 457d5b4e25dSChristian König 458d5b4e25dSChristian König /** 459d5b4e25dSChristian König * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate 460d5b4e25dSChristian König * 461d5b4e25dSChristian König * @ring: amdgpu_ring pointer 462d5b4e25dSChristian König * 463d5b4e25dSChristian König * Emits an hdp invalidate. 464d5b4e25dSChristian König */ 465d5b4e25dSChristian König static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 466d5b4e25dSChristian König { 467d5b4e25dSChristian König amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 468d5b4e25dSChristian König amdgpu_ring_write(ring, 1); 469d5b4e25dSChristian König } 470d5b4e25dSChristian König 471d5b4e25dSChristian König /** 472a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 473a2e73f56SAlex Deucher * 474a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 475a2e73f56SAlex Deucher * 476a2e73f56SAlex Deucher * Test if we can successfully write to the context register 477a2e73f56SAlex Deucher */ 478a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 479a2e73f56SAlex Deucher { 480a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 481a2e73f56SAlex Deucher uint32_t tmp = 0; 482a2e73f56SAlex Deucher unsigned i; 483a2e73f56SAlex Deucher int r; 484a2e73f56SAlex Deucher 485a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 486a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 487a2e73f56SAlex Deucher if (r) { 488a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 489a2e73f56SAlex Deucher ring->idx, r); 490a2e73f56SAlex Deucher return r; 491a2e73f56SAlex Deucher } 492a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 493a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 494a27de35cSChristian König amdgpu_ring_commit(ring); 495a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 496a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 497a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 498a2e73f56SAlex Deucher break; 499a2e73f56SAlex Deucher DRM_UDELAY(1); 500a2e73f56SAlex Deucher } 501a2e73f56SAlex Deucher 502a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 503a2e73f56SAlex Deucher DRM_INFO("ring test on %d succeeded in %d usecs\n", 504a2e73f56SAlex Deucher ring->idx, i); 505a2e73f56SAlex Deucher } else { 506a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 507a2e73f56SAlex Deucher ring->idx, tmp); 508a2e73f56SAlex Deucher r = -EINVAL; 509a2e73f56SAlex Deucher } 510a2e73f56SAlex Deucher return r; 511a2e73f56SAlex Deucher } 512a2e73f56SAlex Deucher 513a2e73f56SAlex Deucher /** 514a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 515a2e73f56SAlex Deucher * 516a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 517a2e73f56SAlex Deucher * @ib: indirect buffer to execute 518a2e73f56SAlex Deucher * 519a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 520a2e73f56SAlex Deucher */ 521a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 522d88bf583SChristian König struct amdgpu_ib *ib, 523d88bf583SChristian König unsigned vm_id, bool ctx_switch) 524a2e73f56SAlex Deucher { 525a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 526a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 527a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 528a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 529a2e73f56SAlex Deucher } 530a2e73f56SAlex Deucher 531a2e73f56SAlex Deucher /** 532a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 533a2e73f56SAlex Deucher * 534a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 535a2e73f56SAlex Deucher * 536a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 537a2e73f56SAlex Deucher */ 538a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 539a2e73f56SAlex Deucher { 540a2e73f56SAlex Deucher uint64_t addr; 541a2e73f56SAlex Deucher uint32_t size; 542a2e73f56SAlex Deucher 543a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 544a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 545a2e73f56SAlex Deucher size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 546a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 547a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 548a2e73f56SAlex Deucher 549a2e73f56SAlex Deucher addr += size; 550c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 551a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 552a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 553a2e73f56SAlex Deucher 554a2e73f56SAlex Deucher addr += size; 555c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 556c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 557a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 558a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 559a2e73f56SAlex Deucher 560a2e73f56SAlex Deucher /* bits 28-31 */ 561a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 28) & 0xF; 562a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 563a2e73f56SAlex Deucher 564a2e73f56SAlex Deucher /* bits 32-39 */ 565a2e73f56SAlex Deucher addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 566a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 567a2e73f56SAlex Deucher 56876ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 56976ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 57076ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 57176ed6cb0SAlex Deucher 572a2e73f56SAlex Deucher uvd_v4_2_init_cg(adev); 573a2e73f56SAlex Deucher } 574a2e73f56SAlex Deucher 575a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 576a2e73f56SAlex Deucher bool enable) 577a2e73f56SAlex Deucher { 578a2e73f56SAlex Deucher u32 orig, data; 579a2e73f56SAlex Deucher 580e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 581a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 582a2e73f56SAlex Deucher data = 0xfff; 583a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 584a2e73f56SAlex Deucher 585a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 586a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 587a2e73f56SAlex Deucher if (orig != data) 588a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 589a2e73f56SAlex Deucher } else { 590a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 591a2e73f56SAlex Deucher data &= ~0xfff; 592a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 593a2e73f56SAlex Deucher 594a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 595a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 596a2e73f56SAlex Deucher if (orig != data) 597a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 598a2e73f56SAlex Deucher } 599a2e73f56SAlex Deucher } 600a2e73f56SAlex Deucher 601a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 602a2e73f56SAlex Deucher bool sw_mode) 603a2e73f56SAlex Deucher { 604a2e73f56SAlex Deucher u32 tmp, tmp2; 605a2e73f56SAlex Deucher 606a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 607a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 608a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 609a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 610a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 611a2e73f56SAlex Deucher 612a2e73f56SAlex Deucher if (sw_mode) { 613a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 614a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 615a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 616a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 617a2e73f56SAlex Deucher } else { 618a2e73f56SAlex Deucher tmp |= 0x7ffff800; 619a2e73f56SAlex Deucher tmp2 = 0; 620a2e73f56SAlex Deucher } 621a2e73f56SAlex Deucher 622a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 623a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 624a2e73f56SAlex Deucher } 625a2e73f56SAlex Deucher 626a2e73f56SAlex Deucher static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 627a2e73f56SAlex Deucher { 628a2e73f56SAlex Deucher bool hw_mode = true; 629a2e73f56SAlex Deucher 630a2e73f56SAlex Deucher if (hw_mode) { 631a2e73f56SAlex Deucher uvd_v4_2_set_dcm(adev, false); 632a2e73f56SAlex Deucher } else { 633a2e73f56SAlex Deucher u32 tmp = RREG32(mmUVD_CGC_CTRL); 634a2e73f56SAlex Deucher tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 635a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 636a2e73f56SAlex Deucher } 637a2e73f56SAlex Deucher } 638a2e73f56SAlex Deucher 6395fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 640a2e73f56SAlex Deucher { 6415fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6425fc3aeebSyanyang1 643a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 644a2e73f56SAlex Deucher } 645a2e73f56SAlex Deucher 6465fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 647a2e73f56SAlex Deucher { 648a2e73f56SAlex Deucher unsigned i; 6495fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 650a2e73f56SAlex Deucher 651a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 652a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 653a2e73f56SAlex Deucher return 0; 654a2e73f56SAlex Deucher } 655a2e73f56SAlex Deucher return -ETIMEDOUT; 656a2e73f56SAlex Deucher } 657a2e73f56SAlex Deucher 6585fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 659a2e73f56SAlex Deucher { 6605fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6615fc3aeebSyanyang1 662a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 663a2e73f56SAlex Deucher 664a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 665a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 666a2e73f56SAlex Deucher mdelay(5); 667a2e73f56SAlex Deucher 668a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 669a2e73f56SAlex Deucher } 670a2e73f56SAlex Deucher 671a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 672a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 673a2e73f56SAlex Deucher unsigned type, 674a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 675a2e73f56SAlex Deucher { 676a2e73f56SAlex Deucher // TODO 677a2e73f56SAlex Deucher return 0; 678a2e73f56SAlex Deucher } 679a2e73f56SAlex Deucher 680a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 681a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 682a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 683a2e73f56SAlex Deucher { 684a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 685a2e73f56SAlex Deucher amdgpu_fence_process(&adev->uvd.ring); 686a2e73f56SAlex Deucher return 0; 687a2e73f56SAlex Deucher } 688a2e73f56SAlex Deucher 6894be5097cSRex Zhu static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 6904be5097cSRex Zhu { 6914be5097cSRex Zhu u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 6924be5097cSRex Zhu 6934be5097cSRex Zhu if (enable) 6944be5097cSRex Zhu tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 6954be5097cSRex Zhu GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 6964be5097cSRex Zhu else 6974be5097cSRex Zhu tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 6984be5097cSRex Zhu GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 6994be5097cSRex Zhu 7004be5097cSRex Zhu WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 7014be5097cSRex Zhu } 7024be5097cSRex Zhu 7035fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 7045fc3aeebSyanyang1 enum amd_clockgating_state state) 705a2e73f56SAlex Deucher { 706a2e73f56SAlex Deucher bool gate = false; 7075fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 708a2e73f56SAlex Deucher 7095fc3aeebSyanyang1 if (state == AMD_CG_STATE_GATE) 710a2e73f56SAlex Deucher gate = true; 711a2e73f56SAlex Deucher 7124be5097cSRex Zhu uvd_v5_0_set_bypass_mode(adev, gate); 7134be5097cSRex Zhu 7144be5097cSRex Zhu if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 7154be5097cSRex Zhu return 0; 7164be5097cSRex Zhu 717a2e73f56SAlex Deucher uvd_v4_2_enable_mgcg(adev, gate); 718a2e73f56SAlex Deucher 719a2e73f56SAlex Deucher return 0; 720a2e73f56SAlex Deucher } 721a2e73f56SAlex Deucher 7225fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 7235fc3aeebSyanyang1 enum amd_powergating_state state) 724a2e73f56SAlex Deucher { 725a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 726a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 727a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 728a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 729a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 730a2e73f56SAlex Deucher * the smc and the hw blocks 731a2e73f56SAlex Deucher */ 7325fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7335fc3aeebSyanyang1 734e3b04bc7SAlex Deucher if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 735b6df77fcSAlex Deucher return 0; 7365fc3aeebSyanyang1 7375fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 738a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 739a2e73f56SAlex Deucher return 0; 740a2e73f56SAlex Deucher } else { 741a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 742a2e73f56SAlex Deucher } 743a2e73f56SAlex Deucher } 744a2e73f56SAlex Deucher 745a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 74688a907d6STom St Denis .name = "uvd_v4_2", 747a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 748a2e73f56SAlex Deucher .late_init = NULL, 749a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 750a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 751a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 752a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 753a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 754a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 755a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 756a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 757a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 758a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 759a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 760a2e73f56SAlex Deucher }; 761a2e73f56SAlex Deucher 762a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 76321cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 76479887142SChristian König .align_mask = 0xf, 76579887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 766a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 767a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 768a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 769a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 770e12f3d7aSChristian König .emit_frame_size = 771e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_flush */ 772e12f3d7aSChristian König 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ 773e12f3d7aSChristian König 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 774e12f3d7aSChristian König .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 775a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 776a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 777d5b4e25dSChristian König .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, 778d5b4e25dSChristian König .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, 779a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 7808de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 781edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 7829e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 783c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 784c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 785a2e73f56SAlex Deucher }; 786a2e73f56SAlex Deucher 787a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 788a2e73f56SAlex Deucher { 789a2e73f56SAlex Deucher adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 790a2e73f56SAlex Deucher } 791a2e73f56SAlex Deucher 792a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 793a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 794a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 795a2e73f56SAlex Deucher }; 796a2e73f56SAlex Deucher 797a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 798a2e73f56SAlex Deucher { 799a2e73f56SAlex Deucher adev->uvd.irq.num_types = 1; 800a2e73f56SAlex Deucher adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 801a2e73f56SAlex Deucher } 802a1255107SAlex Deucher 803a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 804a1255107SAlex Deucher { 805a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 806a1255107SAlex Deucher .major = 4, 807a1255107SAlex Deucher .minor = 2, 808a1255107SAlex Deucher .rev = 0, 809a1255107SAlex Deucher .funcs = &uvd_v4_2_ip_funcs, 810a1255107SAlex Deucher }; 811