1a2e73f56SAlex Deucher /* 2a2e73f56SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a2e73f56SAlex Deucher * 4a2e73f56SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a2e73f56SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a2e73f56SAlex Deucher * to deal in the Software without restriction, including without limitation 7a2e73f56SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a2e73f56SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a2e73f56SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a2e73f56SAlex Deucher * 11a2e73f56SAlex Deucher * The above copyright notice and this permission notice shall be included in 12a2e73f56SAlex Deucher * all copies or substantial portions of the Software. 13a2e73f56SAlex Deucher * 14a2e73f56SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a2e73f56SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a2e73f56SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a2e73f56SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a2e73f56SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a2e73f56SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a2e73f56SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a2e73f56SAlex Deucher * 22a2e73f56SAlex Deucher * Authors: Christian König <christian.koenig@amd.com> 23a2e73f56SAlex Deucher */ 24a2e73f56SAlex Deucher 25a2e73f56SAlex Deucher #include <linux/firmware.h> 26a2e73f56SAlex Deucher #include <drm/drmP.h> 27a2e73f56SAlex Deucher #include "amdgpu.h" 28a2e73f56SAlex Deucher #include "amdgpu_uvd.h" 29a2e73f56SAlex Deucher #include "cikd.h" 30a2e73f56SAlex Deucher 31a2e73f56SAlex Deucher #include "uvd/uvd_4_2_d.h" 32a2e73f56SAlex Deucher #include "uvd/uvd_4_2_sh_mask.h" 33a2e73f56SAlex Deucher 34a2e73f56SAlex Deucher #include "oss/oss_2_0_d.h" 35a2e73f56SAlex Deucher #include "oss/oss_2_0_sh_mask.h" 36a2e73f56SAlex Deucher 37d5b4e25dSChristian König #include "bif/bif_4_1_d.h" 38d5b4e25dSChristian König 394be5097cSRex Zhu #include "smu/smu_7_0_1_d.h" 404be5097cSRex Zhu #include "smu/smu_7_0_1_sh_mask.h" 414be5097cSRex Zhu 42a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 44a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev); 46a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev); 47aa4747c0SRex Zhu static int uvd_v4_2_set_clockgating_state(void *handle, 48aa4747c0SRex Zhu enum amd_clockgating_state state); 49ca581e45SRex Zhu static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 50ca581e45SRex Zhu bool sw_mode); 51a2e73f56SAlex Deucher /** 52a2e73f56SAlex Deucher * uvd_v4_2_ring_get_rptr - get read pointer 53a2e73f56SAlex Deucher * 54a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 55a2e73f56SAlex Deucher * 56a2e73f56SAlex Deucher * Returns the current hardware read pointer 57a2e73f56SAlex Deucher */ 58536fbf94SKen Wang static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 59a2e73f56SAlex Deucher { 60a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 61a2e73f56SAlex Deucher 62a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR); 63a2e73f56SAlex Deucher } 64a2e73f56SAlex Deucher 65a2e73f56SAlex Deucher /** 66a2e73f56SAlex Deucher * uvd_v4_2_ring_get_wptr - get write pointer 67a2e73f56SAlex Deucher * 68a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 69a2e73f56SAlex Deucher * 70a2e73f56SAlex Deucher * Returns the current hardware write pointer 71a2e73f56SAlex Deucher */ 72536fbf94SKen Wang static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 73a2e73f56SAlex Deucher { 74a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 75a2e73f56SAlex Deucher 76a2e73f56SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR); 77a2e73f56SAlex Deucher } 78a2e73f56SAlex Deucher 79a2e73f56SAlex Deucher /** 80a2e73f56SAlex Deucher * uvd_v4_2_ring_set_wptr - set write pointer 81a2e73f56SAlex Deucher * 82a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 83a2e73f56SAlex Deucher * 84a2e73f56SAlex Deucher * Commits the write pointer to the hardware 85a2e73f56SAlex Deucher */ 86a2e73f56SAlex Deucher static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 87a2e73f56SAlex Deucher { 88a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 89a2e73f56SAlex Deucher 90536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 91a2e73f56SAlex Deucher } 92a2e73f56SAlex Deucher 935fc3aeebSyanyang1 static int uvd_v4_2_early_init(void *handle) 94a2e73f56SAlex Deucher { 955fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 962bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1; 975fc3aeebSyanyang1 98a2e73f56SAlex Deucher uvd_v4_2_set_ring_funcs(adev); 99a2e73f56SAlex Deucher uvd_v4_2_set_irq_funcs(adev); 100a2e73f56SAlex Deucher 101a2e73f56SAlex Deucher return 0; 102a2e73f56SAlex Deucher } 103a2e73f56SAlex Deucher 1045fc3aeebSyanyang1 static int uvd_v4_2_sw_init(void *handle) 105a2e73f56SAlex Deucher { 106a2e73f56SAlex Deucher struct amdgpu_ring *ring; 1075fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 108a2e73f56SAlex Deucher int r; 109a2e73f56SAlex Deucher 110a2e73f56SAlex Deucher /* UVD TRAP */ 1112bb795f5SJames Zhu r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 112a2e73f56SAlex Deucher if (r) 113a2e73f56SAlex Deucher return r; 114a2e73f56SAlex Deucher 115a2e73f56SAlex Deucher r = amdgpu_uvd_sw_init(adev); 116a2e73f56SAlex Deucher if (r) 117a2e73f56SAlex Deucher return r; 118a2e73f56SAlex Deucher 119a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 120a2e73f56SAlex Deucher if (r) 121a2e73f56SAlex Deucher return r; 122a2e73f56SAlex Deucher 1232bb795f5SJames Zhu ring = &adev->uvd.inst->ring; 124a2e73f56SAlex Deucher sprintf(ring->name, "uvd"); 1252bb795f5SJames Zhu r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 126a2e73f56SAlex Deucher 127a2e73f56SAlex Deucher return r; 128a2e73f56SAlex Deucher } 129a2e73f56SAlex Deucher 1305fc3aeebSyanyang1 static int uvd_v4_2_sw_fini(void *handle) 131a2e73f56SAlex Deucher { 132a2e73f56SAlex Deucher int r; 1335fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 134a2e73f56SAlex Deucher 135a2e73f56SAlex Deucher r = amdgpu_uvd_suspend(adev); 136a2e73f56SAlex Deucher if (r) 137a2e73f56SAlex Deucher return r; 138a2e73f56SAlex Deucher 13950237287SRex Zhu return amdgpu_uvd_sw_fini(adev); 140a2e73f56SAlex Deucher } 14150237287SRex Zhu 142ca581e45SRex Zhu static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 143ca581e45SRex Zhu bool enable); 144a2e73f56SAlex Deucher /** 145a2e73f56SAlex Deucher * uvd_v4_2_hw_init - start and test UVD block 146a2e73f56SAlex Deucher * 147a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 148a2e73f56SAlex Deucher * 149a2e73f56SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing 150a2e73f56SAlex Deucher */ 1515fc3aeebSyanyang1 static int uvd_v4_2_hw_init(void *handle) 152a2e73f56SAlex Deucher { 1535fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1542bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 155a2e73f56SAlex Deucher uint32_t tmp; 156a2e73f56SAlex Deucher int r; 157a2e73f56SAlex Deucher 158ca581e45SRex Zhu uvd_v4_2_enable_mgcg(adev, true); 159aa4747c0SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 160a2e73f56SAlex Deucher 161a2e73f56SAlex Deucher ring->ready = true; 162a2e73f56SAlex Deucher r = amdgpu_ring_test_ring(ring); 163a2e73f56SAlex Deucher if (r) { 164a2e73f56SAlex Deucher ring->ready = false; 165a2e73f56SAlex Deucher goto done; 166a2e73f56SAlex Deucher } 167a2e73f56SAlex Deucher 168a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10); 169a2e73f56SAlex Deucher if (r) { 170a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 171a2e73f56SAlex Deucher goto done; 172a2e73f56SAlex Deucher } 173a2e73f56SAlex Deucher 174a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 175a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 176a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 177a2e73f56SAlex Deucher 178a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 179a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 180a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 181a2e73f56SAlex Deucher 182a2e73f56SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 183a2e73f56SAlex Deucher amdgpu_ring_write(ring, tmp); 184a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF); 185a2e73f56SAlex Deucher 186a2e73f56SAlex Deucher /* Clear timeout status bits */ 187a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 188a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0x8); 189a2e73f56SAlex Deucher 190a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 191a2e73f56SAlex Deucher amdgpu_ring_write(ring, 3); 192a2e73f56SAlex Deucher 193a27de35cSChristian König amdgpu_ring_commit(ring); 194a2e73f56SAlex Deucher 195a2e73f56SAlex Deucher done: 196a2e73f56SAlex Deucher if (!r) 197a2e73f56SAlex Deucher DRM_INFO("UVD initialized successfully.\n"); 198a2e73f56SAlex Deucher 199a2e73f56SAlex Deucher return r; 200a2e73f56SAlex Deucher } 201a2e73f56SAlex Deucher 202a2e73f56SAlex Deucher /** 203a2e73f56SAlex Deucher * uvd_v4_2_hw_fini - stop the hardware block 204a2e73f56SAlex Deucher * 205a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 206a2e73f56SAlex Deucher * 207a2e73f56SAlex Deucher * Stop the UVD block, mark ring as not ready any more 208a2e73f56SAlex Deucher */ 2095fc3aeebSyanyang1 static int uvd_v4_2_hw_fini(void *handle) 210a2e73f56SAlex Deucher { 2115fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2122bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 213a2e73f56SAlex Deucher 2148b55d17eSRex Zhu if (RREG32(mmUVD_STATUS) != 0) 215a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 2168b55d17eSRex Zhu 217a2e73f56SAlex Deucher ring->ready = false; 218a2e73f56SAlex Deucher 219a2e73f56SAlex Deucher return 0; 220a2e73f56SAlex Deucher } 221a2e73f56SAlex Deucher 2225fc3aeebSyanyang1 static int uvd_v4_2_suspend(void *handle) 223a2e73f56SAlex Deucher { 224a2e73f56SAlex Deucher int r; 2255fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226a2e73f56SAlex Deucher 2273f99dd81SLeo Liu r = uvd_v4_2_hw_fini(adev); 228a2e73f56SAlex Deucher if (r) 229a2e73f56SAlex Deucher return r; 230a2e73f56SAlex Deucher 23150237287SRex Zhu return amdgpu_uvd_suspend(adev); 232a2e73f56SAlex Deucher } 233a2e73f56SAlex Deucher 2345fc3aeebSyanyang1 static int uvd_v4_2_resume(void *handle) 235a2e73f56SAlex Deucher { 236a2e73f56SAlex Deucher int r; 2375fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238a2e73f56SAlex Deucher 239a2e73f56SAlex Deucher r = amdgpu_uvd_resume(adev); 240a2e73f56SAlex Deucher if (r) 241a2e73f56SAlex Deucher return r; 242a2e73f56SAlex Deucher 24350237287SRex Zhu return uvd_v4_2_hw_init(adev); 244a2e73f56SAlex Deucher } 245a2e73f56SAlex Deucher 246a2e73f56SAlex Deucher /** 247a2e73f56SAlex Deucher * uvd_v4_2_start - start UVD block 248a2e73f56SAlex Deucher * 249a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 250a2e73f56SAlex Deucher * 251a2e73f56SAlex Deucher * Setup and start the UVD block 252a2e73f56SAlex Deucher */ 253a2e73f56SAlex Deucher static int uvd_v4_2_start(struct amdgpu_device *adev) 254a2e73f56SAlex Deucher { 2552bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring; 256a2e73f56SAlex Deucher uint32_t rb_bufsz; 257a2e73f56SAlex Deucher int i, j, r; 2588b55d17eSRex Zhu u32 tmp; 259a2e73f56SAlex Deucher /* disable byte swapping */ 260a2e73f56SAlex Deucher u32 lmi_swap_cntl = 0; 261a2e73f56SAlex Deucher u32 mp_swap_cntl = 0; 262a2e73f56SAlex Deucher 2638b55d17eSRex Zhu /* set uvd busy */ 2648b55d17eSRex Zhu WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); 2658b55d17eSRex Zhu 266ca581e45SRex Zhu uvd_v4_2_set_dcm(adev, true); 2678b55d17eSRex Zhu WREG32(mmUVD_CGC_GATE, 0); 268a2e73f56SAlex Deucher 269a2e73f56SAlex Deucher /* take UVD block out of reset */ 270a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 271a2e73f56SAlex Deucher mdelay(5); 272a2e73f56SAlex Deucher 2738b55d17eSRex Zhu /* enable VCPU clock */ 2748b55d17eSRex Zhu WREG32(mmUVD_VCPU_CNTL, 1 << 9); 2758b55d17eSRex Zhu 2768b55d17eSRex Zhu /* disable interupt */ 2778b55d17eSRex Zhu WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 278a2e73f56SAlex Deucher 279a2e73f56SAlex Deucher #ifdef __BIG_ENDIAN 280a2e73f56SAlex Deucher /* swap (8 in 32) RB and IB */ 281a2e73f56SAlex Deucher lmi_swap_cntl = 0xa; 282a2e73f56SAlex Deucher mp_swap_cntl = 0; 283a2e73f56SAlex Deucher #endif 284a2e73f56SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 285a2e73f56SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 2868b55d17eSRex Zhu /* initialize UVD memory controller */ 2878b55d17eSRex Zhu WREG32(mmUVD_LMI_CTRL, 0x203108); 2888b55d17eSRex Zhu 2898b55d17eSRex Zhu tmp = RREG32(mmUVD_MPC_CNTL); 2908b55d17eSRex Zhu WREG32(mmUVD_MPC_CNTL, tmp | 0x10); 291a2e73f56SAlex Deucher 292a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 293a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 294a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 295a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 296a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0); 297a2e73f56SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88); 298a2e73f56SAlex Deucher 2998b55d17eSRex Zhu uvd_v4_2_mc_resume(adev); 300a2e73f56SAlex Deucher 3018b55d17eSRex Zhu tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); 3028b55d17eSRex Zhu WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); 303a2e73f56SAlex Deucher 304a2e73f56SAlex Deucher /* enable UMC */ 305a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 306a2e73f56SAlex Deucher 3078b55d17eSRex Zhu WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 3088b55d17eSRex Zhu 3098b55d17eSRex Zhu WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 3108b55d17eSRex Zhu 3118b55d17eSRex Zhu WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 3128b55d17eSRex Zhu 313a2e73f56SAlex Deucher mdelay(10); 314a2e73f56SAlex Deucher 315a2e73f56SAlex Deucher for (i = 0; i < 10; ++i) { 316a2e73f56SAlex Deucher uint32_t status; 317a2e73f56SAlex Deucher for (j = 0; j < 100; ++j) { 318a2e73f56SAlex Deucher status = RREG32(mmUVD_STATUS); 319a2e73f56SAlex Deucher if (status & 2) 320a2e73f56SAlex Deucher break; 321a2e73f56SAlex Deucher mdelay(10); 322a2e73f56SAlex Deucher } 323a2e73f56SAlex Deucher r = 0; 324a2e73f56SAlex Deucher if (status & 2) 325a2e73f56SAlex Deucher break; 326a2e73f56SAlex Deucher 327a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 328a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 329a2e73f56SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 330a2e73f56SAlex Deucher mdelay(10); 331a2e73f56SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 332a2e73f56SAlex Deucher mdelay(10); 333a2e73f56SAlex Deucher r = -1; 334a2e73f56SAlex Deucher } 335a2e73f56SAlex Deucher 336a2e73f56SAlex Deucher if (r) { 337a2e73f56SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n"); 338a2e73f56SAlex Deucher return r; 339a2e73f56SAlex Deucher } 340a2e73f56SAlex Deucher 341a2e73f56SAlex Deucher /* enable interupt */ 342a2e73f56SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 343a2e73f56SAlex Deucher 3448b55d17eSRex Zhu WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); 3458b55d17eSRex Zhu 346a2e73f56SAlex Deucher /* force RBC into idle state */ 347a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 348a2e73f56SAlex Deucher 349a2e73f56SAlex Deucher /* Set the write pointer delay */ 350a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 351a2e73f56SAlex Deucher 352a2e73f56SAlex Deucher /* programm the 4GB memory segment for rptr and ring buffer */ 353a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 354a2e73f56SAlex Deucher (0x7 << 16) | (0x1 << 31)); 355a2e73f56SAlex Deucher 356a2e73f56SAlex Deucher /* Initialize the ring buffer's read and write pointers */ 357a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0x0); 358a2e73f56SAlex Deucher 359a2e73f56SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 360536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 361a2e73f56SAlex Deucher 362a2e73f56SAlex Deucher /* set the ring address */ 363a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 364a2e73f56SAlex Deucher 365a2e73f56SAlex Deucher /* Set ring buffer size */ 366a2e73f56SAlex Deucher rb_bufsz = order_base_2(ring->ring_size); 367a2e73f56SAlex Deucher rb_bufsz = (0x1 << 8) | rb_bufsz; 368a2e73f56SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 369a2e73f56SAlex Deucher 370a2e73f56SAlex Deucher return 0; 371a2e73f56SAlex Deucher } 372a2e73f56SAlex Deucher 373a2e73f56SAlex Deucher /** 374a2e73f56SAlex Deucher * uvd_v4_2_stop - stop UVD block 375a2e73f56SAlex Deucher * 376a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 377a2e73f56SAlex Deucher * 378a2e73f56SAlex Deucher * stop the UVD block 379a2e73f56SAlex Deucher */ 380a2e73f56SAlex Deucher static void uvd_v4_2_stop(struct amdgpu_device *adev) 381a2e73f56SAlex Deucher { 3828b55d17eSRex Zhu uint32_t i, j; 3838b55d17eSRex Zhu uint32_t status; 3848b55d17eSRex Zhu 385a2e73f56SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 386a2e73f56SAlex Deucher 3878b55d17eSRex Zhu for (i = 0; i < 10; ++i) { 3888b55d17eSRex Zhu for (j = 0; j < 100; ++j) { 3898b55d17eSRex Zhu status = RREG32(mmUVD_STATUS); 3908b55d17eSRex Zhu if (status & 2) 3918b55d17eSRex Zhu break; 3928b55d17eSRex Zhu mdelay(1); 3938b55d17eSRex Zhu } 394e89d5b5cSTom St Denis if (status & 2) 3958b55d17eSRex Zhu break; 3968b55d17eSRex Zhu } 3978b55d17eSRex Zhu 3988b55d17eSRex Zhu for (i = 0; i < 10; ++i) { 3998b55d17eSRex Zhu for (j = 0; j < 100; ++j) { 4008b55d17eSRex Zhu status = RREG32(mmUVD_LMI_STATUS); 4018b55d17eSRex Zhu if (status & 0xf) 4028b55d17eSRex Zhu break; 4038b55d17eSRex Zhu mdelay(1); 4048b55d17eSRex Zhu } 405e89d5b5cSTom St Denis if (status & 0xf) 4068b55d17eSRex Zhu break; 4078b55d17eSRex Zhu } 4088b55d17eSRex Zhu 409a2e73f56SAlex Deucher /* Stall UMC and register bus before resetting VCPU */ 410a2e73f56SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 4118b55d17eSRex Zhu 4128b55d17eSRex Zhu for (i = 0; i < 10; ++i) { 4138b55d17eSRex Zhu for (j = 0; j < 100; ++j) { 4148b55d17eSRex Zhu status = RREG32(mmUVD_LMI_STATUS); 4158b55d17eSRex Zhu if (status & 0x240) 4168b55d17eSRex Zhu break; 417a2e73f56SAlex Deucher mdelay(1); 4188b55d17eSRex Zhu } 419e89d5b5cSTom St Denis if (status & 0x240) 4208b55d17eSRex Zhu break; 4218b55d17eSRex Zhu } 422a2e73f56SAlex Deucher 4238b55d17eSRex Zhu WREG32_P(0x3D49, 0, ~(1 << 2)); 424a2e73f56SAlex Deucher 4258b55d17eSRex Zhu WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); 426a2e73f56SAlex Deucher 4278b55d17eSRex Zhu /* put LMI, VCPU, RBC etc... into reset */ 4288b55d17eSRex Zhu WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 4298b55d17eSRex Zhu UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 4308b55d17eSRex Zhu UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 4318b55d17eSRex Zhu 4328b55d17eSRex Zhu WREG32(mmUVD_STATUS, 0); 433ca581e45SRex Zhu 434ca581e45SRex Zhu uvd_v4_2_set_dcm(adev, false); 435a2e73f56SAlex Deucher } 436a2e73f56SAlex Deucher 437a2e73f56SAlex Deucher /** 438a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_fence - emit an fence & trap command 439a2e73f56SAlex Deucher * 440a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 441a2e73f56SAlex Deucher * @fence: fence to emit 442a2e73f56SAlex Deucher * 443a2e73f56SAlex Deucher * Write a fence and a trap command to the ring. 444a2e73f56SAlex Deucher */ 445a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 446890ee23fSChunming Zhou unsigned flags) 447a2e73f56SAlex Deucher { 448890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 449a2e73f56SAlex Deucher 450a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 451a2e73f56SAlex Deucher amdgpu_ring_write(ring, seq); 452a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 453a2e73f56SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff); 454a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 455a2e73f56SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 456a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 457a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 458a2e73f56SAlex Deucher 459a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 460a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 461a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 462a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0); 463a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 464a2e73f56SAlex Deucher amdgpu_ring_write(ring, 2); 465a2e73f56SAlex Deucher } 466a2e73f56SAlex Deucher 467a2e73f56SAlex Deucher /** 468a2e73f56SAlex Deucher * uvd_v4_2_ring_test_ring - register write test 469a2e73f56SAlex Deucher * 470a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 471a2e73f56SAlex Deucher * 472a2e73f56SAlex Deucher * Test if we can successfully write to the context register 473a2e73f56SAlex Deucher */ 474a2e73f56SAlex Deucher static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 475a2e73f56SAlex Deucher { 476a2e73f56SAlex Deucher struct amdgpu_device *adev = ring->adev; 477a2e73f56SAlex Deucher uint32_t tmp = 0; 478a2e73f56SAlex Deucher unsigned i; 479a2e73f56SAlex Deucher int r; 480a2e73f56SAlex Deucher 481a2e73f56SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 482a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3); 483a2e73f56SAlex Deucher if (r) { 484a2e73f56SAlex Deucher DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 485a2e73f56SAlex Deucher ring->idx, r); 486a2e73f56SAlex Deucher return r; 487a2e73f56SAlex Deucher } 488a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 489a2e73f56SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF); 490a27de35cSChristian König amdgpu_ring_commit(ring); 491a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 492a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID); 493a2e73f56SAlex Deucher if (tmp == 0xDEADBEEF) 494a2e73f56SAlex Deucher break; 495a2e73f56SAlex Deucher DRM_UDELAY(1); 496a2e73f56SAlex Deucher } 497a2e73f56SAlex Deucher 498a2e73f56SAlex Deucher if (i < adev->usec_timeout) { 4999953b72fSpding DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 500a2e73f56SAlex Deucher ring->idx, i); 501a2e73f56SAlex Deucher } else { 502a2e73f56SAlex Deucher DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 503a2e73f56SAlex Deucher ring->idx, tmp); 504a2e73f56SAlex Deucher r = -EINVAL; 505a2e73f56SAlex Deucher } 506a2e73f56SAlex Deucher return r; 507a2e73f56SAlex Deucher } 508a2e73f56SAlex Deucher 509a2e73f56SAlex Deucher /** 510a2e73f56SAlex Deucher * uvd_v4_2_ring_emit_ib - execute indirect buffer 511a2e73f56SAlex Deucher * 512a2e73f56SAlex Deucher * @ring: amdgpu_ring pointer 513a2e73f56SAlex Deucher * @ib: indirect buffer to execute 514a2e73f56SAlex Deucher * 515a2e73f56SAlex Deucher * Write ring commands to execute the indirect buffer 516a2e73f56SAlex Deucher */ 517a2e73f56SAlex Deucher static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 518d88bf583SChristian König struct amdgpu_ib *ib, 519c4f46f22SChristian König unsigned vmid, bool ctx_switch) 520a2e73f56SAlex Deucher { 521a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 522a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->gpu_addr); 523a2e73f56SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 524a2e73f56SAlex Deucher amdgpu_ring_write(ring, ib->length_dw); 525a2e73f56SAlex Deucher } 526a2e73f56SAlex Deucher 527a2e73f56SAlex Deucher /** 528a2e73f56SAlex Deucher * uvd_v4_2_mc_resume - memory controller programming 529a2e73f56SAlex Deucher * 530a2e73f56SAlex Deucher * @adev: amdgpu_device pointer 531a2e73f56SAlex Deucher * 532a2e73f56SAlex Deucher * Let the UVD memory controller know it's offsets 533a2e73f56SAlex Deucher */ 534a2e73f56SAlex Deucher static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 535a2e73f56SAlex Deucher { 536a2e73f56SAlex Deucher uint64_t addr; 537a2e73f56SAlex Deucher uint32_t size; 538a2e73f56SAlex Deucher 539a2e73f56SAlex Deucher /* programm the VCPU memory controller bits 0-27 */ 5402bb795f5SJames Zhu addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 541c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; 542a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 543a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 544a2e73f56SAlex Deucher 545a2e73f56SAlex Deucher addr += size; 546c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE >> 3; 547a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 548a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 549a2e73f56SAlex Deucher 550a2e73f56SAlex Deucher addr += size; 551c0365541SArindam Nath size = (AMDGPU_UVD_STACK_SIZE + 552c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 553a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 554a2e73f56SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 555a2e73f56SAlex Deucher 556a2e73f56SAlex Deucher /* bits 28-31 */ 5572bb795f5SJames Zhu addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; 558a2e73f56SAlex Deucher WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 559a2e73f56SAlex Deucher 560a2e73f56SAlex Deucher /* bits 32-39 */ 5612bb795f5SJames Zhu addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; 562a2e73f56SAlex Deucher WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 563a2e73f56SAlex Deucher 56476ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 56576ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 56676ed6cb0SAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 567a2e73f56SAlex Deucher } 568a2e73f56SAlex Deucher 569a2e73f56SAlex Deucher static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 570a2e73f56SAlex Deucher bool enable) 571a2e73f56SAlex Deucher { 572a2e73f56SAlex Deucher u32 orig, data; 573a2e73f56SAlex Deucher 574e3b04bc7SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 575a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 576aa4747c0SRex Zhu data |= 0xfff; 577a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 578a2e73f56SAlex Deucher 579a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 580a2e73f56SAlex Deucher data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 581a2e73f56SAlex Deucher if (orig != data) 582a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 583a2e73f56SAlex Deucher } else { 584a2e73f56SAlex Deucher data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 585a2e73f56SAlex Deucher data &= ~0xfff; 586a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 587a2e73f56SAlex Deucher 588a2e73f56SAlex Deucher orig = data = RREG32(mmUVD_CGC_CTRL); 589a2e73f56SAlex Deucher data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 590a2e73f56SAlex Deucher if (orig != data) 591a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, data); 592a2e73f56SAlex Deucher } 593a2e73f56SAlex Deucher } 594a2e73f56SAlex Deucher 595a2e73f56SAlex Deucher static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 596a2e73f56SAlex Deucher bool sw_mode) 597a2e73f56SAlex Deucher { 598a2e73f56SAlex Deucher u32 tmp, tmp2; 599a2e73f56SAlex Deucher 600953618cfSRex Zhu WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 601953618cfSRex Zhu 602a2e73f56SAlex Deucher tmp = RREG32(mmUVD_CGC_CTRL); 603a2e73f56SAlex Deucher tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 604a2e73f56SAlex Deucher tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 605a2e73f56SAlex Deucher (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 606a2e73f56SAlex Deucher (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 607a2e73f56SAlex Deucher 608a2e73f56SAlex Deucher if (sw_mode) { 609a2e73f56SAlex Deucher tmp &= ~0x7ffff800; 610a2e73f56SAlex Deucher tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 611a2e73f56SAlex Deucher UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 612a2e73f56SAlex Deucher (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 613a2e73f56SAlex Deucher } else { 614a2e73f56SAlex Deucher tmp |= 0x7ffff800; 615a2e73f56SAlex Deucher tmp2 = 0; 616a2e73f56SAlex Deucher } 617a2e73f56SAlex Deucher 618a2e73f56SAlex Deucher WREG32(mmUVD_CGC_CTRL, tmp); 619a2e73f56SAlex Deucher WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 620a2e73f56SAlex Deucher } 621a2e73f56SAlex Deucher 6225fc3aeebSyanyang1 static bool uvd_v4_2_is_idle(void *handle) 623a2e73f56SAlex Deucher { 6245fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6255fc3aeebSyanyang1 626a2e73f56SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 627a2e73f56SAlex Deucher } 628a2e73f56SAlex Deucher 6295fc3aeebSyanyang1 static int uvd_v4_2_wait_for_idle(void *handle) 630a2e73f56SAlex Deucher { 631a2e73f56SAlex Deucher unsigned i; 6325fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633a2e73f56SAlex Deucher 634a2e73f56SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 635a2e73f56SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 636a2e73f56SAlex Deucher return 0; 637a2e73f56SAlex Deucher } 638a2e73f56SAlex Deucher return -ETIMEDOUT; 639a2e73f56SAlex Deucher } 640a2e73f56SAlex Deucher 6415fc3aeebSyanyang1 static int uvd_v4_2_soft_reset(void *handle) 642a2e73f56SAlex Deucher { 6435fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6445fc3aeebSyanyang1 645a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 646a2e73f56SAlex Deucher 647a2e73f56SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 648a2e73f56SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 649a2e73f56SAlex Deucher mdelay(5); 650a2e73f56SAlex Deucher 651a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 652a2e73f56SAlex Deucher } 653a2e73f56SAlex Deucher 654a2e73f56SAlex Deucher static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 655a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 656a2e73f56SAlex Deucher unsigned type, 657a2e73f56SAlex Deucher enum amdgpu_interrupt_state state) 658a2e73f56SAlex Deucher { 659a2e73f56SAlex Deucher // TODO 660a2e73f56SAlex Deucher return 0; 661a2e73f56SAlex Deucher } 662a2e73f56SAlex Deucher 663a2e73f56SAlex Deucher static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 664a2e73f56SAlex Deucher struct amdgpu_irq_src *source, 665a2e73f56SAlex Deucher struct amdgpu_iv_entry *entry) 666a2e73f56SAlex Deucher { 667a2e73f56SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n"); 6682bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring); 669a2e73f56SAlex Deucher return 0; 670a2e73f56SAlex Deucher } 671a2e73f56SAlex Deucher 6725fc3aeebSyanyang1 static int uvd_v4_2_set_clockgating_state(void *handle, 6735fc3aeebSyanyang1 enum amd_clockgating_state state) 674a2e73f56SAlex Deucher { 675a2e73f56SAlex Deucher return 0; 676a2e73f56SAlex Deucher } 677a2e73f56SAlex Deucher 6785fc3aeebSyanyang1 static int uvd_v4_2_set_powergating_state(void *handle, 6795fc3aeebSyanyang1 enum amd_powergating_state state) 680a2e73f56SAlex Deucher { 681a2e73f56SAlex Deucher /* This doesn't actually powergate the UVD block. 682a2e73f56SAlex Deucher * That's done in the dpm code via the SMC. This 683a2e73f56SAlex Deucher * just re-inits the block as necessary. The actual 684a2e73f56SAlex Deucher * gating still happens in the dpm code. We should 685a2e73f56SAlex Deucher * revisit this when there is a cleaner line between 686a2e73f56SAlex Deucher * the smc and the hw blocks 687a2e73f56SAlex Deucher */ 6885fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6895fc3aeebSyanyang1 6905fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) { 691a2e73f56SAlex Deucher uvd_v4_2_stop(adev); 692b13aa109SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 693254cd2e0SRex Zhu if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 694254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) { 6953a786966SRex Zhu WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 6963a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 6973a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 6983a786966SRex Zhu mdelay(20); 6993a786966SRex Zhu } 7003a786966SRex Zhu } 701a2e73f56SAlex Deucher return 0; 702a2e73f56SAlex Deucher } else { 703b13aa109SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 704254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) & 705254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 7063a786966SRex Zhu WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 7073a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 7083a786966SRex Zhu UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 7093a786966SRex Zhu mdelay(30); 7103a786966SRex Zhu } 7113a786966SRex Zhu } 712a2e73f56SAlex Deucher return uvd_v4_2_start(adev); 713a2e73f56SAlex Deucher } 714a2e73f56SAlex Deucher } 715a2e73f56SAlex Deucher 716a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 71788a907d6STom St Denis .name = "uvd_v4_2", 718a2e73f56SAlex Deucher .early_init = uvd_v4_2_early_init, 719a2e73f56SAlex Deucher .late_init = NULL, 720a2e73f56SAlex Deucher .sw_init = uvd_v4_2_sw_init, 721a2e73f56SAlex Deucher .sw_fini = uvd_v4_2_sw_fini, 722a2e73f56SAlex Deucher .hw_init = uvd_v4_2_hw_init, 723a2e73f56SAlex Deucher .hw_fini = uvd_v4_2_hw_fini, 724a2e73f56SAlex Deucher .suspend = uvd_v4_2_suspend, 725a2e73f56SAlex Deucher .resume = uvd_v4_2_resume, 726a2e73f56SAlex Deucher .is_idle = uvd_v4_2_is_idle, 727a2e73f56SAlex Deucher .wait_for_idle = uvd_v4_2_wait_for_idle, 728a2e73f56SAlex Deucher .soft_reset = uvd_v4_2_soft_reset, 729a2e73f56SAlex Deucher .set_clockgating_state = uvd_v4_2_set_clockgating_state, 730a2e73f56SAlex Deucher .set_powergating_state = uvd_v4_2_set_powergating_state, 731a2e73f56SAlex Deucher }; 732a2e73f56SAlex Deucher 733a2e73f56SAlex Deucher static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 73421cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD, 73579887142SChristian König .align_mask = 0xf, 73679887142SChristian König .nop = PACKET0(mmUVD_NO_OP, 0), 737536fbf94SKen Wang .support_64bit_ptrs = false, 738a2e73f56SAlex Deucher .get_rptr = uvd_v4_2_ring_get_rptr, 739a2e73f56SAlex Deucher .get_wptr = uvd_v4_2_ring_get_wptr, 740a2e73f56SAlex Deucher .set_wptr = uvd_v4_2_ring_set_wptr, 741a2e73f56SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs, 742e12f3d7aSChristian König .emit_frame_size = 743e12f3d7aSChristian König 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 744e12f3d7aSChristian König .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 745a2e73f56SAlex Deucher .emit_ib = uvd_v4_2_ring_emit_ib, 746a2e73f56SAlex Deucher .emit_fence = uvd_v4_2_ring_emit_fence, 747a2e73f56SAlex Deucher .test_ring = uvd_v4_2_ring_test_ring, 7488de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib, 749edff0e28SJammy Zhou .insert_nop = amdgpu_ring_insert_nop, 7509e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib, 751c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use, 752c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use, 753a2e73f56SAlex Deucher }; 754a2e73f56SAlex Deucher 755a2e73f56SAlex Deucher static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 756a2e73f56SAlex Deucher { 7572bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; 758a2e73f56SAlex Deucher } 759a2e73f56SAlex Deucher 760a2e73f56SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 761a2e73f56SAlex Deucher .set = uvd_v4_2_set_interrupt_state, 762a2e73f56SAlex Deucher .process = uvd_v4_2_process_interrupt, 763a2e73f56SAlex Deucher }; 764a2e73f56SAlex Deucher 765a2e73f56SAlex Deucher static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 766a2e73f56SAlex Deucher { 7672bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1; 7682bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; 769a2e73f56SAlex Deucher } 770a1255107SAlex Deucher 771a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 772a1255107SAlex Deucher { 773a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD, 774a1255107SAlex Deucher .major = 4, 775a1255107SAlex Deucher .minor = 2, 776a1255107SAlex Deucher .rev = 0, 777a1255107SAlex Deucher .funcs = &uvd_v4_2_ip_funcs, 778a1255107SAlex Deucher }; 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