148ef409cSJohn Clements /* 248ef409cSJohn Clements * Copyright 2020 Advanced Micro Devices, Inc. 348ef409cSJohn Clements * 448ef409cSJohn Clements * Permission is hereby granted, free of charge, to any person obtaining a 548ef409cSJohn Clements * copy of this software and associated documentation files (the "Software"), 648ef409cSJohn Clements * to deal in the Software without restriction, including without limitation 748ef409cSJohn Clements * the rights to use, copy, modify, merge, publish, distribute, sublicense, 848ef409cSJohn Clements * and/or sell copies of the Software, and to permit persons to whom the 948ef409cSJohn Clements * Software is furnished to do so, subject to the following conditions: 1048ef409cSJohn Clements * 1148ef409cSJohn Clements * The above copyright notice and this permission notice shall be included in 1248ef409cSJohn Clements * all copies or substantial portions of the Software. 1348ef409cSJohn Clements * 1448ef409cSJohn Clements * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1548ef409cSJohn Clements * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1648ef409cSJohn Clements * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1748ef409cSJohn Clements * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1848ef409cSJohn Clements * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1948ef409cSJohn Clements * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2048ef409cSJohn Clements * OTHER DEALINGS IN THE SOFTWARE. 2148ef409cSJohn Clements * 2248ef409cSJohn Clements */ 2348ef409cSJohn Clements #ifndef __UMC_V8_7_H__ 2448ef409cSJohn Clements #define __UMC_V8_7_H__ 2548ef409cSJohn Clements 2648ef409cSJohn Clements #include "soc15_common.h" 2748ef409cSJohn Clements #include "amdgpu.h" 2848ef409cSJohn Clements 2948ef409cSJohn Clements /* HBM Memory Channel Width */ 3048ef409cSJohn Clements #define UMC_V8_7_HBM_MEMORY_CHANNEL_WIDTH 128 3148ef409cSJohn Clements /* number of umc channel instance with memory map register access */ 3248ef409cSJohn Clements #define UMC_V8_7_CHANNEL_INSTANCE_NUM 2 3348ef409cSJohn Clements /* number of umc instance with memory map register access */ 3448ef409cSJohn Clements #define UMC_V8_7_UMC_INSTANCE_NUM 8 3548ef409cSJohn Clements /* total channel instances in one umc block */ 3648ef409cSJohn Clements #define UMC_V8_7_TOTAL_CHANNEL_NUM (UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM) 3748ef409cSJohn Clements /* UMC regiser per channel offset */ 3848ef409cSJohn Clements #define UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA 0x400 3948ef409cSJohn Clements 4048ef409cSJohn Clements /* EccErrCnt max value */ 4148ef409cSJohn Clements #define UMC_V8_7_CE_CNT_MAX 0xffff 4248ef409cSJohn Clements /* umc ce interrupt threshold */ 4348ef409cSJohn Clements #define UMC_V8_7_CE_INT_THRESHOLD 0xffff 4448ef409cSJohn Clements /* umc ce count initial value */ 4548ef409cSJohn Clements #define UMC_V8_7_CE_CNT_INIT (UMC_V8_7_CE_CNT_MAX - UMC_V8_7_CE_INT_THRESHOLD) 4648ef409cSJohn Clements 47*efe17d5aSyipechai extern struct amdgpu_umc_ras umc_v8_7_ras; 4848ef409cSJohn Clements extern const uint32_t 4948ef409cSJohn Clements umc_v8_7_channel_idx_tbl[UMC_V8_7_UMC_INSTANCE_NUM][UMC_V8_7_CHANNEL_INSTANCE_NUM]; 5048ef409cSJohn Clements 5148ef409cSJohn Clements #endif 52