1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __UMC_V8_10_H__ 24 #define __UMC_V8_10_H__ 25 26 #include "soc15_common.h" 27 #include "amdgpu.h" 28 29 /* number of umc channel instance with memory map register access */ 30 #define UMC_V8_10_CHANNEL_INSTANCE_NUM 2 31 /* number of umc instance with memory map register access */ 32 #define UMC_V8_10_UMC_INSTANCE_NUM 2 33 34 /* Total channel instances for all umc nodes */ 35 #define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \ 36 (UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * (adev)->umc.node_inst_num) 37 38 /* UMC regiser per channel offset */ 39 #define UMC_V8_10_PER_CHANNEL_OFFSET 0x400 40 41 /* EccErrCnt max value */ 42 #define UMC_V8_10_CE_CNT_MAX 0xffff 43 /* umc ce interrupt threshold */ 44 #define UUMC_V8_10_CE_INT_THRESHOLD 0xffff 45 /* umc ce count initial value */ 46 #define UMC_V8_10_CE_CNT_INIT (UMC_V8_10_CE_CNT_MAX - UUMC_V8_10_CE_INT_THRESHOLD) 47 48 #define UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM 4 49 50 /* The C5 bit in NA address */ 51 #define UMC_V8_10_NA_C5_BIT 14 52 53 /* Map to swizzle mode address */ 54 #define SWIZZLE_MODE_TMP_ADDR(na, ch_num, ch_idx) \ 55 ((((na) >> 10) * (ch_num) + (ch_idx)) << 10) 56 #define SWIZZLE_MODE_ADDR_HI(addr, col_bit) \ 57 (((addr) >> ((col_bit) + 2)) << ((col_bit) + 2)) 58 #define SWIZZLE_MODE_ADDR_MID(na, col_bit) ((((na) >> 8) & 0x3) << (col_bit)) 59 #define SWIZZLE_MODE_ADDR_LOW(addr, col_bit) \ 60 ((((addr) >> 10) & ((0x1ULL << (col_bit - 8)) - 1)) << 8) 61 #define SWIZZLE_MODE_ADDR_LSB(na) ((na) & 0xFF) 62 63 extern struct amdgpu_umc_ras umc_v8_10_ras; 64 extern const uint32_t 65 umc_v8_10_channel_idx_tbl[] 66 [UMC_V8_10_UMC_INSTANCE_NUM] 67 [UMC_V8_10_CHANNEL_INSTANCE_NUM]; 68 69 #endif 70 71