1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v8_10.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_8_10_0_offset.h" 28 #include "umc/umc_8_10_0_sh_mask.h" 29 30 #define UMC_8_NODE_DIST 0x800000 31 #define UMC_8_INST_DIST 0x4000 32 33 struct channelnum_map_colbit { 34 uint32_t channel_num; 35 uint32_t col_bit; 36 }; 37 38 const struct channelnum_map_colbit umc_v8_10_channelnum_map_colbit_table[] = { 39 {24, 13}, 40 {20, 13}, 41 {16, 12}, 42 {14, 12}, 43 {12, 12}, 44 {10, 12}, 45 {6, 11}, 46 }; 47 48 const uint32_t 49 umc_v8_10_channel_idx_tbl[] 50 [UMC_V8_10_UMC_INSTANCE_NUM] 51 [UMC_V8_10_CHANNEL_INSTANCE_NUM] = { 52 {{16, 18}, {17, 19}}, 53 {{15, 11}, {3, 7}}, 54 {{1, 5}, {13, 9}}, 55 {{23, 21}, {22, 20}}, 56 {{0, 4}, {12, 8}}, 57 {{14, 10}, {2, 6}} 58 }; 59 60 static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev, 61 uint32_t node_inst, 62 uint32_t umc_inst, 63 uint32_t ch_inst) 64 { 65 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + 66 UMC_8_NODE_DIST * node_inst; 67 } 68 69 static void umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev, 70 uint32_t umc_reg_offset) 71 { 72 uint32_t ecc_err_cnt_addr; 73 74 ecc_err_cnt_addr = 75 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); 76 77 /* clear error count */ 78 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, 79 UMC_V8_10_CE_CNT_INIT); 80 } 81 82 static void umc_v8_10_clear_error_count(struct amdgpu_device *adev) 83 { 84 uint32_t node_inst = 0; 85 uint32_t umc_inst = 0; 86 uint32_t ch_inst = 0; 87 uint32_t umc_reg_offset = 0; 88 89 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 90 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 91 node_inst, 92 umc_inst, 93 ch_inst); 94 95 umc_v8_10_clear_error_count_per_channel(adev, 96 umc_reg_offset); 97 } 98 } 99 100 static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev, 101 uint32_t umc_reg_offset, 102 unsigned long *error_count) 103 { 104 uint32_t ecc_err_cnt, ecc_err_cnt_addr; 105 uint64_t mc_umc_status; 106 uint32_t mc_umc_status_addr; 107 108 /* UMC 8_10 registers */ 109 ecc_err_cnt_addr = 110 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); 111 mc_umc_status_addr = 112 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 113 114 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); 115 *error_count += 116 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - 117 UMC_V8_10_CE_CNT_INIT); 118 119 /* Check for SRAM correctable error, MCUMC_STATUS is a 64 bit register */ 120 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 121 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 122 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 123 *error_count += 1; 124 } 125 126 static void umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device *adev, 127 uint32_t umc_reg_offset, 128 unsigned long *error_count) 129 { 130 uint64_t mc_umc_status; 131 uint32_t mc_umc_status_addr; 132 133 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 134 135 /* Check the MCUMC_STATUS. */ 136 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 137 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 138 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 139 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 140 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 141 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 142 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 143 *error_count += 1; 144 } 145 146 static void umc_v8_10_query_ras_error_count(struct amdgpu_device *adev, 147 void *ras_error_status) 148 { 149 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 150 151 uint32_t node_inst = 0; 152 uint32_t umc_inst = 0; 153 uint32_t ch_inst = 0; 154 uint32_t umc_reg_offset = 0; 155 156 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 157 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 158 node_inst, 159 umc_inst, 160 ch_inst); 161 162 umc_v8_10_query_correctable_error_count(adev, 163 umc_reg_offset, 164 &(err_data->ce_count)); 165 umc_v8_10_query_uncorrectable_error_count(adev, 166 umc_reg_offset, 167 &(err_data->ue_count)); 168 } 169 170 umc_v8_10_clear_error_count(adev); 171 } 172 173 static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num) 174 { 175 uint32_t t = 0; 176 177 for (t = 0; t < ARRAY_SIZE(umc_v8_10_channelnum_map_colbit_table); t++) 178 if (channel_num == umc_v8_10_channelnum_map_colbit_table[t].channel_num) 179 return umc_v8_10_channelnum_map_colbit_table[t].col_bit; 180 181 /* Failed to get col_bit. */ 182 return U32_MAX; 183 } 184 185 /* 186 * Mapping normal address to soc physical address in swizzle mode. 187 */ 188 static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev, 189 uint32_t channel_idx, 190 uint64_t na, uint64_t *soc_pa) 191 { 192 uint32_t channel_num = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 193 uint32_t col_bit = umc_v8_10_get_col_bit(channel_num); 194 uint64_t tmp_addr; 195 196 if (col_bit == U32_MAX) 197 return -1; 198 199 tmp_addr = SWIZZLE_MODE_TMP_ADDR(na, channel_num, channel_idx); 200 *soc_pa = SWIZZLE_MODE_ADDR_HI(tmp_addr, col_bit) | 201 SWIZZLE_MODE_ADDR_MID(na, col_bit) | 202 SWIZZLE_MODE_ADDR_LOW(tmp_addr, col_bit) | 203 SWIZZLE_MODE_ADDR_LSB(na); 204 205 return 0; 206 } 207 208 static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 209 struct ras_err_data *err_data, 210 uint32_t umc_reg_offset, 211 uint32_t node_inst, 212 uint32_t ch_inst, 213 uint32_t umc_inst) 214 { 215 uint64_t mc_umc_status_addr; 216 uint64_t mc_umc_status, err_addr; 217 uint32_t channel_index; 218 219 mc_umc_status_addr = 220 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 221 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 222 223 if (mc_umc_status == 0) 224 return; 225 226 if (!err_data->err_addr) { 227 /* clear umc status */ 228 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 229 return; 230 } 231 232 channel_index = 233 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * 234 adev->umc.channel_inst_num + 235 umc_inst * adev->umc.channel_inst_num + 236 ch_inst]; 237 238 /* calculate error address if ue/ce error is detected */ 239 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 240 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && 241 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 242 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { 243 uint32_t addr_lsb; 244 uint64_t mc_umc_addrt0; 245 246 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 247 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); 248 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 249 250 /* the lowest lsb bits should be ignored */ 251 addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb); 252 253 err_addr &= ~((0x1ULL << addr_lsb) - 1); 254 255 /* we only save ue error information currently, ce is skipped */ 256 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) { 257 uint64_t na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT); 258 uint64_t na_err_addr, retired_page_addr; 259 uint32_t col = 0; 260 int ret = 0; 261 262 /* loop for all possibilities of [C6 C5] in normal address. */ 263 for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) { 264 na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT); 265 266 /* Mapping normal error address to retired soc physical address. */ 267 ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index, 268 na_err_addr, &retired_page_addr); 269 if (ret) { 270 dev_err(adev->dev, "Failed to map pa from umc na.\n"); 271 break; 272 } 273 dev_info(adev->dev, "Error Address(PA): 0x%llx\n", 274 retired_page_addr); 275 amdgpu_umc_fill_error_record(err_data, na_err_addr, 276 retired_page_addr, channel_index, umc_inst); 277 } 278 } 279 } 280 281 /* clear umc status */ 282 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 283 } 284 285 static void umc_v8_10_query_ras_error_address(struct amdgpu_device *adev, 286 void *ras_error_status) 287 { 288 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 289 uint32_t node_inst = 0; 290 uint32_t umc_inst = 0; 291 uint32_t ch_inst = 0; 292 uint32_t umc_reg_offset = 0; 293 294 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 295 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 296 node_inst, 297 umc_inst, 298 ch_inst); 299 300 umc_v8_10_query_error_address(adev, 301 err_data, 302 umc_reg_offset, 303 node_inst, 304 ch_inst, 305 umc_inst); 306 } 307 } 308 309 static void umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev, 310 uint32_t umc_reg_offset) 311 { 312 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 313 uint32_t ecc_err_cnt_addr; 314 315 ecc_err_cnt_sel_addr = 316 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel); 317 ecc_err_cnt_addr = 318 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); 319 320 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 321 322 /* set ce error interrupt type to APIC based interrupt */ 323 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel, 324 GeccErrInt, 0x1); 325 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 326 /* set error count to initial value */ 327 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT); 328 } 329 330 static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev) 331 { 332 uint32_t node_inst = 0; 333 uint32_t umc_inst = 0; 334 uint32_t ch_inst = 0; 335 uint32_t umc_reg_offset = 0; 336 337 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 338 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 339 node_inst, 340 umc_inst, 341 ch_inst); 342 343 umc_v8_10_err_cnt_init_per_channel(adev, umc_reg_offset); 344 } 345 } 346 347 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = { 348 .query_ras_error_count = umc_v8_10_query_ras_error_count, 349 .query_ras_error_address = umc_v8_10_query_ras_error_address, 350 }; 351 352 struct amdgpu_umc_ras umc_v8_10_ras = { 353 .ras_block = { 354 .hw_ops = &umc_v8_10_ras_hw_ops, 355 }, 356 .err_cnt_init = umc_v8_10_err_cnt_init, 357 }; 358