1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v8_10.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_8_10_0_offset.h" 28 #include "umc/umc_8_10_0_sh_mask.h" 29 30 #define UMC_8_NODE_DIST 0x800000 31 #define UMC_8_INST_DIST 0x4000 32 33 struct channelnum_map_colbit { 34 uint32_t channel_num; 35 uint32_t col_bit; 36 }; 37 38 const struct channelnum_map_colbit umc_v8_10_channelnum_map_colbit_table[] = { 39 {24, 13}, 40 {20, 13}, 41 {16, 12}, 42 {14, 12}, 43 {12, 12}, 44 {10, 12}, 45 {6, 11}, 46 }; 47 48 const uint32_t 49 umc_v8_10_channel_idx_tbl_ext0[] 50 [UMC_V8_10_UMC_INSTANCE_NUM] 51 [UMC_V8_10_CHANNEL_INSTANCE_NUM] = { 52 {{1, 5}, {7, 3}}, 53 {{14, 15}, {13, 12}}, 54 {{10, 11}, {9, 8}}, 55 {{6, 2}, {0, 4}} 56 }; 57 58 const uint32_t 59 umc_v8_10_channel_idx_tbl[] 60 [UMC_V8_10_UMC_INSTANCE_NUM] 61 [UMC_V8_10_CHANNEL_INSTANCE_NUM] = { 62 {{16, 18}, {17, 19}}, 63 {{15, 11}, {3, 7}}, 64 {{1, 5}, {13, 9}}, 65 {{23, 21}, {22, 20}}, 66 {{0, 4}, {12, 8}}, 67 {{14, 10}, {2, 6}} 68 }; 69 70 static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev, 71 uint32_t node_inst, 72 uint32_t umc_inst, 73 uint32_t ch_inst) 74 { 75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + 76 UMC_8_NODE_DIST * node_inst; 77 } 78 79 static void umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev, 80 uint32_t umc_reg_offset) 81 { 82 uint32_t ecc_err_cnt_addr; 83 84 ecc_err_cnt_addr = 85 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); 86 87 /* clear error count */ 88 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, 89 UMC_V8_10_CE_CNT_INIT); 90 } 91 92 static void umc_v8_10_clear_error_count(struct amdgpu_device *adev) 93 { 94 uint32_t node_inst = 0; 95 uint32_t umc_inst = 0; 96 uint32_t ch_inst = 0; 97 uint32_t umc_reg_offset = 0; 98 99 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 100 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 101 node_inst, 102 umc_inst, 103 ch_inst); 104 105 umc_v8_10_clear_error_count_per_channel(adev, 106 umc_reg_offset); 107 } 108 } 109 110 static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev, 111 uint32_t umc_reg_offset, 112 unsigned long *error_count) 113 { 114 uint64_t mc_umc_status; 115 uint32_t mc_umc_status_addr; 116 117 /* UMC 8_10 registers */ 118 mc_umc_status_addr = 119 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 120 121 /* Rely on MCUMC_STATUS for correctable error counter 122 * MCUMC_STATUS is a 64 bit register 123 */ 124 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 125 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 126 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 127 *error_count += 1; 128 } 129 130 static void umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device *adev, 131 uint32_t umc_reg_offset, 132 unsigned long *error_count) 133 { 134 uint64_t mc_umc_status; 135 uint32_t mc_umc_status_addr; 136 137 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 138 139 /* Check the MCUMC_STATUS. */ 140 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 141 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 142 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 143 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 144 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 145 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 146 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 147 *error_count += 1; 148 } 149 150 static void umc_v8_10_query_ras_error_count(struct amdgpu_device *adev, 151 void *ras_error_status) 152 { 153 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 154 155 uint32_t node_inst = 0; 156 uint32_t umc_inst = 0; 157 uint32_t ch_inst = 0; 158 uint32_t umc_reg_offset = 0; 159 160 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 161 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 162 node_inst, 163 umc_inst, 164 ch_inst); 165 166 umc_v8_10_query_correctable_error_count(adev, 167 umc_reg_offset, 168 &(err_data->ce_count)); 169 umc_v8_10_query_uncorrectable_error_count(adev, 170 umc_reg_offset, 171 &(err_data->ue_count)); 172 } 173 174 umc_v8_10_clear_error_count(adev); 175 } 176 177 static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num) 178 { 179 uint32_t t = 0; 180 181 for (t = 0; t < ARRAY_SIZE(umc_v8_10_channelnum_map_colbit_table); t++) 182 if (channel_num == umc_v8_10_channelnum_map_colbit_table[t].channel_num) 183 return umc_v8_10_channelnum_map_colbit_table[t].col_bit; 184 185 /* Failed to get col_bit. */ 186 return U32_MAX; 187 } 188 189 /* 190 * Mapping normal address to soc physical address in swizzle mode. 191 */ 192 static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev, 193 uint32_t channel_idx, 194 uint64_t na, uint64_t *soc_pa) 195 { 196 uint32_t channel_num = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 197 uint32_t col_bit = umc_v8_10_get_col_bit(channel_num); 198 uint64_t tmp_addr; 199 200 if (col_bit == U32_MAX) 201 return -1; 202 203 tmp_addr = SWIZZLE_MODE_TMP_ADDR(na, channel_num, channel_idx); 204 *soc_pa = SWIZZLE_MODE_ADDR_HI(tmp_addr, col_bit) | 205 SWIZZLE_MODE_ADDR_MID(na, col_bit) | 206 SWIZZLE_MODE_ADDR_LOW(tmp_addr, col_bit) | 207 SWIZZLE_MODE_ADDR_LSB(na); 208 209 return 0; 210 } 211 212 static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 213 struct ras_err_data *err_data, 214 uint32_t umc_reg_offset, 215 uint32_t node_inst, 216 uint32_t ch_inst, 217 uint32_t umc_inst) 218 { 219 uint64_t mc_umc_status_addr; 220 uint64_t mc_umc_status, err_addr; 221 uint64_t mc_umc_addrt0, na_err_addr_base; 222 uint64_t na_err_addr, retired_page_addr; 223 uint32_t channel_index, addr_lsb, col = 0; 224 int ret = 0; 225 226 mc_umc_status_addr = 227 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 228 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 229 230 if (mc_umc_status == 0) 231 return; 232 233 if (!err_data->err_addr) { 234 /* clear umc status */ 235 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 236 return; 237 } 238 239 channel_index = 240 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * 241 adev->umc.channel_inst_num + 242 umc_inst * adev->umc.channel_inst_num + 243 ch_inst]; 244 245 /* calculate error address if ue error is detected */ 246 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 247 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && 248 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) { 249 250 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 251 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); 252 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 253 254 /* the lowest lsb bits should be ignored */ 255 addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb); 256 err_addr &= ~((0x1ULL << addr_lsb) - 1); 257 na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT); 258 259 /* loop for all possibilities of [C6 C5] in normal address. */ 260 for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) { 261 na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT); 262 263 /* Mapping normal error address to retired soc physical address. */ 264 ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index, 265 na_err_addr, &retired_page_addr); 266 if (ret) { 267 dev_err(adev->dev, "Failed to map pa from umc na.\n"); 268 break; 269 } 270 dev_info(adev->dev, "Error Address(PA): 0x%llx\n", 271 retired_page_addr); 272 amdgpu_umc_fill_error_record(err_data, na_err_addr, 273 retired_page_addr, channel_index, umc_inst); 274 } 275 } 276 277 /* clear umc status */ 278 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 279 } 280 281 static void umc_v8_10_query_ras_error_address(struct amdgpu_device *adev, 282 void *ras_error_status) 283 { 284 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 285 uint32_t node_inst = 0; 286 uint32_t umc_inst = 0; 287 uint32_t ch_inst = 0; 288 uint32_t umc_reg_offset = 0; 289 290 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 291 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 292 node_inst, 293 umc_inst, 294 ch_inst); 295 296 umc_v8_10_query_error_address(adev, 297 err_data, 298 umc_reg_offset, 299 node_inst, 300 ch_inst, 301 umc_inst); 302 } 303 } 304 305 static void umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev, 306 uint32_t umc_reg_offset) 307 { 308 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 309 uint32_t ecc_err_cnt_addr; 310 311 ecc_err_cnt_sel_addr = 312 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel); 313 ecc_err_cnt_addr = 314 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); 315 316 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 317 318 /* set ce error interrupt type to APIC based interrupt */ 319 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel, 320 GeccErrInt, 0x1); 321 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 322 /* set error count to initial value */ 323 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT); 324 } 325 326 static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev) 327 { 328 uint32_t node_inst = 0; 329 uint32_t umc_inst = 0; 330 uint32_t ch_inst = 0; 331 uint32_t umc_reg_offset = 0; 332 333 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 334 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 335 node_inst, 336 umc_inst, 337 ch_inst); 338 339 umc_v8_10_err_cnt_init_per_channel(adev, umc_reg_offset); 340 } 341 } 342 343 static uint32_t umc_v8_10_query_ras_poison_mode_per_channel( 344 struct amdgpu_device *adev, 345 uint32_t umc_reg_offset) 346 { 347 uint32_t ecc_ctrl_addr, ecc_ctrl; 348 349 ecc_ctrl_addr = 350 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccCtrl); 351 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + 352 umc_reg_offset) * 4); 353 354 return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_GeccCtrl, UCFatalEn); 355 } 356 357 static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev) 358 { 359 uint32_t umc_reg_offset = 0; 360 361 /* Enabling fatal error in umc node0 instance0 channel0 will be 362 * considered as fatal error mode 363 */ 364 umc_reg_offset = get_umc_v8_10_reg_offset(adev, 0, 0, 0); 365 return !umc_v8_10_query_ras_poison_mode_per_channel(adev, umc_reg_offset); 366 } 367 368 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = { 369 .query_ras_error_count = umc_v8_10_query_ras_error_count, 370 .query_ras_error_address = umc_v8_10_query_ras_error_address, 371 }; 372 373 struct amdgpu_umc_ras umc_v8_10_ras = { 374 .ras_block = { 375 .hw_ops = &umc_v8_10_ras_hw_ops, 376 }, 377 .err_cnt_init = umc_v8_10_err_cnt_init, 378 .query_ras_poison_mode = umc_v8_10_query_ras_poison_mode, 379 }; 380