1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v6_7.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 28 #include "umc/umc_6_7_0_offset.h" 29 #include "umc/umc_6_7_0_sh_mask.h" 30 31 const uint32_t 32 umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = { 33 {28, 20, 24, 16, 12, 4, 8, 0}, 34 {6, 30, 2, 26, 22, 14, 18, 10}, 35 {19, 11, 15, 7, 3, 27, 31, 23}, 36 {9, 1, 5, 29, 25, 17, 21, 13} 37 }; 38 const uint32_t 39 umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = { 40 {19, 11, 15, 7, 3, 27, 31, 23}, 41 {9, 1, 5, 29, 25, 17, 21, 13}, 42 {28, 20, 24, 16, 12, 4, 8, 0}, 43 {6, 30, 2, 26, 22, 14, 18, 10}, 44 }; 45 46 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev, 47 uint32_t umc_inst, 48 uint32_t ch_inst) 49 { 50 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst; 51 } 52 53 static inline uint32_t get_umc_v6_7_channel_index(struct amdgpu_device *adev, 54 uint32_t umc_inst, 55 uint32_t ch_inst) 56 { 57 return adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; 58 } 59 60 static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev, 61 uint32_t umc_inst, uint32_t ch_inst, 62 unsigned long *error_count) 63 { 64 uint64_t mc_umc_status; 65 uint32_t eccinfo_table_idx; 66 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 67 68 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; 69 /* check for SRAM correctable error 70 MCUMC_STATUS is a 64 bit register */ 71 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; 72 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 73 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 74 *error_count += 1; 75 } 76 77 static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev, 78 uint32_t umc_inst, uint32_t ch_inst, 79 unsigned long *error_count) 80 { 81 uint64_t mc_umc_status; 82 uint32_t eccinfo_table_idx; 83 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 84 85 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; 86 /* check the MCUMC_STATUS */ 87 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; 88 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 89 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 90 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 91 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 92 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 93 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 94 *error_count += 1; 95 } 96 97 static void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev, 98 void *ras_error_status) 99 { 100 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 101 102 uint32_t umc_inst = 0; 103 uint32_t ch_inst = 0; 104 105 /*TODO: driver needs to toggle DF Cstate to ensure 106 * safe access of UMC registers. Will add the protection */ 107 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 108 umc_v6_7_ecc_info_query_correctable_error_count(adev, 109 umc_inst, ch_inst, 110 &(err_data->ce_count)); 111 umc_v6_7_ecc_info_querry_uncorrectable_error_count(adev, 112 umc_inst, ch_inst, 113 &(err_data->ue_count)); 114 } 115 } 116 117 static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, 118 struct ras_err_data *err_data, 119 uint32_t ch_inst, 120 uint32_t umc_inst) 121 { 122 uint64_t mc_umc_status, err_addr, soc_pa, retired_page, column; 123 uint32_t channel_index; 124 uint32_t eccinfo_table_idx; 125 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 126 127 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; 128 channel_index = 129 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; 130 131 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; 132 133 if (mc_umc_status == 0) 134 return; 135 136 if (!err_data->err_addr) 137 return; 138 139 /* calculate error address if ue/ce error is detected */ 140 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 141 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 142 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { 143 144 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; 145 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 146 147 /* translate umc channel address to soc pa, 3 parts are included */ 148 soc_pa = ADDR_OF_8KB_BLOCK(err_addr) | 149 ADDR_OF_256B_BLOCK(channel_index) | 150 OFFSET_IN_256B_BLOCK(err_addr); 151 152 /* The umc channel bits are not original values, they are hashed */ 153 SET_CHANNEL_HASH(channel_index, soc_pa); 154 155 /* clear [C4 C3 C2] in soc physical address */ 156 soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT); 157 158 /* we only save ue error information currently, ce is skipped */ 159 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) 160 == 1) { 161 /* loop for all possibilities of [C4 C3 C2] */ 162 for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) { 163 retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT); 164 amdgpu_umc_fill_error_record(err_data, err_addr, 165 retired_page, channel_index, umc_inst); 166 167 /* shift R14 bit */ 168 retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT); 169 amdgpu_umc_fill_error_record(err_data, err_addr, 170 retired_page, channel_index, umc_inst); 171 } 172 } 173 } 174 } 175 176 static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev, 177 void *ras_error_status) 178 { 179 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 180 181 uint32_t umc_inst = 0; 182 uint32_t ch_inst = 0; 183 184 /*TODO: driver needs to toggle DF Cstate to ensure 185 * safe access of UMC resgisters. Will add the protection 186 * when firmware interface is ready */ 187 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 188 umc_v6_7_ecc_info_query_error_address(adev, 189 err_data, 190 ch_inst, 191 umc_inst); 192 } 193 } 194 195 static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev, 196 uint32_t umc_reg_offset, 197 unsigned long *error_count) 198 { 199 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 200 uint32_t ecc_err_cnt, ecc_err_cnt_addr; 201 uint64_t mc_umc_status; 202 uint32_t mc_umc_status_addr; 203 204 /* UMC 6_1_1 registers */ 205 ecc_err_cnt_sel_addr = 206 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); 207 ecc_err_cnt_addr = 208 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); 209 mc_umc_status_addr = 210 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 211 212 /* select the lower chip and check the error count */ 213 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 214 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 215 EccErrCntCsSel, 0); 216 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 217 218 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); 219 *error_count += 220 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - 221 UMC_V6_7_CE_CNT_INIT); 222 223 /* select the higher chip and check the err counter */ 224 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 225 EccErrCntCsSel, 1); 226 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 227 228 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); 229 *error_count += 230 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - 231 UMC_V6_7_CE_CNT_INIT); 232 233 /* check for SRAM correctable error 234 MCUMC_STATUS is a 64 bit register */ 235 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 236 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 237 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 238 *error_count += 1; 239 } 240 241 static void umc_v6_7_querry_uncorrectable_error_count(struct amdgpu_device *adev, 242 uint32_t umc_reg_offset, 243 unsigned long *error_count) 244 { 245 uint64_t mc_umc_status; 246 uint32_t mc_umc_status_addr; 247 248 mc_umc_status_addr = 249 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 250 251 /* check the MCUMC_STATUS */ 252 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 253 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 254 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 255 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 256 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 257 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 258 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 259 *error_count += 1; 260 } 261 262 static void umc_v6_7_reset_error_count_per_channel(struct amdgpu_device *adev, 263 uint32_t umc_reg_offset) 264 { 265 uint32_t ecc_err_cnt_addr; 266 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 267 268 ecc_err_cnt_sel_addr = 269 SOC15_REG_OFFSET(UMC, 0, 270 regUMCCH0_0_EccErrCntSel); 271 ecc_err_cnt_addr = 272 SOC15_REG_OFFSET(UMC, 0, 273 regUMCCH0_0_EccErrCnt); 274 275 /* select the lower chip */ 276 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + 277 umc_reg_offset) * 4); 278 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, 279 UMCCH0_0_EccErrCntSel, 280 EccErrCntCsSel, 0); 281 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, 282 ecc_err_cnt_sel); 283 284 /* clear lower chip error count */ 285 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, 286 UMC_V6_7_CE_CNT_INIT); 287 288 /* select the higher chip */ 289 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + 290 umc_reg_offset) * 4); 291 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, 292 UMCCH0_0_EccErrCntSel, 293 EccErrCntCsSel, 1); 294 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, 295 ecc_err_cnt_sel); 296 297 /* clear higher chip error count */ 298 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, 299 UMC_V6_7_CE_CNT_INIT); 300 } 301 302 static void umc_v6_7_reset_error_count(struct amdgpu_device *adev) 303 { 304 uint32_t umc_inst = 0; 305 uint32_t ch_inst = 0; 306 uint32_t umc_reg_offset = 0; 307 308 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 309 umc_reg_offset = get_umc_v6_7_reg_offset(adev, 310 umc_inst, 311 ch_inst); 312 313 umc_v6_7_reset_error_count_per_channel(adev, 314 umc_reg_offset); 315 } 316 } 317 318 static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev, 319 void *ras_error_status) 320 { 321 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 322 323 uint32_t umc_inst = 0; 324 uint32_t ch_inst = 0; 325 uint32_t umc_reg_offset = 0; 326 327 /*TODO: driver needs to toggle DF Cstate to ensure 328 * safe access of UMC registers. Will add the protection */ 329 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 330 umc_reg_offset = get_umc_v6_7_reg_offset(adev, 331 umc_inst, 332 ch_inst); 333 umc_v6_7_query_correctable_error_count(adev, 334 umc_reg_offset, 335 &(err_data->ce_count)); 336 umc_v6_7_querry_uncorrectable_error_count(adev, 337 umc_reg_offset, 338 &(err_data->ue_count)); 339 } 340 341 umc_v6_7_reset_error_count(adev); 342 } 343 344 static void umc_v6_7_query_error_address(struct amdgpu_device *adev, 345 struct ras_err_data *err_data, 346 uint32_t umc_reg_offset, 347 uint32_t ch_inst, 348 uint32_t umc_inst) 349 { 350 uint32_t mc_umc_status_addr; 351 uint32_t channel_index; 352 uint64_t mc_umc_status, mc_umc_addrt0; 353 uint64_t err_addr, soc_pa, retired_page, column; 354 355 mc_umc_status_addr = 356 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 357 mc_umc_addrt0 = 358 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 359 360 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 361 362 if (mc_umc_status == 0) 363 return; 364 365 if (!err_data->err_addr) { 366 /* clear umc status */ 367 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 368 return; 369 } 370 371 channel_index = 372 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; 373 374 /* calculate error address if ue/ce error is detected */ 375 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 376 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 377 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { 378 379 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); 380 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 381 382 /* translate umc channel address to soc pa, 3 parts are included */ 383 soc_pa = ADDR_OF_8KB_BLOCK(err_addr) | 384 ADDR_OF_256B_BLOCK(channel_index) | 385 OFFSET_IN_256B_BLOCK(err_addr); 386 387 /* The umc channel bits are not original values, they are hashed */ 388 SET_CHANNEL_HASH(channel_index, soc_pa); 389 390 /* clear [C4 C3 C2] in soc physical address */ 391 soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT); 392 393 /* we only save ue error information currently, ce is skipped */ 394 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) 395 == 1) { 396 /* loop for all possibilities of [C4 C3 C2] */ 397 for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) { 398 retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT); 399 amdgpu_umc_fill_error_record(err_data, err_addr, 400 retired_page, channel_index, umc_inst); 401 402 /* shift R14 bit */ 403 retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT); 404 amdgpu_umc_fill_error_record(err_data, err_addr, 405 retired_page, channel_index, umc_inst); 406 } 407 } 408 } 409 410 /* clear umc status */ 411 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 412 } 413 414 static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev, 415 void *ras_error_status) 416 { 417 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 418 419 uint32_t umc_inst = 0; 420 uint32_t ch_inst = 0; 421 uint32_t umc_reg_offset = 0; 422 423 /*TODO: driver needs to toggle DF Cstate to ensure 424 * safe access of UMC resgisters. Will add the protection 425 * when firmware interface is ready */ 426 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 427 umc_reg_offset = get_umc_v6_7_reg_offset(adev, 428 umc_inst, 429 ch_inst); 430 umc_v6_7_query_error_address(adev, 431 err_data, 432 umc_reg_offset, 433 ch_inst, 434 umc_inst); 435 } 436 } 437 438 static uint32_t umc_v6_7_query_ras_poison_mode_per_channel( 439 struct amdgpu_device *adev, 440 uint32_t umc_reg_offset) 441 { 442 uint32_t ecc_ctrl_addr, ecc_ctrl; 443 444 ecc_ctrl_addr = 445 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccCtrl); 446 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + 447 umc_reg_offset) * 4); 448 449 return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn); 450 } 451 452 static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev) 453 { 454 uint32_t umc_inst = 0; 455 uint32_t ch_inst = 0; 456 uint32_t umc_reg_offset = 0; 457 458 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 459 umc_reg_offset = get_umc_v6_7_reg_offset(adev, 460 umc_inst, 461 ch_inst); 462 /* Enabling fatal error in one channel will be considered 463 as fatal error mode */ 464 if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset)) 465 return false; 466 } 467 468 return true; 469 } 470 471 const struct amdgpu_ras_block_hw_ops umc_v6_7_ras_hw_ops = { 472 .query_ras_error_count = umc_v6_7_query_ras_error_count, 473 .query_ras_error_address = umc_v6_7_query_ras_error_address, 474 }; 475 476 struct amdgpu_umc_ras umc_v6_7_ras = { 477 .ras_block = { 478 .hw_ops = &umc_v6_7_ras_hw_ops, 479 }, 480 .query_ras_poison_mode = umc_v6_7_query_ras_poison_mode, 481 .ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count, 482 .ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address, 483 }; 484