19884c2b1SHawking Zhang /* 29884c2b1SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 39884c2b1SHawking Zhang * 49884c2b1SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 59884c2b1SHawking Zhang * copy of this software and associated documentation files (the "Software"), 69884c2b1SHawking Zhang * to deal in the Software without restriction, including without limitation 79884c2b1SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 89884c2b1SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 99884c2b1SHawking Zhang * Software is furnished to do so, subject to the following conditions: 109884c2b1SHawking Zhang * 119884c2b1SHawking Zhang * The above copyright notice and this permission notice shall be included in 129884c2b1SHawking Zhang * all copies or substantial portions of the Software. 139884c2b1SHawking Zhang * 149884c2b1SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 159884c2b1SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 169884c2b1SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 179884c2b1SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 189884c2b1SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 199884c2b1SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 209884c2b1SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 219884c2b1SHawking Zhang * 229884c2b1SHawking Zhang */ 239884c2b1SHawking Zhang #ifndef __UMC_V6_1_H__ 249884c2b1SHawking Zhang #define __UMC_V6_1_H__ 259884c2b1SHawking Zhang 269884c2b1SHawking Zhang #include "soc15_common.h" 273aacf4eaSTao Zhou #include "amdgpu.h" 289884c2b1SHawking Zhang 299884c2b1SHawking Zhang /* HBM Memory Channel Width */ 309884c2b1SHawking Zhang #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128 319884c2b1SHawking Zhang /* number of umc channel instance with memory map register access */ 329884c2b1SHawking Zhang #define UMC_V6_1_CHANNEL_INSTANCE_NUM 4 339884c2b1SHawking Zhang /* number of umc instance with memory map register access */ 349884c2b1SHawking Zhang #define UMC_V6_1_UMC_INSTANCE_NUM 8 3533b97cf8STao Zhou /* total channel instances in one umc block */ 3633b97cf8STao Zhou #define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM) 379884c2b1SHawking Zhang /* UMC regiser per channel offset */ 384cf781c2SJohn Clements #define UMC_V6_1_PER_CHANNEL_OFFSET_VG20 0x800 394cf781c2SJohn Clements #define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT 0x400 409884c2b1SHawking Zhang 41b7f92097STao Zhou /* EccErrCnt max value */ 42b7f92097STao Zhou #define UMC_V6_1_CE_CNT_MAX 0xffff 43b7f92097STao Zhou /* umc ce interrupt threshold */ 44b7f92097STao Zhou #define UMC_V6_1_CE_INT_THRESHOLD 0xffff 45b7f92097STao Zhou /* umc ce count initial value */ 46b7f92097STao Zhou #define UMC_V6_1_CE_CNT_INIT (UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD) 47b7f92097STao Zhou 48*efe17d5aSyipechai extern struct amdgpu_umc_ras umc_v6_1_ras; 493aacf4eaSTao Zhou extern const uint32_t 503aacf4eaSTao Zhou umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM]; 519884c2b1SHawking Zhang 529884c2b1SHawking Zhang #endif 53