1aaa36a97SAlex Deucher /* 2aaa36a97SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 3aaa36a97SAlex Deucher * 4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation 7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10aaa36a97SAlex Deucher * 11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included 12aaa36a97SAlex Deucher * in all copies or substantial portions of the Software. 13aaa36a97SAlex Deucher * 14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15aaa36a97SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18aaa36a97SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19aaa36a97SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20aaa36a97SAlex Deucher * 21aaa36a97SAlex Deucher */ 22aaa36a97SAlex Deucher 23aaa36a97SAlex Deucher #ifndef __TONGA_SDMA_PKT_OPEN_H_ 24aaa36a97SAlex Deucher #define __TONGA_SDMA_PKT_OPEN_H_ 25aaa36a97SAlex Deucher 26aaa36a97SAlex Deucher #define SDMA_OP_NOP 0 27aaa36a97SAlex Deucher #define SDMA_OP_COPY 1 28aaa36a97SAlex Deucher #define SDMA_OP_WRITE 2 29aaa36a97SAlex Deucher #define SDMA_OP_INDIRECT 4 30aaa36a97SAlex Deucher #define SDMA_OP_FENCE 5 31aaa36a97SAlex Deucher #define SDMA_OP_TRAP 6 32aaa36a97SAlex Deucher #define SDMA_OP_SEM 7 33aaa36a97SAlex Deucher #define SDMA_OP_POLL_REGMEM 8 34aaa36a97SAlex Deucher #define SDMA_OP_COND_EXE 9 35aaa36a97SAlex Deucher #define SDMA_OP_ATOMIC 10 36aaa36a97SAlex Deucher #define SDMA_OP_CONST_FILL 11 37aaa36a97SAlex Deucher #define SDMA_OP_GEN_PTEPDE 12 38aaa36a97SAlex Deucher #define SDMA_OP_TIMESTAMP 13 39aaa36a97SAlex Deucher #define SDMA_OP_SRBM_WRITE 14 40aaa36a97SAlex Deucher #define SDMA_OP_PRE_EXE 15 41aaa36a97SAlex Deucher #define SDMA_SUBOP_TIMESTAMP_SET 0 42aaa36a97SAlex Deucher #define SDMA_SUBOP_TIMESTAMP_GET 1 43aaa36a97SAlex Deucher #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 44aaa36a97SAlex Deucher #define SDMA_SUBOP_COPY_LINEAR 0 45aaa36a97SAlex Deucher #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 46aaa36a97SAlex Deucher #define SDMA_SUBOP_COPY_TILED 1 47aaa36a97SAlex Deucher #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 48aaa36a97SAlex Deucher #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 49aaa36a97SAlex Deucher #define SDMA_SUBOP_COPY_SOA 3 50aaa36a97SAlex Deucher #define SDMA_SUBOP_WRITE_LINEAR 0 51aaa36a97SAlex Deucher #define SDMA_SUBOP_WRITE_TILED 1 52aaa36a97SAlex Deucher 53aaa36a97SAlex Deucher /*define for op field*/ 54aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_op_offset 0 55aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_op_mask 0x000000FF 56aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_op_shift 0 57aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 58aaa36a97SAlex Deucher 59aaa36a97SAlex Deucher /*define for sub_op field*/ 60aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_sub_op_offset 0 61aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 62aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_sub_op_shift 8 63aaa36a97SAlex Deucher #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 64aaa36a97SAlex Deucher 65aaa36a97SAlex Deucher /* 66aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_LINEAR packet 67aaa36a97SAlex Deucher */ 68aaa36a97SAlex Deucher 69aaa36a97SAlex Deucher /*define for HEADER word*/ 70aaa36a97SAlex Deucher /*define for op field*/ 71aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 72aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 73aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 74aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 75aaa36a97SAlex Deucher 76aaa36a97SAlex Deucher /*define for sub_op field*/ 77aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 78aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 79aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 80aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 81aaa36a97SAlex Deucher 82aaa36a97SAlex Deucher /*define for broadcast field*/ 83aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 84aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 85aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 86aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 87aaa36a97SAlex Deucher 88aaa36a97SAlex Deucher /*define for COUNT word*/ 89aaa36a97SAlex Deucher /*define for count field*/ 90aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 91aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 92aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 93aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 94aaa36a97SAlex Deucher 95aaa36a97SAlex Deucher /*define for PARAMETER word*/ 96aaa36a97SAlex Deucher /*define for dst_sw field*/ 97aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 98aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 99aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 100aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 101aaa36a97SAlex Deucher 102aaa36a97SAlex Deucher /*define for dst_ha field*/ 103aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2 104aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask 0x00000001 105aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift 22 106aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift) 107aaa36a97SAlex Deucher 108aaa36a97SAlex Deucher /*define for src_sw field*/ 109aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 110aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 111aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 112aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 113aaa36a97SAlex Deucher 114aaa36a97SAlex Deucher /*define for src_ha field*/ 115aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2 116aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask 0x00000001 117aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift 30 118aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift) 119aaa36a97SAlex Deucher 120aaa36a97SAlex Deucher /*define for SRC_ADDR_LO word*/ 121aaa36a97SAlex Deucher /*define for src_addr_31_0 field*/ 122aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 123aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 124aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 125aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 126aaa36a97SAlex Deucher 127aaa36a97SAlex Deucher /*define for SRC_ADDR_HI word*/ 128aaa36a97SAlex Deucher /*define for src_addr_63_32 field*/ 129aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 130aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 131aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 132aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 133aaa36a97SAlex Deucher 134aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 135aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 136aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 137aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 138aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 139aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 140aaa36a97SAlex Deucher 141aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 142aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 143aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 144aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 145aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 146aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 147aaa36a97SAlex Deucher 148aaa36a97SAlex Deucher 149aaa36a97SAlex Deucher /* 150aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 151aaa36a97SAlex Deucher */ 152aaa36a97SAlex Deucher 153aaa36a97SAlex Deucher /*define for HEADER word*/ 154aaa36a97SAlex Deucher /*define for op field*/ 155aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 156aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 157aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 158aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 159aaa36a97SAlex Deucher 160aaa36a97SAlex Deucher /*define for sub_op field*/ 161aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 162aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 163aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 164aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 165aaa36a97SAlex Deucher 166aaa36a97SAlex Deucher /*define for broadcast field*/ 167aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 168aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 169aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 170aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 171aaa36a97SAlex Deucher 172aaa36a97SAlex Deucher /*define for COUNT word*/ 173aaa36a97SAlex Deucher /*define for count field*/ 174aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 175aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 176aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 177aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 178aaa36a97SAlex Deucher 179aaa36a97SAlex Deucher /*define for PARAMETER word*/ 180aaa36a97SAlex Deucher /*define for dst2_sw field*/ 181aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 182aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 183aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 184aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 185aaa36a97SAlex Deucher 186aaa36a97SAlex Deucher /*define for dst2_ha field*/ 187aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2 188aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask 0x00000001 189aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift 14 190aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift) 191aaa36a97SAlex Deucher 192aaa36a97SAlex Deucher /*define for dst1_sw field*/ 193aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 194aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 195aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 196aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 197aaa36a97SAlex Deucher 198aaa36a97SAlex Deucher /*define for dst1_ha field*/ 199aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2 200aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask 0x00000001 201aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift 22 202aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift) 203aaa36a97SAlex Deucher 204aaa36a97SAlex Deucher /*define for src_sw field*/ 205aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 206aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 207aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 208aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 209aaa36a97SAlex Deucher 210aaa36a97SAlex Deucher /*define for src_ha field*/ 211aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2 212aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask 0x00000001 213aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift 30 214aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift) 215aaa36a97SAlex Deucher 216aaa36a97SAlex Deucher /*define for SRC_ADDR_LO word*/ 217aaa36a97SAlex Deucher /*define for src_addr_31_0 field*/ 218aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 219aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 220aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 221aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 222aaa36a97SAlex Deucher 223aaa36a97SAlex Deucher /*define for SRC_ADDR_HI word*/ 224aaa36a97SAlex Deucher /*define for src_addr_63_32 field*/ 225aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 226aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 227aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 228aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 229aaa36a97SAlex Deucher 230aaa36a97SAlex Deucher /*define for DST1_ADDR_LO word*/ 231aaa36a97SAlex Deucher /*define for dst1_addr_31_0 field*/ 232aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 233aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 234aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 235aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 236aaa36a97SAlex Deucher 237aaa36a97SAlex Deucher /*define for DST1_ADDR_HI word*/ 238aaa36a97SAlex Deucher /*define for dst1_addr_63_32 field*/ 239aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 240aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 241aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 242aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 243aaa36a97SAlex Deucher 244aaa36a97SAlex Deucher /*define for DST2_ADDR_LO word*/ 245aaa36a97SAlex Deucher /*define for dst2_addr_31_0 field*/ 246aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 247aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 248aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 249aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 250aaa36a97SAlex Deucher 251aaa36a97SAlex Deucher /*define for DST2_ADDR_HI word*/ 252aaa36a97SAlex Deucher /*define for dst2_addr_63_32 field*/ 253aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 254aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 255aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 256aaa36a97SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 257aaa36a97SAlex Deucher 258aaa36a97SAlex Deucher 259aaa36a97SAlex Deucher /* 260aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 261aaa36a97SAlex Deucher */ 262aaa36a97SAlex Deucher 263aaa36a97SAlex Deucher /*define for HEADER word*/ 264aaa36a97SAlex Deucher /*define for op field*/ 265aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 266aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 267aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 268aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 269aaa36a97SAlex Deucher 270aaa36a97SAlex Deucher /*define for sub_op field*/ 271aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 272aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 273aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 274aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 275aaa36a97SAlex Deucher 276aaa36a97SAlex Deucher /*define for elementsize field*/ 277aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 278aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 279aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 280aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 281aaa36a97SAlex Deucher 282aaa36a97SAlex Deucher /*define for SRC_ADDR_LO word*/ 283aaa36a97SAlex Deucher /*define for src_addr_31_0 field*/ 284aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 285aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 286aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 287aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 288aaa36a97SAlex Deucher 289aaa36a97SAlex Deucher /*define for SRC_ADDR_HI word*/ 290aaa36a97SAlex Deucher /*define for src_addr_63_32 field*/ 291aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 292aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 293aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 294aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 295aaa36a97SAlex Deucher 296aaa36a97SAlex Deucher /*define for DW_3 word*/ 297aaa36a97SAlex Deucher /*define for src_x field*/ 298aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 299aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 300aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 301aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 302aaa36a97SAlex Deucher 303aaa36a97SAlex Deucher /*define for src_y field*/ 304aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 305aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 306aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 307aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 308aaa36a97SAlex Deucher 309aaa36a97SAlex Deucher /*define for DW_4 word*/ 310aaa36a97SAlex Deucher /*define for src_z field*/ 311aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 312aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF 313aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 314aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 315aaa36a97SAlex Deucher 316aaa36a97SAlex Deucher /*define for src_pitch field*/ 317aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 318aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x00003FFF 319aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 16 320aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 321aaa36a97SAlex Deucher 322aaa36a97SAlex Deucher /*define for DW_5 word*/ 323aaa36a97SAlex Deucher /*define for src_slice_pitch field*/ 324aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 325aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 326aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 327aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 328aaa36a97SAlex Deucher 329aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 330aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 331aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 332aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 333aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 334aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 335aaa36a97SAlex Deucher 336aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 337aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 338aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 339aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 340aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 341aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 342aaa36a97SAlex Deucher 343aaa36a97SAlex Deucher /*define for DW_8 word*/ 344aaa36a97SAlex Deucher /*define for dst_x field*/ 345aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 346aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 347aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 348aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 349aaa36a97SAlex Deucher 350aaa36a97SAlex Deucher /*define for dst_y field*/ 351aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 352aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 353aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 354aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 355aaa36a97SAlex Deucher 356aaa36a97SAlex Deucher /*define for DW_9 word*/ 357aaa36a97SAlex Deucher /*define for dst_z field*/ 358aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 359aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF 360aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 361aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 362aaa36a97SAlex Deucher 363aaa36a97SAlex Deucher /*define for dst_pitch field*/ 364aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 365aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x00003FFF 366aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 16 367aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 368aaa36a97SAlex Deucher 369aaa36a97SAlex Deucher /*define for DW_10 word*/ 370aaa36a97SAlex Deucher /*define for dst_slice_pitch field*/ 371aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 372aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 373aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 374aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 375aaa36a97SAlex Deucher 376aaa36a97SAlex Deucher /*define for DW_11 word*/ 377aaa36a97SAlex Deucher /*define for rect_x field*/ 378aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 379aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 380aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 381aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 382aaa36a97SAlex Deucher 383aaa36a97SAlex Deucher /*define for rect_y field*/ 384aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 385aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 386aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 387aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 388aaa36a97SAlex Deucher 389aaa36a97SAlex Deucher /*define for DW_12 word*/ 390aaa36a97SAlex Deucher /*define for rect_z field*/ 391aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 392aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF 393aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 394aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 395aaa36a97SAlex Deucher 396aaa36a97SAlex Deucher /*define for dst_sw field*/ 397aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 398aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 399aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 400aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 401aaa36a97SAlex Deucher 402aaa36a97SAlex Deucher /*define for dst_ha field*/ 403aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12 404aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask 0x00000001 405aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift 22 406aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift) 407aaa36a97SAlex Deucher 408aaa36a97SAlex Deucher /*define for src_sw field*/ 409aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 410aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 411aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 412aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 413aaa36a97SAlex Deucher 414aaa36a97SAlex Deucher /*define for src_ha field*/ 415aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12 416aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask 0x00000001 417aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift 30 418aaa36a97SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift) 419aaa36a97SAlex Deucher 420aaa36a97SAlex Deucher 421aaa36a97SAlex Deucher /* 422aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_TILED packet 423aaa36a97SAlex Deucher */ 424aaa36a97SAlex Deucher 425aaa36a97SAlex Deucher /*define for HEADER word*/ 426aaa36a97SAlex Deucher /*define for op field*/ 427aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 428aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 429aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 430aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 431aaa36a97SAlex Deucher 432aaa36a97SAlex Deucher /*define for sub_op field*/ 433aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 434aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 435aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 436aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 437aaa36a97SAlex Deucher 438aaa36a97SAlex Deucher /*define for detile field*/ 439aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 440aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 441aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 442aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 443aaa36a97SAlex Deucher 444aaa36a97SAlex Deucher /*define for TILED_ADDR_LO word*/ 445aaa36a97SAlex Deucher /*define for tiled_addr_31_0 field*/ 446aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 447aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 448aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 449aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 450aaa36a97SAlex Deucher 451aaa36a97SAlex Deucher /*define for TILED_ADDR_HI word*/ 452aaa36a97SAlex Deucher /*define for tiled_addr_63_32 field*/ 453aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 454aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 455aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 456aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 457aaa36a97SAlex Deucher 458aaa36a97SAlex Deucher /*define for DW_3 word*/ 459aaa36a97SAlex Deucher /*define for pitch_in_tile field*/ 460aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3 461aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask 0x000007FF 462aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift 0 463aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift) 464aaa36a97SAlex Deucher 465aaa36a97SAlex Deucher /*define for height field*/ 466aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_height_offset 3 467aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_height_mask 0x00003FFF 468aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_height_shift 16 469aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift) 470aaa36a97SAlex Deucher 471aaa36a97SAlex Deucher /*define for DW_4 word*/ 472aaa36a97SAlex Deucher /*define for slice_pitch field*/ 473aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4 474aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask 0x003FFFFF 475aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift 0 476aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift) 477aaa36a97SAlex Deucher 478aaa36a97SAlex Deucher /*define for DW_5 word*/ 479aaa36a97SAlex Deucher /*define for element_size field*/ 480aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 481aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 482aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 483aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 484aaa36a97SAlex Deucher 485aaa36a97SAlex Deucher /*define for array_mode field*/ 486aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5 487aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask 0x0000000F 488aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift 3 489aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift) 490aaa36a97SAlex Deucher 491aaa36a97SAlex Deucher /*define for mit_mode field*/ 492aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5 493aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask 0x00000007 494aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift 8 495aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift) 496aaa36a97SAlex Deucher 497aaa36a97SAlex Deucher /*define for tilesplit_size field*/ 498aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5 499aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask 0x00000007 500aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift 11 501aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift) 502aaa36a97SAlex Deucher 503aaa36a97SAlex Deucher /*define for bank_w field*/ 504aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5 505aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask 0x00000003 506aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift 15 507aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift) 508aaa36a97SAlex Deucher 509aaa36a97SAlex Deucher /*define for bank_h field*/ 510aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5 511aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask 0x00000003 512aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift 18 513aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift) 514aaa36a97SAlex Deucher 515aaa36a97SAlex Deucher /*define for num_bank field*/ 516aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5 517aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask 0x00000003 518aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift 21 519aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift) 520aaa36a97SAlex Deucher 521aaa36a97SAlex Deucher /*define for mat_aspt field*/ 522aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5 523aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask 0x00000003 524aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift 24 525aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift) 526aaa36a97SAlex Deucher 527aaa36a97SAlex Deucher /*define for pipe_config field*/ 528aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5 529aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask 0x0000001F 530aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift 26 531aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift) 532aaa36a97SAlex Deucher 533aaa36a97SAlex Deucher /*define for DW_6 word*/ 534aaa36a97SAlex Deucher /*define for x field*/ 535aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 536aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 537aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 538aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 539aaa36a97SAlex Deucher 540aaa36a97SAlex Deucher /*define for y field*/ 541aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 542aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 543aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 544aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 545aaa36a97SAlex Deucher 546aaa36a97SAlex Deucher /*define for DW_7 word*/ 547aaa36a97SAlex Deucher /*define for z field*/ 548aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 549aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00000FFF 550aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 551aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 552aaa36a97SAlex Deucher 553aaa36a97SAlex Deucher /*define for linear_sw field*/ 554aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 555aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 556aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 557aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 558aaa36a97SAlex Deucher 559aaa36a97SAlex Deucher /*define for tile_sw field*/ 560aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 561aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 562aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 563aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 564aaa36a97SAlex Deucher 565aaa36a97SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 566aaa36a97SAlex Deucher /*define for linear_addr_31_0 field*/ 567aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 568aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 569aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 570aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 571aaa36a97SAlex Deucher 572aaa36a97SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 573aaa36a97SAlex Deucher /*define for linear_addr_63_32 field*/ 574aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 575aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 576aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 577aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 578aaa36a97SAlex Deucher 579aaa36a97SAlex Deucher /*define for LINEAR_PITCH word*/ 580aaa36a97SAlex Deucher /*define for linear_pitch field*/ 581aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 582aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 583aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 584aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 585aaa36a97SAlex Deucher 586aaa36a97SAlex Deucher /*define for COUNT word*/ 587aaa36a97SAlex Deucher /*define for count field*/ 588aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_count_offset 11 589aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF 590aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 591aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 592aaa36a97SAlex Deucher 593aaa36a97SAlex Deucher 594aaa36a97SAlex Deucher /* 595aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 596aaa36a97SAlex Deucher */ 597aaa36a97SAlex Deucher 598aaa36a97SAlex Deucher /*define for HEADER word*/ 599aaa36a97SAlex Deucher /*define for op field*/ 600aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 601aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 602aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 603aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 604aaa36a97SAlex Deucher 605aaa36a97SAlex Deucher /*define for sub_op field*/ 606aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 607aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 608aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 609aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 610aaa36a97SAlex Deucher 611aaa36a97SAlex Deucher /*define for videocopy field*/ 612aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 613aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 614aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 615aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 616aaa36a97SAlex Deucher 617aaa36a97SAlex Deucher /*define for broadcast field*/ 618aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 619aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 620aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 621aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 622aaa36a97SAlex Deucher 623aaa36a97SAlex Deucher /*define for TILED_ADDR_LO_0 word*/ 624aaa36a97SAlex Deucher /*define for tiled_addr0_31_0 field*/ 625aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 626aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 627aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 628aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 629aaa36a97SAlex Deucher 630aaa36a97SAlex Deucher /*define for TILED_ADDR_HI_0 word*/ 631aaa36a97SAlex Deucher /*define for tiled_addr0_63_32 field*/ 632aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 633aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 634aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 635aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 636aaa36a97SAlex Deucher 637aaa36a97SAlex Deucher /*define for TILED_ADDR_LO_1 word*/ 638aaa36a97SAlex Deucher /*define for tiled_addr1_31_0 field*/ 639aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 640aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 641aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 642aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 643aaa36a97SAlex Deucher 644aaa36a97SAlex Deucher /*define for TILED_ADDR_HI_1 word*/ 645aaa36a97SAlex Deucher /*define for tiled_addr1_63_32 field*/ 646aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 647aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 648aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 649aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 650aaa36a97SAlex Deucher 651aaa36a97SAlex Deucher /*define for DW_5 word*/ 652aaa36a97SAlex Deucher /*define for pitch_in_tile field*/ 653aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5 654aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask 0x000007FF 655aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift 0 656aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift) 657aaa36a97SAlex Deucher 658aaa36a97SAlex Deucher /*define for height field*/ 659aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5 660aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask 0x00003FFF 661aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift 16 662aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift) 663aaa36a97SAlex Deucher 664aaa36a97SAlex Deucher /*define for DW_6 word*/ 665aaa36a97SAlex Deucher /*define for slice_pitch field*/ 666aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6 667aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask 0x003FFFFF 668aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift 0 669aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift) 670aaa36a97SAlex Deucher 671aaa36a97SAlex Deucher /*define for DW_7 word*/ 672aaa36a97SAlex Deucher /*define for element_size field*/ 673aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 674aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 675aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 676aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 677aaa36a97SAlex Deucher 678aaa36a97SAlex Deucher /*define for array_mode field*/ 679aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7 680aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask 0x0000000F 681aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift 3 682aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift) 683aaa36a97SAlex Deucher 684aaa36a97SAlex Deucher /*define for mit_mode field*/ 685aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7 686aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask 0x00000007 687aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift 8 688aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift) 689aaa36a97SAlex Deucher 690aaa36a97SAlex Deucher /*define for tilesplit_size field*/ 691aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7 692aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask 0x00000007 693aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift 11 694aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift) 695aaa36a97SAlex Deucher 696aaa36a97SAlex Deucher /*define for bank_w field*/ 697aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7 698aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask 0x00000003 699aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift 15 700aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift) 701aaa36a97SAlex Deucher 702aaa36a97SAlex Deucher /*define for bank_h field*/ 703aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7 704aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask 0x00000003 705aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift 18 706aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift) 707aaa36a97SAlex Deucher 708aaa36a97SAlex Deucher /*define for num_bank field*/ 709aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7 710aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask 0x00000003 711aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift 21 712aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift) 713aaa36a97SAlex Deucher 714aaa36a97SAlex Deucher /*define for mat_aspt field*/ 715aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7 716aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask 0x00000003 717aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift 24 718aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift) 719aaa36a97SAlex Deucher 720aaa36a97SAlex Deucher /*define for pipe_config field*/ 721aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7 722aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask 0x0000001F 723aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift 26 724aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift) 725aaa36a97SAlex Deucher 726aaa36a97SAlex Deucher /*define for DW_8 word*/ 727aaa36a97SAlex Deucher /*define for x field*/ 728aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 729aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 730aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 731aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 732aaa36a97SAlex Deucher 733aaa36a97SAlex Deucher /*define for y field*/ 734aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 735aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 736aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 737aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 738aaa36a97SAlex Deucher 739aaa36a97SAlex Deucher /*define for DW_9 word*/ 740aaa36a97SAlex Deucher /*define for z field*/ 741aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 742aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00000FFF 743aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 744aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 745aaa36a97SAlex Deucher 746aaa36a97SAlex Deucher /*define for DW_10 word*/ 747aaa36a97SAlex Deucher /*define for dst2_sw field*/ 748aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 749aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 750aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 751aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 752aaa36a97SAlex Deucher 753aaa36a97SAlex Deucher /*define for dst2_ha field*/ 754aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10 755aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask 0x00000001 756aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift 14 757aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift) 758aaa36a97SAlex Deucher 759aaa36a97SAlex Deucher /*define for linear_sw field*/ 760aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 761aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 762aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 763aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 764aaa36a97SAlex Deucher 765aaa36a97SAlex Deucher /*define for tile_sw field*/ 766aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 767aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 768aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 769aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 770aaa36a97SAlex Deucher 771aaa36a97SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 772aaa36a97SAlex Deucher /*define for linear_addr_31_0 field*/ 773aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 774aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 775aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 776aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 777aaa36a97SAlex Deucher 778aaa36a97SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 779aaa36a97SAlex Deucher /*define for linear_addr_63_32 field*/ 780aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 781aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 782aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 783aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 784aaa36a97SAlex Deucher 785aaa36a97SAlex Deucher /*define for LINEAR_PITCH word*/ 786aaa36a97SAlex Deucher /*define for linear_pitch field*/ 787aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 788aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 789aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 790aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 791aaa36a97SAlex Deucher 792aaa36a97SAlex Deucher /*define for COUNT word*/ 793aaa36a97SAlex Deucher /*define for count field*/ 794aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14 795aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF 796aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 797aaa36a97SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 798aaa36a97SAlex Deucher 799aaa36a97SAlex Deucher 800aaa36a97SAlex Deucher /* 801aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_T2T packet 802aaa36a97SAlex Deucher */ 803aaa36a97SAlex Deucher 804aaa36a97SAlex Deucher /*define for HEADER word*/ 805aaa36a97SAlex Deucher /*define for op field*/ 806aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 807aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 808aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 809aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 810aaa36a97SAlex Deucher 811aaa36a97SAlex Deucher /*define for sub_op field*/ 812aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 813aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 814aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 815aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 816aaa36a97SAlex Deucher 817aaa36a97SAlex Deucher /*define for SRC_ADDR_LO word*/ 818aaa36a97SAlex Deucher /*define for src_addr_31_0 field*/ 819aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 820aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 821aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 822aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 823aaa36a97SAlex Deucher 824aaa36a97SAlex Deucher /*define for SRC_ADDR_HI word*/ 825aaa36a97SAlex Deucher /*define for src_addr_63_32 field*/ 826aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 827aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 828aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 829aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 830aaa36a97SAlex Deucher 831aaa36a97SAlex Deucher /*define for DW_3 word*/ 832aaa36a97SAlex Deucher /*define for src_x field*/ 833aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 834aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 835aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 836aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 837aaa36a97SAlex Deucher 838aaa36a97SAlex Deucher /*define for src_y field*/ 839aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 840aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 841aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 842aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 843aaa36a97SAlex Deucher 844aaa36a97SAlex Deucher /*define for DW_4 word*/ 845aaa36a97SAlex Deucher /*define for src_z field*/ 846aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 847aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF 848aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 849aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 850aaa36a97SAlex Deucher 851aaa36a97SAlex Deucher /*define for src_pitch_in_tile field*/ 852aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4 853aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask 0x00000FFF 854aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift 16 855aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift) 856aaa36a97SAlex Deucher 857aaa36a97SAlex Deucher /*define for DW_5 word*/ 858aaa36a97SAlex Deucher /*define for src_slice_pitch field*/ 859aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5 860aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask 0x003FFFFF 861aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift 0 862aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift) 863aaa36a97SAlex Deucher 864aaa36a97SAlex Deucher /*define for DW_6 word*/ 865aaa36a97SAlex Deucher /*define for src_element_size field*/ 866aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 867aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 868aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 869aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 870aaa36a97SAlex Deucher 871aaa36a97SAlex Deucher /*define for src_array_mode field*/ 872aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6 873aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask 0x0000000F 874aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift 3 875aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift) 876aaa36a97SAlex Deucher 877aaa36a97SAlex Deucher /*define for src_mit_mode field*/ 878aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6 879aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask 0x00000007 880aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift 8 881aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift) 882aaa36a97SAlex Deucher 883aaa36a97SAlex Deucher /*define for src_tilesplit_size field*/ 884aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6 885aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask 0x00000007 886aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift 11 887aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift) 888aaa36a97SAlex Deucher 889aaa36a97SAlex Deucher /*define for src_bank_w field*/ 890aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6 891aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask 0x00000003 892aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift 15 893aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift) 894aaa36a97SAlex Deucher 895aaa36a97SAlex Deucher /*define for src_bank_h field*/ 896aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6 897aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask 0x00000003 898aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift 18 899aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift) 900aaa36a97SAlex Deucher 901aaa36a97SAlex Deucher /*define for src_num_bank field*/ 902aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6 903aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask 0x00000003 904aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift 21 905aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift) 906aaa36a97SAlex Deucher 907aaa36a97SAlex Deucher /*define for src_mat_aspt field*/ 908aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6 909aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask 0x00000003 910aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift 24 911aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift) 912aaa36a97SAlex Deucher 913aaa36a97SAlex Deucher /*define for src_pipe_config field*/ 914aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6 915aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask 0x0000001F 916aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift 26 917aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift) 918aaa36a97SAlex Deucher 919aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 920aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 921aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 922aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 923aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 924aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 925aaa36a97SAlex Deucher 926aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 927aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 928aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 929aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 930aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 931aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 932aaa36a97SAlex Deucher 933aaa36a97SAlex Deucher /*define for DW_9 word*/ 934aaa36a97SAlex Deucher /*define for dst_x field*/ 935aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 936aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 937aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 938aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 939aaa36a97SAlex Deucher 940aaa36a97SAlex Deucher /*define for dst_y field*/ 941aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 942aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 943aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 944aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 945aaa36a97SAlex Deucher 946aaa36a97SAlex Deucher /*define for DW_10 word*/ 947aaa36a97SAlex Deucher /*define for dst_z field*/ 948aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 949aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF 950aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 951aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 952aaa36a97SAlex Deucher 953aaa36a97SAlex Deucher /*define for dst_pitch_in_tile field*/ 954aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10 955aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask 0x00000FFF 956aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift 16 957aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift) 958aaa36a97SAlex Deucher 959aaa36a97SAlex Deucher /*define for DW_11 word*/ 960aaa36a97SAlex Deucher /*define for dst_slice_pitch field*/ 961aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11 962aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask 0x003FFFFF 963aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift 0 964aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift) 965aaa36a97SAlex Deucher 966aaa36a97SAlex Deucher /*define for DW_12 word*/ 967aaa36a97SAlex Deucher /*define for dst_array_mode field*/ 968aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12 969aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask 0x0000000F 970aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift 3 971aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift) 972aaa36a97SAlex Deucher 973aaa36a97SAlex Deucher /*define for dst_mit_mode field*/ 974aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12 975aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask 0x00000007 976aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift 8 977aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift) 978aaa36a97SAlex Deucher 979aaa36a97SAlex Deucher /*define for dst_tilesplit_size field*/ 980aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12 981aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask 0x00000007 982aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift 11 983aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift) 984aaa36a97SAlex Deucher 985aaa36a97SAlex Deucher /*define for dst_bank_w field*/ 986aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12 987aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask 0x00000003 988aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift 15 989aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift) 990aaa36a97SAlex Deucher 991aaa36a97SAlex Deucher /*define for dst_bank_h field*/ 992aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12 993aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask 0x00000003 994aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift 18 995aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift) 996aaa36a97SAlex Deucher 997aaa36a97SAlex Deucher /*define for dst_num_bank field*/ 998aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12 999aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask 0x00000003 1000aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift 21 1001aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift) 1002aaa36a97SAlex Deucher 1003aaa36a97SAlex Deucher /*define for dst_mat_aspt field*/ 1004aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12 1005aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask 0x00000003 1006aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift 24 1007aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift) 1008aaa36a97SAlex Deucher 1009aaa36a97SAlex Deucher /*define for dst_pipe_config field*/ 1010aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12 1011aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask 0x0000001F 1012aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift 26 1013aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift) 1014aaa36a97SAlex Deucher 1015aaa36a97SAlex Deucher /*define for DW_13 word*/ 1016aaa36a97SAlex Deucher /*define for rect_x field*/ 1017aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 1018aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 1019aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 1020aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 1021aaa36a97SAlex Deucher 1022aaa36a97SAlex Deucher /*define for rect_y field*/ 1023aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 1024aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 1025aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 1026aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 1027aaa36a97SAlex Deucher 1028aaa36a97SAlex Deucher /*define for DW_14 word*/ 1029aaa36a97SAlex Deucher /*define for rect_z field*/ 1030aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 1031aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF 1032aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 1033aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 1034aaa36a97SAlex Deucher 1035aaa36a97SAlex Deucher /*define for dst_sw field*/ 1036aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 1037aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 1038aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 1039aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 1040aaa36a97SAlex Deucher 1041aaa36a97SAlex Deucher /*define for src_sw field*/ 1042aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 1043aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 1044aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 1045aaa36a97SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 1046aaa36a97SAlex Deucher 1047aaa36a97SAlex Deucher 1048aaa36a97SAlex Deucher /* 1049aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 1050aaa36a97SAlex Deucher */ 1051aaa36a97SAlex Deucher 1052aaa36a97SAlex Deucher /*define for HEADER word*/ 1053aaa36a97SAlex Deucher /*define for op field*/ 1054aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 1055aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 1056aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 1057aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 1058aaa36a97SAlex Deucher 1059aaa36a97SAlex Deucher /*define for sub_op field*/ 1060aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 1061aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 1062aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 1063aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 1064aaa36a97SAlex Deucher 1065aaa36a97SAlex Deucher /*define for detile field*/ 1066aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 1067aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 1068aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 1069aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 1070aaa36a97SAlex Deucher 1071aaa36a97SAlex Deucher /*define for TILED_ADDR_LO word*/ 1072aaa36a97SAlex Deucher /*define for tiled_addr_31_0 field*/ 1073aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1074aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1075aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1076aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 1077aaa36a97SAlex Deucher 1078aaa36a97SAlex Deucher /*define for TILED_ADDR_HI word*/ 1079aaa36a97SAlex Deucher /*define for tiled_addr_63_32 field*/ 1080aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1081aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1082aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1083aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 1084aaa36a97SAlex Deucher 1085aaa36a97SAlex Deucher /*define for DW_3 word*/ 1086aaa36a97SAlex Deucher /*define for tiled_x field*/ 1087aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 1088aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 1089aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 1090aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 1091aaa36a97SAlex Deucher 1092aaa36a97SAlex Deucher /*define for tiled_y field*/ 1093aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 1094aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 1095aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 1096aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 1097aaa36a97SAlex Deucher 1098aaa36a97SAlex Deucher /*define for DW_4 word*/ 1099aaa36a97SAlex Deucher /*define for tiled_z field*/ 1100aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 1101aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF 1102aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 1103aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 1104aaa36a97SAlex Deucher 1105aaa36a97SAlex Deucher /*define for pitch_in_tile field*/ 1106aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4 1107aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask 0x00000FFF 1108aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift 16 1109aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift) 1110aaa36a97SAlex Deucher 1111aaa36a97SAlex Deucher /*define for DW_5 word*/ 1112aaa36a97SAlex Deucher /*define for slice_pitch field*/ 1113aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5 1114aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask 0x003FFFFF 1115aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift 0 1116aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift) 1117aaa36a97SAlex Deucher 1118aaa36a97SAlex Deucher /*define for DW_6 word*/ 1119aaa36a97SAlex Deucher /*define for element_size field*/ 1120aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 1121aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 1122aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 1123aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 1124aaa36a97SAlex Deucher 1125aaa36a97SAlex Deucher /*define for array_mode field*/ 1126aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6 1127aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask 0x0000000F 1128aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift 3 1129aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift) 1130aaa36a97SAlex Deucher 1131aaa36a97SAlex Deucher /*define for mit_mode field*/ 1132aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6 1133aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask 0x00000007 1134aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift 8 1135aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift) 1136aaa36a97SAlex Deucher 1137aaa36a97SAlex Deucher /*define for tilesplit_size field*/ 1138aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6 1139aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask 0x00000007 1140aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift 11 1141aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift) 1142aaa36a97SAlex Deucher 1143aaa36a97SAlex Deucher /*define for bank_w field*/ 1144aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6 1145aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask 0x00000003 1146aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift 15 1147aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift) 1148aaa36a97SAlex Deucher 1149aaa36a97SAlex Deucher /*define for bank_h field*/ 1150aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6 1151aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask 0x00000003 1152aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift 18 1153aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift) 1154aaa36a97SAlex Deucher 1155aaa36a97SAlex Deucher /*define for num_bank field*/ 1156aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6 1157aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask 0x00000003 1158aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift 21 1159aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift) 1160aaa36a97SAlex Deucher 1161aaa36a97SAlex Deucher /*define for mat_aspt field*/ 1162aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6 1163aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask 0x00000003 1164aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift 24 1165aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift) 1166aaa36a97SAlex Deucher 1167aaa36a97SAlex Deucher /*define for pipe_config field*/ 1168aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6 1169aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask 0x0000001F 1170aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift 26 1171aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift) 1172aaa36a97SAlex Deucher 1173aaa36a97SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 1174aaa36a97SAlex Deucher /*define for linear_addr_31_0 field*/ 1175aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 1176aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1177aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1178aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1179aaa36a97SAlex Deucher 1180aaa36a97SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 1181aaa36a97SAlex Deucher /*define for linear_addr_63_32 field*/ 1182aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 1183aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1184aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1185aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1186aaa36a97SAlex Deucher 1187aaa36a97SAlex Deucher /*define for DW_9 word*/ 1188aaa36a97SAlex Deucher /*define for linear_x field*/ 1189aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 1190aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 1191aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 1192aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 1193aaa36a97SAlex Deucher 1194aaa36a97SAlex Deucher /*define for linear_y field*/ 1195aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 1196aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 1197aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 1198aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 1199aaa36a97SAlex Deucher 1200aaa36a97SAlex Deucher /*define for DW_10 word*/ 1201aaa36a97SAlex Deucher /*define for linear_z field*/ 1202aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 1203aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF 1204aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 1205aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 1206aaa36a97SAlex Deucher 1207aaa36a97SAlex Deucher /*define for linear_pitch field*/ 1208aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 1209aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 1210aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 1211aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 1212aaa36a97SAlex Deucher 1213aaa36a97SAlex Deucher /*define for DW_11 word*/ 1214aaa36a97SAlex Deucher /*define for linear_slice_pitch field*/ 1215aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 1216aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 1217aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 1218aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 1219aaa36a97SAlex Deucher 1220aaa36a97SAlex Deucher /*define for DW_12 word*/ 1221aaa36a97SAlex Deucher /*define for rect_x field*/ 1222aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 1223aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 1224aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 1225aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 1226aaa36a97SAlex Deucher 1227aaa36a97SAlex Deucher /*define for rect_y field*/ 1228aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 1229aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 1230aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 1231aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 1232aaa36a97SAlex Deucher 1233aaa36a97SAlex Deucher /*define for DW_13 word*/ 1234aaa36a97SAlex Deucher /*define for rect_z field*/ 1235aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 1236aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF 1237aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 1238aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 1239aaa36a97SAlex Deucher 1240aaa36a97SAlex Deucher /*define for linear_sw field*/ 1241aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 1242aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 1243aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 1244aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 1245aaa36a97SAlex Deucher 1246aaa36a97SAlex Deucher /*define for tile_sw field*/ 1247aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 1248aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 1249aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 1250aaa36a97SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 1251aaa36a97SAlex Deucher 1252aaa36a97SAlex Deucher 1253aaa36a97SAlex Deucher /* 1254aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COPY_STRUCT packet 1255aaa36a97SAlex Deucher */ 1256aaa36a97SAlex Deucher 1257aaa36a97SAlex Deucher /*define for HEADER word*/ 1258aaa36a97SAlex Deucher /*define for op field*/ 1259aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 1260aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 1261aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 1262aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 1263aaa36a97SAlex Deucher 1264aaa36a97SAlex Deucher /*define for sub_op field*/ 1265aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 1266aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 1267aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 1268aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 1269aaa36a97SAlex Deucher 1270aaa36a97SAlex Deucher /*define for detile field*/ 1271aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 1272aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 1273aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 1274aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 1275aaa36a97SAlex Deucher 1276aaa36a97SAlex Deucher /*define for SB_ADDR_LO word*/ 1277aaa36a97SAlex Deucher /*define for sb_addr_31_0 field*/ 1278aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 1279aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 1280aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 1281aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 1282aaa36a97SAlex Deucher 1283aaa36a97SAlex Deucher /*define for SB_ADDR_HI word*/ 1284aaa36a97SAlex Deucher /*define for sb_addr_63_32 field*/ 1285aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 1286aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 1287aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 1288aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 1289aaa36a97SAlex Deucher 1290aaa36a97SAlex Deucher /*define for START_INDEX word*/ 1291aaa36a97SAlex Deucher /*define for start_index field*/ 1292aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 1293aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 1294aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 1295aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 1296aaa36a97SAlex Deucher 1297aaa36a97SAlex Deucher /*define for COUNT word*/ 1298aaa36a97SAlex Deucher /*define for count field*/ 1299aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 1300aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 1301aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 1302aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 1303aaa36a97SAlex Deucher 1304aaa36a97SAlex Deucher /*define for DW_5 word*/ 1305aaa36a97SAlex Deucher /*define for stride field*/ 1306aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 1307aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 1308aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 1309aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 1310aaa36a97SAlex Deucher 1311aaa36a97SAlex Deucher /*define for struct_sw field*/ 1312aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 1313aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 1314aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 16 1315aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 1316aaa36a97SAlex Deucher 1317aaa36a97SAlex Deucher /*define for struct_ha field*/ 1318aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5 1319aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask 0x00000001 1320aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift 22 1321aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift) 1322aaa36a97SAlex Deucher 1323aaa36a97SAlex Deucher /*define for linear_sw field*/ 1324aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 1325aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 1326aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 24 1327aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 1328aaa36a97SAlex Deucher 1329aaa36a97SAlex Deucher /*define for linear_ha field*/ 1330aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5 1331aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask 0x00000001 1332aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift 30 1333aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift) 1334aaa36a97SAlex Deucher 1335aaa36a97SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 1336aaa36a97SAlex Deucher /*define for linear_addr_31_0 field*/ 1337aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 1338aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1339aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1340aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1341aaa36a97SAlex Deucher 1342aaa36a97SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 1343aaa36a97SAlex Deucher /*define for linear_addr_63_32 field*/ 1344aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 1345aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1346aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1347aaa36a97SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1348aaa36a97SAlex Deucher 1349aaa36a97SAlex Deucher 1350aaa36a97SAlex Deucher /* 1351aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_WRITE_UNTILED packet 1352aaa36a97SAlex Deucher */ 1353aaa36a97SAlex Deucher 1354aaa36a97SAlex Deucher /*define for HEADER word*/ 1355aaa36a97SAlex Deucher /*define for op field*/ 1356aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 1357aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 1358aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 1359aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 1360aaa36a97SAlex Deucher 1361aaa36a97SAlex Deucher /*define for sub_op field*/ 1362aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 1363aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 1364aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 1365aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 1366aaa36a97SAlex Deucher 1367aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 1368aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 1369aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 1370aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1371aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 1372aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 1373aaa36a97SAlex Deucher 1374aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 1375aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 1376aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 1377aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1378aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 1379aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 1380aaa36a97SAlex Deucher 1381aaa36a97SAlex Deucher /*define for DW_3 word*/ 1382aaa36a97SAlex Deucher /*define for count field*/ 1383aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 1384aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x003FFFFF 1385aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 1386aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 1387aaa36a97SAlex Deucher 1388aaa36a97SAlex Deucher /*define for sw field*/ 1389aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 1390aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 1391aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 1392aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 1393aaa36a97SAlex Deucher 1394aaa36a97SAlex Deucher /*define for DATA0 word*/ 1395aaa36a97SAlex Deucher /*define for data0 field*/ 1396aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 1397aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 1398aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 1399aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 1400aaa36a97SAlex Deucher 1401aaa36a97SAlex Deucher 1402aaa36a97SAlex Deucher /* 1403aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_WRITE_TILED packet 1404aaa36a97SAlex Deucher */ 1405aaa36a97SAlex Deucher 1406aaa36a97SAlex Deucher /*define for HEADER word*/ 1407aaa36a97SAlex Deucher /*define for op field*/ 1408aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 1409aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 1410aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 1411aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 1412aaa36a97SAlex Deucher 1413aaa36a97SAlex Deucher /*define for sub_op field*/ 1414aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 1415aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 1416aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 1417aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 1418aaa36a97SAlex Deucher 1419aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 1420aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 1421aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 1422aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1423aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 1424aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 1425aaa36a97SAlex Deucher 1426aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 1427aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 1428aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 1429aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1430aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 1431aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 1432aaa36a97SAlex Deucher 1433aaa36a97SAlex Deucher /*define for DW_3 word*/ 1434aaa36a97SAlex Deucher /*define for pitch_in_tile field*/ 1435aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3 1436aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask 0x000007FF 1437aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift 0 1438aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift) 1439aaa36a97SAlex Deucher 1440aaa36a97SAlex Deucher /*define for height field*/ 1441aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3 1442aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_height_mask 0x00003FFF 1443aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_height_shift 16 1444aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift) 1445aaa36a97SAlex Deucher 1446aaa36a97SAlex Deucher /*define for DW_4 word*/ 1447aaa36a97SAlex Deucher /*define for slice_pitch field*/ 1448aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4 1449aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask 0x003FFFFF 1450aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift 0 1451aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift) 1452aaa36a97SAlex Deucher 1453aaa36a97SAlex Deucher /*define for DW_5 word*/ 1454aaa36a97SAlex Deucher /*define for element_size field*/ 1455aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 1456aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 1457aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 1458aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 1459aaa36a97SAlex Deucher 1460aaa36a97SAlex Deucher /*define for array_mode field*/ 1461aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5 1462aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask 0x0000000F 1463aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift 3 1464aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift) 1465aaa36a97SAlex Deucher 1466aaa36a97SAlex Deucher /*define for mit_mode field*/ 1467aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5 1468aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask 0x00000007 1469aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift 8 1470aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift) 1471aaa36a97SAlex Deucher 1472aaa36a97SAlex Deucher /*define for tilesplit_size field*/ 1473aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5 1474aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask 0x00000007 1475aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift 11 1476aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift) 1477aaa36a97SAlex Deucher 1478aaa36a97SAlex Deucher /*define for bank_w field*/ 1479aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5 1480aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask 0x00000003 1481aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift 15 1482aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift) 1483aaa36a97SAlex Deucher 1484aaa36a97SAlex Deucher /*define for bank_h field*/ 1485aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5 1486aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask 0x00000003 1487aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift 18 1488aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift) 1489aaa36a97SAlex Deucher 1490aaa36a97SAlex Deucher /*define for num_bank field*/ 1491aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5 1492aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask 0x00000003 1493aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift 21 1494aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift) 1495aaa36a97SAlex Deucher 1496aaa36a97SAlex Deucher /*define for mat_aspt field*/ 1497aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5 1498aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask 0x00000003 1499aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift 24 1500aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift) 1501aaa36a97SAlex Deucher 1502aaa36a97SAlex Deucher /*define for pipe_config field*/ 1503aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5 1504aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask 0x0000001F 1505aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift 26 1506aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift) 1507aaa36a97SAlex Deucher 1508aaa36a97SAlex Deucher /*define for DW_6 word*/ 1509aaa36a97SAlex Deucher /*define for x field*/ 1510aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 1511aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 1512aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 1513aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 1514aaa36a97SAlex Deucher 1515aaa36a97SAlex Deucher /*define for y field*/ 1516aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 1517aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 1518aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 1519aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 1520aaa36a97SAlex Deucher 1521aaa36a97SAlex Deucher /*define for DW_7 word*/ 1522aaa36a97SAlex Deucher /*define for z field*/ 1523aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 1524aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00000FFF 1525aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 1526aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 1527aaa36a97SAlex Deucher 1528aaa36a97SAlex Deucher /*define for sw field*/ 1529aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 1530aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 1531aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 1532aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 1533aaa36a97SAlex Deucher 1534aaa36a97SAlex Deucher /*define for COUNT word*/ 1535aaa36a97SAlex Deucher /*define for count field*/ 1536aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 1537aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x003FFFFF 1538aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 1539aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 1540aaa36a97SAlex Deucher 1541aaa36a97SAlex Deucher /*define for DATA0 word*/ 1542aaa36a97SAlex Deucher /*define for data0 field*/ 1543aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 1544aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 1545aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 1546aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 1547aaa36a97SAlex Deucher 1548aaa36a97SAlex Deucher 1549aaa36a97SAlex Deucher /* 1550aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_WRITE_INCR packet 1551aaa36a97SAlex Deucher */ 1552aaa36a97SAlex Deucher 1553aaa36a97SAlex Deucher /*define for HEADER word*/ 1554aaa36a97SAlex Deucher /*define for op field*/ 1555aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 1556aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 1557aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 1558aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 1559aaa36a97SAlex Deucher 1560aaa36a97SAlex Deucher /*define for sub_op field*/ 1561aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 1562aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 1563aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 1564aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 1565aaa36a97SAlex Deucher 1566aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 1567aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 1568aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 1569aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1570aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 1571aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 1572aaa36a97SAlex Deucher 1573aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 1574aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 1575aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 1576aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1577aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 1578aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 1579aaa36a97SAlex Deucher 1580aaa36a97SAlex Deucher /*define for MASK_DW0 word*/ 1581aaa36a97SAlex Deucher /*define for mask_dw0 field*/ 1582aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 1583aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 1584aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 1585aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 1586aaa36a97SAlex Deucher 1587aaa36a97SAlex Deucher /*define for MASK_DW1 word*/ 1588aaa36a97SAlex Deucher /*define for mask_dw1 field*/ 1589aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 1590aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 1591aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 1592aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 1593aaa36a97SAlex Deucher 1594aaa36a97SAlex Deucher /*define for INIT_DW0 word*/ 1595aaa36a97SAlex Deucher /*define for init_dw0 field*/ 1596aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 1597aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 1598aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 1599aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 1600aaa36a97SAlex Deucher 1601aaa36a97SAlex Deucher /*define for INIT_DW1 word*/ 1602aaa36a97SAlex Deucher /*define for init_dw1 field*/ 1603aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 1604aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 1605aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 1606aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 1607aaa36a97SAlex Deucher 1608aaa36a97SAlex Deucher /*define for INCR_DW0 word*/ 1609aaa36a97SAlex Deucher /*define for incr_dw0 field*/ 1610aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 1611aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 1612aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 1613aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 1614aaa36a97SAlex Deucher 1615aaa36a97SAlex Deucher /*define for INCR_DW1 word*/ 1616aaa36a97SAlex Deucher /*define for incr_dw1 field*/ 1617aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 1618aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 1619aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 1620aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 1621aaa36a97SAlex Deucher 1622aaa36a97SAlex Deucher /*define for COUNT word*/ 1623aaa36a97SAlex Deucher /*define for count field*/ 1624aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 1625aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 1626aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 1627aaa36a97SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 1628aaa36a97SAlex Deucher 1629aaa36a97SAlex Deucher 1630aaa36a97SAlex Deucher /* 1631aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_INDIRECT packet 1632aaa36a97SAlex Deucher */ 1633aaa36a97SAlex Deucher 1634aaa36a97SAlex Deucher /*define for HEADER word*/ 1635aaa36a97SAlex Deucher /*define for op field*/ 1636aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 1637aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 1638aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 1639aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 1640aaa36a97SAlex Deucher 1641aaa36a97SAlex Deucher /*define for sub_op field*/ 1642aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 1643aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 1644aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 1645aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 1646aaa36a97SAlex Deucher 1647aaa36a97SAlex Deucher /*define for vmid field*/ 1648aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 1649aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 1650aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 1651aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 1652aaa36a97SAlex Deucher 1653aaa36a97SAlex Deucher /*define for BASE_LO word*/ 1654aaa36a97SAlex Deucher /*define for ib_base_31_0 field*/ 1655aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 1656aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 1657aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 1658aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 1659aaa36a97SAlex Deucher 1660aaa36a97SAlex Deucher /*define for BASE_HI word*/ 1661aaa36a97SAlex Deucher /*define for ib_base_63_32 field*/ 1662aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 1663aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 1664aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 1665aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 1666aaa36a97SAlex Deucher 1667aaa36a97SAlex Deucher /*define for IB_SIZE word*/ 1668aaa36a97SAlex Deucher /*define for ib_size field*/ 1669aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 1670aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 1671aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 1672aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 1673aaa36a97SAlex Deucher 1674aaa36a97SAlex Deucher /*define for CSA_ADDR_LO word*/ 1675aaa36a97SAlex Deucher /*define for csa_addr_31_0 field*/ 1676aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 1677aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 1678aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 1679aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 1680aaa36a97SAlex Deucher 1681aaa36a97SAlex Deucher /*define for CSA_ADDR_HI word*/ 1682aaa36a97SAlex Deucher /*define for csa_addr_63_32 field*/ 1683aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 1684aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 1685aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 1686aaa36a97SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 1687aaa36a97SAlex Deucher 1688aaa36a97SAlex Deucher 1689aaa36a97SAlex Deucher /* 1690aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_SEMAPHORE packet 1691aaa36a97SAlex Deucher */ 1692aaa36a97SAlex Deucher 1693aaa36a97SAlex Deucher /*define for HEADER word*/ 1694aaa36a97SAlex Deucher /*define for op field*/ 1695aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 1696aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 1697aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 1698aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 1699aaa36a97SAlex Deucher 1700aaa36a97SAlex Deucher /*define for sub_op field*/ 1701aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 1702aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 1703aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 1704aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 1705aaa36a97SAlex Deucher 1706aaa36a97SAlex Deucher /*define for write_one field*/ 1707aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 1708aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 1709aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 1710aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 1711aaa36a97SAlex Deucher 1712aaa36a97SAlex Deucher /*define for signal field*/ 1713aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 1714aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 1715aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 1716aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 1717aaa36a97SAlex Deucher 1718aaa36a97SAlex Deucher /*define for mailbox field*/ 1719aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 1720aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 1721aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 1722aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 1723aaa36a97SAlex Deucher 1724aaa36a97SAlex Deucher /*define for ADDR_LO word*/ 1725aaa36a97SAlex Deucher /*define for addr_31_0 field*/ 1726aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 1727aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1728aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 1729aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 1730aaa36a97SAlex Deucher 1731aaa36a97SAlex Deucher /*define for ADDR_HI word*/ 1732aaa36a97SAlex Deucher /*define for addr_63_32 field*/ 1733aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 1734aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1735aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 1736aaa36a97SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 1737aaa36a97SAlex Deucher 1738aaa36a97SAlex Deucher 1739aaa36a97SAlex Deucher /* 1740aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_FENCE packet 1741aaa36a97SAlex Deucher */ 1742aaa36a97SAlex Deucher 1743aaa36a97SAlex Deucher /*define for HEADER word*/ 1744aaa36a97SAlex Deucher /*define for op field*/ 1745aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_op_offset 0 1746aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 1747aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_op_shift 0 1748aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 1749aaa36a97SAlex Deucher 1750aaa36a97SAlex Deucher /*define for sub_op field*/ 1751aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 1752aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 1753aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 1754aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 1755aaa36a97SAlex Deucher 1756aaa36a97SAlex Deucher /*define for ADDR_LO word*/ 1757aaa36a97SAlex Deucher /*define for addr_31_0 field*/ 1758aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 1759aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1760aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 1761aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 1762aaa36a97SAlex Deucher 1763aaa36a97SAlex Deucher /*define for ADDR_HI word*/ 1764aaa36a97SAlex Deucher /*define for addr_63_32 field*/ 1765aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 1766aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1767aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 1768aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 1769aaa36a97SAlex Deucher 1770aaa36a97SAlex Deucher /*define for DATA word*/ 1771aaa36a97SAlex Deucher /*define for data field*/ 1772aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_DATA_data_offset 3 1773aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 1774aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_DATA_data_shift 0 1775aaa36a97SAlex Deucher #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 1776aaa36a97SAlex Deucher 1777aaa36a97SAlex Deucher 1778aaa36a97SAlex Deucher /* 1779aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_SRBM_WRITE packet 1780aaa36a97SAlex Deucher */ 1781aaa36a97SAlex Deucher 1782aaa36a97SAlex Deucher /*define for HEADER word*/ 1783aaa36a97SAlex Deucher /*define for op field*/ 1784aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 1785aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 1786aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 1787aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 1788aaa36a97SAlex Deucher 1789aaa36a97SAlex Deucher /*define for sub_op field*/ 1790aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 1791aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 1792aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 1793aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 1794aaa36a97SAlex Deucher 1795aaa36a97SAlex Deucher /*define for byte_en field*/ 1796aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 1797aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 1798aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 1799aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 1800aaa36a97SAlex Deucher 1801aaa36a97SAlex Deucher /*define for ADDR word*/ 1802aaa36a97SAlex Deucher /*define for addr field*/ 1803aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 1804aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0000FFFF 1805aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 1806aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 1807aaa36a97SAlex Deucher 1808aaa36a97SAlex Deucher /*define for DATA word*/ 1809aaa36a97SAlex Deucher /*define for data field*/ 1810aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 1811aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 1812aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 1813aaa36a97SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 1814aaa36a97SAlex Deucher 1815aaa36a97SAlex Deucher 1816aaa36a97SAlex Deucher /* 1817aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_PRE_EXE packet 1818aaa36a97SAlex Deucher */ 1819aaa36a97SAlex Deucher 1820aaa36a97SAlex Deucher /*define for HEADER word*/ 1821aaa36a97SAlex Deucher /*define for op field*/ 1822aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 1823aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 1824aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 1825aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 1826aaa36a97SAlex Deucher 1827aaa36a97SAlex Deucher /*define for sub_op field*/ 1828aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 1829aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 1830aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 1831aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 1832aaa36a97SAlex Deucher 1833aaa36a97SAlex Deucher /*define for dev_sel field*/ 1834aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 1835aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 1836aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 1837aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 1838aaa36a97SAlex Deucher 1839aaa36a97SAlex Deucher /*define for EXEC_COUNT word*/ 1840aaa36a97SAlex Deucher /*define for exec_count field*/ 1841aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 1842aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 1843aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 1844aaa36a97SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 1845aaa36a97SAlex Deucher 1846aaa36a97SAlex Deucher 1847aaa36a97SAlex Deucher /* 1848aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_COND_EXE packet 1849aaa36a97SAlex Deucher */ 1850aaa36a97SAlex Deucher 1851aaa36a97SAlex Deucher /*define for HEADER word*/ 1852aaa36a97SAlex Deucher /*define for op field*/ 1853aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 1854aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 1855aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 1856aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 1857aaa36a97SAlex Deucher 1858aaa36a97SAlex Deucher /*define for sub_op field*/ 1859aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 1860aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 1861aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 1862aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 1863aaa36a97SAlex Deucher 1864aaa36a97SAlex Deucher /*define for ADDR_LO word*/ 1865aaa36a97SAlex Deucher /*define for addr_31_0 field*/ 1866aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 1867aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1868aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 1869aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 1870aaa36a97SAlex Deucher 1871aaa36a97SAlex Deucher /*define for ADDR_HI word*/ 1872aaa36a97SAlex Deucher /*define for addr_63_32 field*/ 1873aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 1874aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1875aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 1876aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 1877aaa36a97SAlex Deucher 1878aaa36a97SAlex Deucher /*define for REFERENCE word*/ 1879aaa36a97SAlex Deucher /*define for reference field*/ 1880aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 1881aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 1882aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 1883aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 1884aaa36a97SAlex Deucher 1885aaa36a97SAlex Deucher /*define for EXEC_COUNT word*/ 1886aaa36a97SAlex Deucher /*define for exec_count field*/ 1887aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 1888aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 1889aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 1890aaa36a97SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 1891aaa36a97SAlex Deucher 1892aaa36a97SAlex Deucher 1893aaa36a97SAlex Deucher /* 1894aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_CONSTANT_FILL packet 1895aaa36a97SAlex Deucher */ 1896aaa36a97SAlex Deucher 1897aaa36a97SAlex Deucher /*define for HEADER word*/ 1898aaa36a97SAlex Deucher /*define for op field*/ 1899aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 1900aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 1901aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 1902aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 1903aaa36a97SAlex Deucher 1904aaa36a97SAlex Deucher /*define for sub_op field*/ 1905aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 1906aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 1907aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 1908aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 1909aaa36a97SAlex Deucher 1910aaa36a97SAlex Deucher /*define for sw field*/ 1911aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 1912aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 1913aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 1914aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 1915aaa36a97SAlex Deucher 1916aaa36a97SAlex Deucher /*define for fillsize field*/ 1917aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 1918aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 1919aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 1920aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 1921aaa36a97SAlex Deucher 1922aaa36a97SAlex Deucher /*define for DST_ADDR_LO word*/ 1923aaa36a97SAlex Deucher /*define for dst_addr_31_0 field*/ 1924aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 1925aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1926aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 1927aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 1928aaa36a97SAlex Deucher 1929aaa36a97SAlex Deucher /*define for DST_ADDR_HI word*/ 1930aaa36a97SAlex Deucher /*define for dst_addr_63_32 field*/ 1931aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 1932aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1933aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 1934aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 1935aaa36a97SAlex Deucher 1936aaa36a97SAlex Deucher /*define for DATA word*/ 1937aaa36a97SAlex Deucher /*define for src_data_31_0 field*/ 1938aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 1939aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 1940aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 1941aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 1942aaa36a97SAlex Deucher 1943aaa36a97SAlex Deucher /*define for COUNT word*/ 1944aaa36a97SAlex Deucher /*define for count field*/ 1945aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 1946aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 1947aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 1948aaa36a97SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 1949aaa36a97SAlex Deucher 1950aaa36a97SAlex Deucher 1951aaa36a97SAlex Deucher /* 1952aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_POLL_REGMEM packet 1953aaa36a97SAlex Deucher */ 1954aaa36a97SAlex Deucher 1955aaa36a97SAlex Deucher /*define for HEADER word*/ 1956aaa36a97SAlex Deucher /*define for op field*/ 1957aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 1958aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 1959aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 1960aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 1961aaa36a97SAlex Deucher 1962aaa36a97SAlex Deucher /*define for sub_op field*/ 1963aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 1964aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 1965aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 1966aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 1967aaa36a97SAlex Deucher 1968aaa36a97SAlex Deucher /*define for hdp_flush field*/ 1969aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 1970aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 1971aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 1972aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 1973aaa36a97SAlex Deucher 1974aaa36a97SAlex Deucher /*define for func field*/ 1975aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 1976aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 1977aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 1978aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 1979aaa36a97SAlex Deucher 1980aaa36a97SAlex Deucher /*define for mem_poll field*/ 1981aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 1982aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 1983aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 1984aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 1985aaa36a97SAlex Deucher 1986aaa36a97SAlex Deucher /*define for ADDR_LO word*/ 1987aaa36a97SAlex Deucher /*define for addr_31_0 field*/ 1988aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 1989aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1990aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 1991aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 1992aaa36a97SAlex Deucher 1993aaa36a97SAlex Deucher /*define for ADDR_HI word*/ 1994aaa36a97SAlex Deucher /*define for addr_63_32 field*/ 1995aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 1996aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1997aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 1998aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 1999aaa36a97SAlex Deucher 2000aaa36a97SAlex Deucher /*define for VALUE word*/ 2001aaa36a97SAlex Deucher /*define for value field*/ 2002aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 2003aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 2004aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 2005aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 2006aaa36a97SAlex Deucher 2007aaa36a97SAlex Deucher /*define for MASK word*/ 2008aaa36a97SAlex Deucher /*define for mask field*/ 2009aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 2010aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 2011aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 2012aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 2013aaa36a97SAlex Deucher 2014aaa36a97SAlex Deucher /*define for DW5 word*/ 2015aaa36a97SAlex Deucher /*define for interval field*/ 2016aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 2017aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 2018aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 2019aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 2020aaa36a97SAlex Deucher 2021aaa36a97SAlex Deucher /*define for retry_count field*/ 2022aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 2023aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 2024aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 2025aaa36a97SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 2026aaa36a97SAlex Deucher 2027aaa36a97SAlex Deucher 2028aaa36a97SAlex Deucher /* 2029aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_ATOMIC packet 2030aaa36a97SAlex Deucher */ 2031aaa36a97SAlex Deucher 2032aaa36a97SAlex Deucher /*define for HEADER word*/ 2033aaa36a97SAlex Deucher /*define for op field*/ 2034aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 2035aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 2036aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 2037aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 2038aaa36a97SAlex Deucher 2039aaa36a97SAlex Deucher /*define for loop field*/ 2040aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 2041aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 2042aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 2043aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 2044aaa36a97SAlex Deucher 2045aaa36a97SAlex Deucher /*define for atomic_op field*/ 2046aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 2047aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 2048aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 2049aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 2050aaa36a97SAlex Deucher 2051aaa36a97SAlex Deucher /*define for ADDR_LO word*/ 2052aaa36a97SAlex Deucher /*define for addr_31_0 field*/ 2053aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 2054aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2055aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 2056aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 2057aaa36a97SAlex Deucher 2058aaa36a97SAlex Deucher /*define for ADDR_HI word*/ 2059aaa36a97SAlex Deucher /*define for addr_63_32 field*/ 2060aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 2061aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2062aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 2063aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 2064aaa36a97SAlex Deucher 2065aaa36a97SAlex Deucher /*define for SRC_DATA_LO word*/ 2066aaa36a97SAlex Deucher /*define for src_data_31_0 field*/ 2067aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 2068aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 2069aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 2070aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 2071aaa36a97SAlex Deucher 2072aaa36a97SAlex Deucher /*define for SRC_DATA_HI word*/ 2073aaa36a97SAlex Deucher /*define for src_data_63_32 field*/ 2074aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 2075aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 2076aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 2077aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 2078aaa36a97SAlex Deucher 2079aaa36a97SAlex Deucher /*define for CMP_DATA_LO word*/ 2080aaa36a97SAlex Deucher /*define for cmp_data_31_0 field*/ 2081aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 2082aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 2083aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 2084aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 2085aaa36a97SAlex Deucher 2086aaa36a97SAlex Deucher /*define for CMP_DATA_HI word*/ 2087aaa36a97SAlex Deucher /*define for cmp_data_63_32 field*/ 2088aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 2089aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 2090aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 2091aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 2092aaa36a97SAlex Deucher 2093aaa36a97SAlex Deucher /*define for LOOP_INTERVAL word*/ 2094aaa36a97SAlex Deucher /*define for loop_interval field*/ 2095aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 2096aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 2097aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 2098aaa36a97SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 2099aaa36a97SAlex Deucher 2100aaa36a97SAlex Deucher 2101aaa36a97SAlex Deucher /* 2102aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 2103aaa36a97SAlex Deucher */ 2104aaa36a97SAlex Deucher 2105aaa36a97SAlex Deucher /*define for HEADER word*/ 2106aaa36a97SAlex Deucher /*define for op field*/ 2107aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 2108aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 2109aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 2110aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 2111aaa36a97SAlex Deucher 2112aaa36a97SAlex Deucher /*define for sub_op field*/ 2113aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 2114aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 2115aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 2116aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 2117aaa36a97SAlex Deucher 2118aaa36a97SAlex Deucher /*define for INIT_DATA_LO word*/ 2119aaa36a97SAlex Deucher /*define for init_data_31_0 field*/ 2120aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 2121aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 2122aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 2123aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 2124aaa36a97SAlex Deucher 2125aaa36a97SAlex Deucher /*define for INIT_DATA_HI word*/ 2126aaa36a97SAlex Deucher /*define for init_data_63_32 field*/ 2127aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 2128aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 2129aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 2130aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 2131aaa36a97SAlex Deucher 2132aaa36a97SAlex Deucher 2133aaa36a97SAlex Deucher /* 2134aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 2135aaa36a97SAlex Deucher */ 2136aaa36a97SAlex Deucher 2137aaa36a97SAlex Deucher /*define for HEADER word*/ 2138aaa36a97SAlex Deucher /*define for op field*/ 2139aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 2140aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 2141aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 2142aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 2143aaa36a97SAlex Deucher 2144aaa36a97SAlex Deucher /*define for sub_op field*/ 2145aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 2146aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 2147aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 2148aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 2149aaa36a97SAlex Deucher 2150aaa36a97SAlex Deucher /*define for WRITE_ADDR_LO word*/ 2151aaa36a97SAlex Deucher /*define for write_addr_31_3 field*/ 2152aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 2153aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 2154aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 2155aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 2156aaa36a97SAlex Deucher 2157aaa36a97SAlex Deucher /*define for WRITE_ADDR_HI word*/ 2158aaa36a97SAlex Deucher /*define for write_addr_63_32 field*/ 2159aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 2160aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 2161aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 2162aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 2163aaa36a97SAlex Deucher 2164aaa36a97SAlex Deucher 2165aaa36a97SAlex Deucher /* 2166aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 2167aaa36a97SAlex Deucher */ 2168aaa36a97SAlex Deucher 2169aaa36a97SAlex Deucher /*define for HEADER word*/ 2170aaa36a97SAlex Deucher /*define for op field*/ 2171aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 2172aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 2173aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 2174aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 2175aaa36a97SAlex Deucher 2176aaa36a97SAlex Deucher /*define for sub_op field*/ 2177aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 2178aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 2179aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 2180aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 2181aaa36a97SAlex Deucher 2182aaa36a97SAlex Deucher /*define for WRITE_ADDR_LO word*/ 2183aaa36a97SAlex Deucher /*define for write_addr_31_3 field*/ 2184aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 2185aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 2186aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 2187aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 2188aaa36a97SAlex Deucher 2189aaa36a97SAlex Deucher /*define for WRITE_ADDR_HI word*/ 2190aaa36a97SAlex Deucher /*define for write_addr_63_32 field*/ 2191aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 2192aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 2193aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 2194aaa36a97SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 2195aaa36a97SAlex Deucher 2196aaa36a97SAlex Deucher 2197aaa36a97SAlex Deucher /* 2198aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_TRAP packet 2199aaa36a97SAlex Deucher */ 2200aaa36a97SAlex Deucher 2201aaa36a97SAlex Deucher /*define for HEADER word*/ 2202aaa36a97SAlex Deucher /*define for op field*/ 2203aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_op_offset 0 2204aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 2205aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_op_shift 0 2206aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 2207aaa36a97SAlex Deucher 2208aaa36a97SAlex Deucher /*define for sub_op field*/ 2209aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 2210aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 2211aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 2212aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 2213aaa36a97SAlex Deucher 2214aaa36a97SAlex Deucher /*define for INT_CONTEXT word*/ 2215aaa36a97SAlex Deucher /*define for int_context field*/ 2216aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 2217aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 2218aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 2219aaa36a97SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 2220aaa36a97SAlex Deucher 2221aaa36a97SAlex Deucher 2222aaa36a97SAlex Deucher /* 2223aaa36a97SAlex Deucher ** Definitions for SDMA_PKT_NOP packet 2224aaa36a97SAlex Deucher */ 2225aaa36a97SAlex Deucher 2226aaa36a97SAlex Deucher /*define for HEADER word*/ 2227aaa36a97SAlex Deucher /*define for op field*/ 2228aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_op_offset 0 2229aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 2230aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_op_shift 0 2231aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 2232aaa36a97SAlex Deucher 2233aaa36a97SAlex Deucher /*define for sub_op field*/ 2234aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 2235aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 2236aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 2237aaa36a97SAlex Deucher #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 2238aaa36a97SAlex Deucher 2239aaa36a97SAlex Deucher 2240aaa36a97SAlex Deucher #endif /* __TONGA_SDMA_PKT_OPEN_H_ */ 2241