1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "vid.h" 27 28 #include "oss/oss_3_0_d.h" 29 #include "oss/oss_3_0_sh_mask.h" 30 31 #include "bif/bif_5_1_d.h" 32 #include "bif/bif_5_1_sh_mask.h" 33 34 /* 35 * Interrupts 36 * Starting with r6xx, interrupts are handled via a ring buffer. 37 * Ring buffers are areas of GPU accessible memory that the GPU 38 * writes interrupt vectors into and the host reads vectors out of. 39 * There is a rptr (read pointer) that determines where the 40 * host is currently reading, and a wptr (write pointer) 41 * which determines where the GPU has written. When the 42 * pointers are equal, the ring is idle. When the GPU 43 * writes vectors to the ring buffer, it increments the 44 * wptr. When there is an interrupt, the host then starts 45 * fetching commands and processing them until the pointers are 46 * equal again at which point it updates the rptr. 47 */ 48 49 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev); 50 51 /** 52 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer 53 * 54 * @adev: amdgpu_device pointer 55 * 56 * Enable the interrupt ring buffer (VI). 57 */ 58 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) 59 { 60 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 61 62 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 64 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 65 adev->irq.ih.enabled = true; 66 } 67 68 /** 69 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer 70 * 71 * @adev: amdgpu_device pointer 72 * 73 * Disable the interrupt ring buffer (VI). 74 */ 75 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) 76 { 77 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 78 79 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 81 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 82 /* set rptr, wptr to 0 */ 83 WREG32(mmIH_RB_RPTR, 0); 84 WREG32(mmIH_RB_WPTR, 0); 85 adev->irq.ih.enabled = false; 86 adev->irq.ih.rptr = 0; 87 } 88 89 /** 90 * tonga_ih_irq_init - init and enable the interrupt ring 91 * 92 * @adev: amdgpu_device pointer 93 * 94 * Allocate a ring buffer for the interrupt controller, 95 * enable the RLC, disable interrupts, enable the IH 96 * ring buffer and enable it (VI). 97 * Called at device load and reume. 98 * Returns 0 for success, errors for failure. 99 */ 100 static int tonga_ih_irq_init(struct amdgpu_device *adev) 101 { 102 int rb_bufsz; 103 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; 104 u64 wptr_off; 105 106 /* disable irqs */ 107 tonga_ih_disable_interrupts(adev); 108 109 /* setup interrupt control */ 110 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 111 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 112 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 113 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 114 */ 115 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 116 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 118 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 119 120 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 121 if (adev->irq.ih.use_bus_addr) 122 WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); 123 else 124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 125 126 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 127 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 129 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 132 133 if (adev->irq.msi_enabled) 134 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 135 136 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 137 138 /* set the writeback address whether it's enabled or not */ 139 if (adev->irq.ih.use_bus_addr) 140 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); 141 else 142 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 143 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); 144 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); 145 146 /* set rptr, wptr to 0 */ 147 WREG32(mmIH_RB_RPTR, 0); 148 WREG32(mmIH_RB_WPTR, 0); 149 150 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); 151 if (adev->irq.ih.use_doorbell) { 152 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 153 OFFSET, adev->irq.ih.doorbell_index); 154 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 155 ENABLE, 1); 156 } else { 157 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 158 ENABLE, 0); 159 } 160 WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 161 162 pci_set_master(adev->pdev); 163 164 /* enable interrupts */ 165 tonga_ih_enable_interrupts(adev); 166 167 return 0; 168 } 169 170 /** 171 * tonga_ih_irq_disable - disable interrupts 172 * 173 * @adev: amdgpu_device pointer 174 * 175 * Disable interrupts on the hw (VI). 176 */ 177 static void tonga_ih_irq_disable(struct amdgpu_device *adev) 178 { 179 tonga_ih_disable_interrupts(adev); 180 181 /* Wait and acknowledge irq */ 182 mdelay(1); 183 } 184 185 /** 186 * tonga_ih_get_wptr - get the IH ring buffer wptr 187 * 188 * @adev: amdgpu_device pointer 189 * 190 * Get the IH ring buffer wptr from either the register 191 * or the writeback memory buffer (VI). Also check for 192 * ring buffer overflow and deal with it. 193 * Used by cz_irq_process(VI). 194 * Returns the value of the wptr. 195 */ 196 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev) 197 { 198 u32 wptr, tmp; 199 200 if (adev->irq.ih.use_bus_addr) 201 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); 202 else 203 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); 204 205 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 207 /* When a ring buffer overflow happen start parsing interrupt 208 * from the last not overwritten vector (wptr + 16). Hopefully 209 * this should allow us to catchup. 210 */ 211 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 212 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); 213 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; 214 tmp = RREG32(mmIH_RB_CNTL); 215 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 216 WREG32(mmIH_RB_CNTL, tmp); 217 } 218 return (wptr & adev->irq.ih.ptr_mask); 219 } 220 221 /** 222 * tonga_ih_prescreen_iv - prescreen an interrupt vector 223 * 224 * @adev: amdgpu_device pointer 225 * 226 * Returns true if the interrupt vector should be further processed. 227 */ 228 static bool tonga_ih_prescreen_iv(struct amdgpu_device *adev) 229 { 230 /* Process all interrupts */ 231 return true; 232 } 233 234 /** 235 * tonga_ih_decode_iv - decode an interrupt vector 236 * 237 * @adev: amdgpu_device pointer 238 * 239 * Decodes the interrupt vector at the current rptr 240 * position and also advance the position. 241 */ 242 static void tonga_ih_decode_iv(struct amdgpu_device *adev, 243 struct amdgpu_iv_entry *entry) 244 { 245 /* wptr/rptr are in bytes! */ 246 u32 ring_index = adev->irq.ih.rptr >> 2; 247 uint32_t dw[4]; 248 249 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 250 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); 251 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); 252 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 253 254 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 255 entry->src_id = dw[0] & 0xff; 256 entry->src_data[0] = dw[1] & 0xfffffff; 257 entry->ring_id = dw[2] & 0xff; 258 entry->vm_id = (dw[2] >> 8) & 0xff; 259 entry->pas_id = (dw[2] >> 16) & 0xffff; 260 261 /* wptr/rptr are in bytes! */ 262 adev->irq.ih.rptr += 16; 263 } 264 265 /** 266 * tonga_ih_set_rptr - set the IH ring buffer rptr 267 * 268 * @adev: amdgpu_device pointer 269 * 270 * Set the IH ring buffer rptr. 271 */ 272 static void tonga_ih_set_rptr(struct amdgpu_device *adev) 273 { 274 if (adev->irq.ih.use_doorbell) { 275 /* XXX check if swapping is necessary on BE */ 276 if (adev->irq.ih.use_bus_addr) 277 adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; 278 else 279 adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; 280 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); 281 } else { 282 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 283 } 284 } 285 286 static int tonga_ih_early_init(void *handle) 287 { 288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 289 int ret; 290 291 ret = amdgpu_irq_add_domain(adev); 292 if (ret) 293 return ret; 294 295 tonga_ih_set_interrupt_funcs(adev); 296 297 return 0; 298 } 299 300 static int tonga_ih_sw_init(void *handle) 301 { 302 int r; 303 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 304 305 r = amdgpu_ih_ring_init(adev, 64 * 1024, true); 306 if (r) 307 return r; 308 309 adev->irq.ih.use_doorbell = true; 310 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH; 311 312 r = amdgpu_irq_init(adev); 313 314 return r; 315 } 316 317 static int tonga_ih_sw_fini(void *handle) 318 { 319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 320 321 amdgpu_irq_fini(adev); 322 amdgpu_ih_ring_fini(adev); 323 amdgpu_irq_remove_domain(adev); 324 325 return 0; 326 } 327 328 static int tonga_ih_hw_init(void *handle) 329 { 330 int r; 331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 332 333 r = tonga_ih_irq_init(adev); 334 if (r) 335 return r; 336 337 return 0; 338 } 339 340 static int tonga_ih_hw_fini(void *handle) 341 { 342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 343 344 tonga_ih_irq_disable(adev); 345 346 return 0; 347 } 348 349 static int tonga_ih_suspend(void *handle) 350 { 351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 352 353 return tonga_ih_hw_fini(adev); 354 } 355 356 static int tonga_ih_resume(void *handle) 357 { 358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 359 360 return tonga_ih_hw_init(adev); 361 } 362 363 static bool tonga_ih_is_idle(void *handle) 364 { 365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 366 u32 tmp = RREG32(mmSRBM_STATUS); 367 368 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 369 return false; 370 371 return true; 372 } 373 374 static int tonga_ih_wait_for_idle(void *handle) 375 { 376 unsigned i; 377 u32 tmp; 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 380 for (i = 0; i < adev->usec_timeout; i++) { 381 /* read MC_STATUS */ 382 tmp = RREG32(mmSRBM_STATUS); 383 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 384 return 0; 385 udelay(1); 386 } 387 return -ETIMEDOUT; 388 } 389 390 static bool tonga_ih_check_soft_reset(void *handle) 391 { 392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 393 u32 srbm_soft_reset = 0; 394 u32 tmp = RREG32(mmSRBM_STATUS); 395 396 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 397 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 398 SOFT_RESET_IH, 1); 399 400 if (srbm_soft_reset) { 401 adev->irq.srbm_soft_reset = srbm_soft_reset; 402 return true; 403 } else { 404 adev->irq.srbm_soft_reset = 0; 405 return false; 406 } 407 } 408 409 static int tonga_ih_pre_soft_reset(void *handle) 410 { 411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 412 413 if (!adev->irq.srbm_soft_reset) 414 return 0; 415 416 return tonga_ih_hw_fini(adev); 417 } 418 419 static int tonga_ih_post_soft_reset(void *handle) 420 { 421 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 422 423 if (!adev->irq.srbm_soft_reset) 424 return 0; 425 426 return tonga_ih_hw_init(adev); 427 } 428 429 static int tonga_ih_soft_reset(void *handle) 430 { 431 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 432 u32 srbm_soft_reset; 433 434 if (!adev->irq.srbm_soft_reset) 435 return 0; 436 srbm_soft_reset = adev->irq.srbm_soft_reset; 437 438 if (srbm_soft_reset) { 439 u32 tmp; 440 441 tmp = RREG32(mmSRBM_SOFT_RESET); 442 tmp |= srbm_soft_reset; 443 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 444 WREG32(mmSRBM_SOFT_RESET, tmp); 445 tmp = RREG32(mmSRBM_SOFT_RESET); 446 447 udelay(50); 448 449 tmp &= ~srbm_soft_reset; 450 WREG32(mmSRBM_SOFT_RESET, tmp); 451 tmp = RREG32(mmSRBM_SOFT_RESET); 452 453 /* Wait a little for things to settle down */ 454 udelay(50); 455 } 456 457 return 0; 458 } 459 460 static int tonga_ih_set_clockgating_state(void *handle, 461 enum amd_clockgating_state state) 462 { 463 return 0; 464 } 465 466 static int tonga_ih_set_powergating_state(void *handle, 467 enum amd_powergating_state state) 468 { 469 return 0; 470 } 471 472 static const struct amd_ip_funcs tonga_ih_ip_funcs = { 473 .name = "tonga_ih", 474 .early_init = tonga_ih_early_init, 475 .late_init = NULL, 476 .sw_init = tonga_ih_sw_init, 477 .sw_fini = tonga_ih_sw_fini, 478 .hw_init = tonga_ih_hw_init, 479 .hw_fini = tonga_ih_hw_fini, 480 .suspend = tonga_ih_suspend, 481 .resume = tonga_ih_resume, 482 .is_idle = tonga_ih_is_idle, 483 .wait_for_idle = tonga_ih_wait_for_idle, 484 .check_soft_reset = tonga_ih_check_soft_reset, 485 .pre_soft_reset = tonga_ih_pre_soft_reset, 486 .soft_reset = tonga_ih_soft_reset, 487 .post_soft_reset = tonga_ih_post_soft_reset, 488 .set_clockgating_state = tonga_ih_set_clockgating_state, 489 .set_powergating_state = tonga_ih_set_powergating_state, 490 }; 491 492 static const struct amdgpu_ih_funcs tonga_ih_funcs = { 493 .get_wptr = tonga_ih_get_wptr, 494 .prescreen_iv = tonga_ih_prescreen_iv, 495 .decode_iv = tonga_ih_decode_iv, 496 .set_rptr = tonga_ih_set_rptr 497 }; 498 499 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) 500 { 501 if (adev->irq.ih_funcs == NULL) 502 adev->irq.ih_funcs = &tonga_ih_funcs; 503 } 504 505 const struct amdgpu_ip_block_version tonga_ih_ip_block = 506 { 507 .type = AMD_IP_BLOCK_TYPE_IH, 508 .major = 3, 509 .minor = 0, 510 .rev = 0, 511 .funcs = &tonga_ih_ip_funcs, 512 }; 513