1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "vid.h" 27 28 #include "oss/oss_3_0_d.h" 29 #include "oss/oss_3_0_sh_mask.h" 30 31 #include "bif/bif_5_1_d.h" 32 #include "bif/bif_5_1_sh_mask.h" 33 34 /* 35 * Interrupts 36 * Starting with r6xx, interrupts are handled via a ring buffer. 37 * Ring buffers are areas of GPU accessible memory that the GPU 38 * writes interrupt vectors into and the host reads vectors out of. 39 * There is a rptr (read pointer) that determines where the 40 * host is currently reading, and a wptr (write pointer) 41 * which determines where the GPU has written. When the 42 * pointers are equal, the ring is idle. When the GPU 43 * writes vectors to the ring buffer, it increments the 44 * wptr. When there is an interrupt, the host then starts 45 * fetching commands and processing them until the pointers are 46 * equal again at which point it updates the rptr. 47 */ 48 49 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev); 50 51 /** 52 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer 53 * 54 * @adev: amdgpu_device pointer 55 * 56 * Enable the interrupt ring buffer (VI). 57 */ 58 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) 59 { 60 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 61 62 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 64 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 65 adev->irq.ih.enabled = true; 66 } 67 68 /** 69 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer 70 * 71 * @adev: amdgpu_device pointer 72 * 73 * Disable the interrupt ring buffer (VI). 74 */ 75 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) 76 { 77 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 78 79 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 81 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 82 /* set rptr, wptr to 0 */ 83 WREG32(mmIH_RB_RPTR, 0); 84 WREG32(mmIH_RB_WPTR, 0); 85 adev->irq.ih.enabled = false; 86 adev->irq.ih.rptr = 0; 87 } 88 89 /** 90 * tonga_ih_irq_init - init and enable the interrupt ring 91 * 92 * @adev: amdgpu_device pointer 93 * 94 * Allocate a ring buffer for the interrupt controller, 95 * enable the RLC, disable interrupts, enable the IH 96 * ring buffer and enable it (VI). 97 * Called at device load and reume. 98 * Returns 0 for success, errors for failure. 99 */ 100 static int tonga_ih_irq_init(struct amdgpu_device *adev) 101 { 102 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; 103 struct amdgpu_ih_ring *ih = &adev->irq.ih; 104 int rb_bufsz; 105 106 /* disable irqs */ 107 tonga_ih_disable_interrupts(adev); 108 109 /* setup interrupt control */ 110 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 111 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 112 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 113 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 114 */ 115 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 116 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 118 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 119 120 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 121 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); 122 123 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 124 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 126 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 129 130 if (adev->irq.msi_enabled) 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 132 133 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 134 135 /* set the writeback address whether it's enabled or not */ 136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 138 139 /* set rptr, wptr to 0 */ 140 WREG32(mmIH_RB_RPTR, 0); 141 WREG32(mmIH_RB_WPTR, 0); 142 143 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); 144 if (adev->irq.ih.use_doorbell) { 145 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 146 OFFSET, adev->irq.ih.doorbell_index); 147 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 148 ENABLE, 1); 149 } else { 150 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 151 ENABLE, 0); 152 } 153 WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 154 155 pci_set_master(adev->pdev); 156 157 /* enable interrupts */ 158 tonga_ih_enable_interrupts(adev); 159 160 return 0; 161 } 162 163 /** 164 * tonga_ih_irq_disable - disable interrupts 165 * 166 * @adev: amdgpu_device pointer 167 * 168 * Disable interrupts on the hw (VI). 169 */ 170 static void tonga_ih_irq_disable(struct amdgpu_device *adev) 171 { 172 tonga_ih_disable_interrupts(adev); 173 174 /* Wait and acknowledge irq */ 175 mdelay(1); 176 } 177 178 /** 179 * tonga_ih_get_wptr - get the IH ring buffer wptr 180 * 181 * @adev: amdgpu_device pointer 182 * 183 * Get the IH ring buffer wptr from either the register 184 * or the writeback memory buffer (VI). Also check for 185 * ring buffer overflow and deal with it. 186 * Used by cz_irq_process(VI). 187 * Returns the value of the wptr. 188 */ 189 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev, 190 struct amdgpu_ih_ring *ih) 191 { 192 u32 wptr, tmp; 193 194 wptr = le32_to_cpu(*ih->wptr_cpu); 195 196 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 197 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 198 /* When a ring buffer overflow happen start parsing interrupt 199 * from the last not overwritten vector (wptr + 16). Hopefully 200 * this should allow us to catchup. 201 */ 202 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 203 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 204 ih->rptr = (wptr + 16) & ih->ptr_mask; 205 tmp = RREG32(mmIH_RB_CNTL); 206 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 207 WREG32(mmIH_RB_CNTL, tmp); 208 } 209 return (wptr & ih->ptr_mask); 210 } 211 212 /** 213 * tonga_ih_decode_iv - decode an interrupt vector 214 * 215 * @adev: amdgpu_device pointer 216 * 217 * Decodes the interrupt vector at the current rptr 218 * position and also advance the position. 219 */ 220 static void tonga_ih_decode_iv(struct amdgpu_device *adev, 221 struct amdgpu_ih_ring *ih, 222 struct amdgpu_iv_entry *entry) 223 { 224 /* wptr/rptr are in bytes! */ 225 u32 ring_index = ih->rptr >> 2; 226 uint32_t dw[4]; 227 228 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 229 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 230 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 231 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 232 233 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 234 entry->src_id = dw[0] & 0xff; 235 entry->src_data[0] = dw[1] & 0xfffffff; 236 entry->ring_id = dw[2] & 0xff; 237 entry->vmid = (dw[2] >> 8) & 0xff; 238 entry->pasid = (dw[2] >> 16) & 0xffff; 239 240 /* wptr/rptr are in bytes! */ 241 ih->rptr += 16; 242 } 243 244 /** 245 * tonga_ih_set_rptr - set the IH ring buffer rptr 246 * 247 * @adev: amdgpu_device pointer 248 * 249 * Set the IH ring buffer rptr. 250 */ 251 static void tonga_ih_set_rptr(struct amdgpu_device *adev, 252 struct amdgpu_ih_ring *ih) 253 { 254 if (ih->use_doorbell) { 255 /* XXX check if swapping is necessary on BE */ 256 *ih->rptr_cpu = ih->rptr; 257 WDOORBELL32(ih->doorbell_index, ih->rptr); 258 } else { 259 WREG32(mmIH_RB_RPTR, ih->rptr); 260 } 261 } 262 263 static int tonga_ih_early_init(void *handle) 264 { 265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 266 int ret; 267 268 ret = amdgpu_irq_add_domain(adev); 269 if (ret) 270 return ret; 271 272 tonga_ih_set_interrupt_funcs(adev); 273 274 return 0; 275 } 276 277 static int tonga_ih_sw_init(void *handle) 278 { 279 int r; 280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 281 282 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true); 283 if (r) 284 return r; 285 286 adev->irq.ih.use_doorbell = true; 287 adev->irq.ih.doorbell_index = adev->doorbell_index.ih; 288 289 r = amdgpu_irq_init(adev); 290 291 return r; 292 } 293 294 static int tonga_ih_sw_fini(void *handle) 295 { 296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 297 298 amdgpu_irq_fini(adev); 299 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 300 amdgpu_irq_remove_domain(adev); 301 302 return 0; 303 } 304 305 static int tonga_ih_hw_init(void *handle) 306 { 307 int r; 308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 309 310 r = tonga_ih_irq_init(adev); 311 if (r) 312 return r; 313 314 return 0; 315 } 316 317 static int tonga_ih_hw_fini(void *handle) 318 { 319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 320 321 tonga_ih_irq_disable(adev); 322 323 return 0; 324 } 325 326 static int tonga_ih_suspend(void *handle) 327 { 328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 329 330 return tonga_ih_hw_fini(adev); 331 } 332 333 static int tonga_ih_resume(void *handle) 334 { 335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 336 337 return tonga_ih_hw_init(adev); 338 } 339 340 static bool tonga_ih_is_idle(void *handle) 341 { 342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 343 u32 tmp = RREG32(mmSRBM_STATUS); 344 345 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 346 return false; 347 348 return true; 349 } 350 351 static int tonga_ih_wait_for_idle(void *handle) 352 { 353 unsigned i; 354 u32 tmp; 355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 356 357 for (i = 0; i < adev->usec_timeout; i++) { 358 /* read MC_STATUS */ 359 tmp = RREG32(mmSRBM_STATUS); 360 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 361 return 0; 362 udelay(1); 363 } 364 return -ETIMEDOUT; 365 } 366 367 static bool tonga_ih_check_soft_reset(void *handle) 368 { 369 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 370 u32 srbm_soft_reset = 0; 371 u32 tmp = RREG32(mmSRBM_STATUS); 372 373 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 374 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 375 SOFT_RESET_IH, 1); 376 377 if (srbm_soft_reset) { 378 adev->irq.srbm_soft_reset = srbm_soft_reset; 379 return true; 380 } else { 381 adev->irq.srbm_soft_reset = 0; 382 return false; 383 } 384 } 385 386 static int tonga_ih_pre_soft_reset(void *handle) 387 { 388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 389 390 if (!adev->irq.srbm_soft_reset) 391 return 0; 392 393 return tonga_ih_hw_fini(adev); 394 } 395 396 static int tonga_ih_post_soft_reset(void *handle) 397 { 398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 399 400 if (!adev->irq.srbm_soft_reset) 401 return 0; 402 403 return tonga_ih_hw_init(adev); 404 } 405 406 static int tonga_ih_soft_reset(void *handle) 407 { 408 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 409 u32 srbm_soft_reset; 410 411 if (!adev->irq.srbm_soft_reset) 412 return 0; 413 srbm_soft_reset = adev->irq.srbm_soft_reset; 414 415 if (srbm_soft_reset) { 416 u32 tmp; 417 418 tmp = RREG32(mmSRBM_SOFT_RESET); 419 tmp |= srbm_soft_reset; 420 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 421 WREG32(mmSRBM_SOFT_RESET, tmp); 422 tmp = RREG32(mmSRBM_SOFT_RESET); 423 424 udelay(50); 425 426 tmp &= ~srbm_soft_reset; 427 WREG32(mmSRBM_SOFT_RESET, tmp); 428 tmp = RREG32(mmSRBM_SOFT_RESET); 429 430 /* Wait a little for things to settle down */ 431 udelay(50); 432 } 433 434 return 0; 435 } 436 437 static int tonga_ih_set_clockgating_state(void *handle, 438 enum amd_clockgating_state state) 439 { 440 return 0; 441 } 442 443 static int tonga_ih_set_powergating_state(void *handle, 444 enum amd_powergating_state state) 445 { 446 return 0; 447 } 448 449 static const struct amd_ip_funcs tonga_ih_ip_funcs = { 450 .name = "tonga_ih", 451 .early_init = tonga_ih_early_init, 452 .late_init = NULL, 453 .sw_init = tonga_ih_sw_init, 454 .sw_fini = tonga_ih_sw_fini, 455 .hw_init = tonga_ih_hw_init, 456 .hw_fini = tonga_ih_hw_fini, 457 .suspend = tonga_ih_suspend, 458 .resume = tonga_ih_resume, 459 .is_idle = tonga_ih_is_idle, 460 .wait_for_idle = tonga_ih_wait_for_idle, 461 .check_soft_reset = tonga_ih_check_soft_reset, 462 .pre_soft_reset = tonga_ih_pre_soft_reset, 463 .soft_reset = tonga_ih_soft_reset, 464 .post_soft_reset = tonga_ih_post_soft_reset, 465 .set_clockgating_state = tonga_ih_set_clockgating_state, 466 .set_powergating_state = tonga_ih_set_powergating_state, 467 }; 468 469 static const struct amdgpu_ih_funcs tonga_ih_funcs = { 470 .get_wptr = tonga_ih_get_wptr, 471 .decode_iv = tonga_ih_decode_iv, 472 .set_rptr = tonga_ih_set_rptr 473 }; 474 475 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) 476 { 477 adev->irq.ih_funcs = &tonga_ih_funcs; 478 } 479 480 const struct amdgpu_ip_block_version tonga_ih_ip_block = 481 { 482 .type = AMD_IP_BLOCK_TYPE_IH, 483 .major = 3, 484 .minor = 0, 485 .rev = 0, 486 .funcs = &tonga_ih_ip_funcs, 487 }; 488